modified caravel_core.mag layout to ensure that all the defaults
blocks got the correct substitutions. Previously, only the
individual defaults blocks layouts were checked and verified.
clean. Provides the netgen report, JSON file, and run-time log of
each. Modified the scripts to tee into the run-time log file and to
add the SPICE netlist of the simple_por. Corrected the simple_por
netlist to make the xhigh resistors non-width-specific, since the
width-specific ID mask is not a GDS layer and cannot be reconstructed
from GDS (at least not with the current tech file in magic).
- set the parasitics log file for each RC corner to be in the directory `./signoff/<design_name>/primetime-signoff/logs/`
- flag if there is any error in reading a spef file
- correct paths of `RAM256` and `RAM128` spef files
- set PT message limit to 1500 instead of the default 100
- report SI bottleneck nets for any design
* reharden: caravel
~ shift caravel_clocking due to change in size
~ change the pr boundary of caravel_power_routing mag file
~ regenarate lef of caravel_power_routing
* update pdn for `caravel_clocking` & `digital_pll`
* added script to update and generate the power routing views
* ~ run update_power_routing_views from the caravel root with prboundary
* fix output message
* added power routing lef, mag and gds
* fix update_power_routing_views saving wrong cell name
* reharden: caravel
~ incorperate pdn changes
~ re-extract spefs
* fix caravel_power_routing views
* fix abs path in maglef views
* fix abs path in mag views
add substcut layers in gpio_control_block and mgmt_protect
* generate a new chip_io gds
* regenerate gpio_control_block due to mag and gds not in sync
* reharden: caravel
~ change config to pass clean routing
~ use updated views of macros
* lvs clean views
* add caravel top-level generated sdf for all corners
* fix absolute path for mgmt_core_wrapper
Co-authored-by: kareem <kareem.farid@efabless.com>
Co-authored-by: Bassant Hassan <bassant.hassan@efabless.com>