mirror of https://github.com/efabless/caravel.git
Final LVS run reports for caravel and caravan top levels, showing LVS
clean. Provides the netgen report, JSON file, and run-time log of each. Modified the scripts to tee into the run-time log file and to add the SPICE netlist of the simple_por. Corrected the simple_por netlist to make the xhigh resistors non-width-specific, since the width-specific ID mask is not a GDS layer and cannot be reconstructed from GDS (at least not with the current tech file in magic).
This commit is contained in:
Tim Edwards
parent
fffc4cb2ee
commit
cca54a2a74
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@ -10,6 +10,7 @@
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# magic layout.
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#
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# Written by Tim Edwards for MPW-7 10/11/2022
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# Updated/fixed 11/08/2022
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#-------------------------------------------------------------------
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echo ${PDK_ROOT:=/usr/share/pdk} > /dev/null
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@ -17,8 +18,10 @@ echo ${PDK:=sky130A} > /dev/null
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# Generate DEF of chip_io
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echo "Generating DEF view of chip_io"
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magic -d OGL -rcfile ${PDK_ROOT}/${PDK}/libs.tech/magic/${PDK}.magicrc << EOF
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magic -dnull -noconsole -rcfile ${PDK_ROOT}/${PDK}/libs.tech/magic/${PDK}.magicrc << EOF
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load chip_io
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select top cell
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expand
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property flatten true
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flatten -doproperty chip_io_flat
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load chip_io_flat
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@ -28,7 +31,20 @@ select top cell
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extract do local
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extract no all
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extract all
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def write chip_io
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# Declare all signals to be SPECIALNETS
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set globals(vccd) 1
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set globals(vssd) 1
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set globals(vddio) 1
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set globals(vssio) 1
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set globals(vdda1) 1
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set globals(vssa1) 1
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set globals(vccd1) 1
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set globals(vssd1) 1
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set globals(vdda2) 1
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set globals(vssa2) 1
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set globals(vccd2) 1
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set globals(vssd2) 1
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def write chip_io -units 400
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quit -noprompt
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EOF
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@ -36,8 +52,10 @@ rm *.ext
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# Generate DEF of chip_io_alt
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echo "Generating DEF view of chip_io_alt"
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magic -d OGL -rcfile ${PDK_ROOT}/${PDK}/libs.tech/magic/${PDK}.magicrc << EOF
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magic -dnull -noconsole -rcfile ${PDK_ROOT}/${PDK}/libs.tech/magic/${PDK}.magicrc << EOF
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load chip_io_alt
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select top cell
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expand
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property flatten true
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flatten -doproperty chip_io_alt_flat
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load chip_io_alt_flat
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@ -47,7 +65,20 @@ select top cell
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extract do local
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extract no all
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extract all
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def write chip_io_alt
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# Declare all signals to be SPECIALNETS
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set globals(vccd) 1
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set globals(vssd) 1
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set globals(vddio) 1
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set globals(vssio) 1
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set globals(vdda1) 1
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set globals(vssa1) 1
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set globals(vccd1) 1
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set globals(vssd1) 1
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set globals(vdda2) 1
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set globals(vssa2) 1
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set globals(vccd2) 1
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set globals(vssd2) 1
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def write chip_io_alt -units 400
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quit -noprompt
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EOF
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@ -88,7 +88,7 @@ EOF
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rm -f *.ext
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fi
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cat > netgenD.tcl << EOF
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cat > netgenE.tcl << EOF
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puts stdout "Reading netlist caravan.spice"
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set circuit1 [readnet spice $CARAVEL_ROOT/spi/lvs/caravan.spice]
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puts stdout "Reading SPICE netlists of I/O"
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@ -128,11 +128,11 @@ readnet verilog $LITEX_ROOT/verilog/gl/mgmt_core_wrapper.v \$circuit2
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puts stdout "Reading top gate-level verilog module"
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readnet verilog $CARAVEL_ROOT/verilog/gl/caravan-signoff.v \$circuit2
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# Cells in management core wrapper (layout) are prefixed with RL_ or KF_
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# Cells in management core wrapper (layout) are prefixed with unique 2-letter prefix
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set cells1 [cells list -all \$circuit1]
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set cells2 [cells list -all \$circuit2]
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foreach cell \$cells1 {
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if {[regexp "\\[A-Z\\]\\[A-Z\\]_(.+)" \$cell match cellname]} {
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if {[regexp {.._(.+)} \$cell match cellname]} {
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if {([lsearch \$cells2 \$cell] < 0) && ([lsearch \$cells2 \$cellname] >= 0) && ([lsearch \$cells1 \$cellname] < 0)} {
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equate classes "\$circuit1 \$cell" "\$circuit2 \$cellname"
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puts stdout "Matching pins of \$cell in circuit 1 and \$cellname in circuit 2"
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@ -140,7 +140,7 @@ foreach cell \$cells1 {
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}
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}
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# Ignore fill cells in standard cell sets that have two-letter prefixes.
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if {[regexp {\\[A-Z\\]\\[A-Z\\]_sky130_fd_sc_[^_]+__fill_[[:digit:]]+} \$cell match]} {
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if {[regexp {.._sky130_fd_sc_[^_]+__fill_[[:digit:]]+} \$cell match]} {
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ignore class "\$circuit1 \$cell"
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}
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}
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@ -152,7 +152,7 @@ EOF
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export NETGEN_COLUMNS=90
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export MAGIC_EXT_USE_GDS=1
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netgen -batch source netgenD.tcl >& caravan_3_lvs.log
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rm netgenD.tcl
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netgen -batch source netgenE.tcl 2>&1 | tee caravan_3_lvs.log
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rm netgenE.tcl
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exit 0
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@ -131,7 +131,7 @@ readnet verilog $CARAVEL_ROOT/verilog/gl/caravel-signoff.v \$circuit2
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set cells1 [cells list -all \$circuit1]
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set cells2 [cells list -all \$circuit2]
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foreach cell \$cells1 {
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if {[regexp "\\[A-Z\\]\\[A-Z\\]_(.+)" \$cell match cellname]} {
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if {[regexp ".._(.+)" \$cell match cellname]} {
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if {([lsearch \$cells2 \$cell] < 0) && ([lsearch \$cells2 \$cellname] >= 0) && ([lsearch \$cells1 \$cellname] < 0)} {
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equate classes "\$circuit1 \$cell" "\$circuit2 \$cellname"
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puts stdout "Matching pins of \$cell in circuit 1 and \$cellname in circuit 2"
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@ -139,7 +139,7 @@ foreach cell \$cells1 {
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}
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}
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# Ignore fill cells in standard cell sets that have two-letter prefixes.
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if {[regexp {\\[A-Z\\]\\[A-Z\\]_sky130_fd_sc_[^_]+__fill_[[:digit:]]+} \$cell match]} {
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if {[regexp {.._sky130_fd_sc_[^_]+__fill_[[:digit:]]+} \$cell match]} {
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ignore class "\$circuit1 \$cell"
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}
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}
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@ -151,7 +151,7 @@ EOF
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export NETGEN_COLUMNS=90
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export MAGIC_EXT_USE_GDS=1
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netgen -batch source netgenD.tcl >& caravel_3_lvs.log
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netgen -batch source netgenD.tcl 2>&1 | tee caravel_3_lvs.log
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rm netgenD.tcl
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exit 0
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File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
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@ -6983,6 +6983,46 @@ B
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Cell pin lists are equivalent.
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Device classes NF_sky130_fd_sc_hd__nor4b_2 and sky130_fd_sc_hd__nor4b_2 are equivalent.
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Circuit 1 cell sky130_fd_pr__cap_mim_m3_1 and Circuit 2 cell sky130_fd_pr__cap_mim_m3_1 are black boxes.
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Warning: Equate pins: cell sky130_fd_pr__cap_mim_m3_1 is a placeholder, treated as a black box.
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Warning: Equate pins: cell sky130_fd_pr__cap_mim_m3_1 is a placeholder, treated as a black box.
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Subcircuit pins:
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Circuit 1: sky130_fd_pr__cap_mim_m3_1 |Circuit 2: sky130_fd_pr__cap_mim_m3_1
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--------------------------------------------------------------------------------------------|--------------------------------------------------------------------------------------------
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1 |1
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2 |2
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-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
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Cell pin lists are equivalent.
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Device classes sky130_fd_pr__cap_mim_m3_1 and sky130_fd_pr__cap_mim_m3_1 are equivalent.
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Circuit 1 cell sky130_fd_pr__cap_mim_m3_2 and Circuit 2 cell sky130_fd_pr__cap_mim_m3_2 are black boxes.
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Warning: Equate pins: cell sky130_fd_pr__cap_mim_m3_2 is a placeholder, treated as a black box.
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Warning: Equate pins: cell sky130_fd_pr__cap_mim_m3_2 is a placeholder, treated as a black box.
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Subcircuit pins:
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Circuit 1: sky130_fd_pr__cap_mim_m3_2 |Circuit 2: sky130_fd_pr__cap_mim_m3_2
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--------------------------------------------------------------------------------------------|--------------------------------------------------------------------------------------------
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1 |1
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2 |2
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-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
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Cell pin lists are equivalent.
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Device classes sky130_fd_pr__cap_mim_m3_2 and sky130_fd_pr__cap_mim_m3_2 are equivalent.
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Circuit 1 cell sky130_fd_pr__res_xhigh_po and Circuit 2 cell sky130_fd_pr__res_xhigh_po are black boxes.
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Warning: Equate pins: cell sky130_fd_pr__res_xhigh_po is a placeholder, treated as a black box.
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Warning: Equate pins: cell sky130_fd_pr__res_xhigh_po is a placeholder, treated as a black box.
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Subcircuit pins:
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Circuit 1: sky130_fd_pr__res_xhigh_po |Circuit 2: sky130_fd_pr__res_xhigh_po
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--------------------------------------------------------------------------------------------|--------------------------------------------------------------------------------------------
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1 |1
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2 |2
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3 |3
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-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
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Cell pin lists are equivalent.
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Device classes sky130_fd_pr__res_xhigh_po and sky130_fd_pr__res_xhigh_po are equivalent.
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Circuit 1 cell sky130_fd_pr__res_generic_pd__hv and Circuit 2 cell sky130_fd_pr__res_generic_pd__hv are black boxes.
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Warning: Equate pins: cell sky130_fd_pr__res_generic_pd__hv is a placeholder, treated as a black box.
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Warning: Equate pins: cell sky130_fd_pr__res_generic_pd__hv is a placeholder, treated as a black box.
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@ -18099,20 +18139,46 @@ flash_io3_di
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-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
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Cell pin lists are equivalent.
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Device classes mgmt_core_wrapper and mgmt_core_wrapper are equivalent.
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Flattening unmatched subcell QJ_sky130_fd_pr__pfet_g5v0d10v5_3YBPVB in circuit simple_por (0)(4 instances)
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Flattening unmatched subcell QJ_sky130_fd_pr__pfet_g5v0d10v5_YUHPXE in circuit simple_por (0)(1 instance)
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Flattening unmatched subcell QJ_sky130_fd_pr__nfet_g5v0d10v5_ZK8HQC in circuit simple_por (0)(1 instance)
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Flattening unmatched subcell QJ_sky130_fd_pr__nfet_g5v0d10v5_PKVMTM in circuit simple_por (0)(1 instance)
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Flattening unmatched subcell QJ_sky130_fd_pr__cap_mim_m3_1_WRT4AW in circuit simple_por (0)(1 instance)
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Flattening unmatched subcell QJ_sky130_fd_pr__pfet_g5v0d10v5_YEUEBV in circuit simple_por (0)(1 instance)
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Flattening unmatched subcell QJ_sky130_fd_pr__pfet_g5v0d10v5_YUHPBG in circuit simple_por (0)(1 instance)
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Flattening unmatched subcell QJ_sky130_fd_pr__cap_mim_m3_2_W5U4AW in circuit simple_por (0)(1 instance)
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Flattening unmatched subcell QJ_sky130_fd_pr__pfet_g5v0d10v5_ZEUEFZ in circuit simple_por (0)(1 instance)
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Flattening unmatched subcell QJ_sky130_fd_pr__res_xhigh_po_0p69_S5N9F3 in circuit simple_por (0)(1 instance)
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Flattening unmatched subcell QJ_sky130_fd_pr__nfet_g5v0d10v5_TGFUGS in circuit simple_por (0)(1 instance)
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Circuit 2 cell simple_por is a black box; will not flatten Circuit 1
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Warning: Equate pins: cell simple_por is a placeholder, treated as a black box.
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Class simple_por (0): Merged 20 parallel devices.
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Class simple_por (0): Merged 24 series devices.
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Subcircuit summary:
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Circuit 1: simple_por |Circuit 2: simple_por
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--------------------------------------------------------------------------------------------|--------------------------------------------------------------------------------------------
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sky130_fd_pr__pfet_g5v0d10v5 (21->8) |sky130_fd_pr__pfet_g5v0d10v5 (8)
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sky130_fd_pr__nfet_g5v0d10v5 (9->3) |sky130_fd_pr__nfet_g5v0d10v5 (3)
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sky130_fd_pr__cap_mim_m3_1 (1) |sky130_fd_pr__cap_mim_m3_1 (1)
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sky130_fd_pr__cap_mim_m3_2 (1) |sky130_fd_pr__cap_mim_m3_2 (1)
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QJ_sky130_fd_sc_hvl__buf_8 (2) |sky130_fd_sc_hvl__buf_8 (2)
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QJ_sky130_fd_sc_hvl__inv_8 (1) |sky130_fd_sc_hvl__inv_8 (1)
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sky130_fd_pr__res_xhigh_po (28->3) |sky130_fd_pr__res_xhigh_po (4->3)
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QJ_sky130_fd_sc_hvl__schmittbuf_1 (1) |sky130_fd_sc_hvl__schmittbuf_1 (1)
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Number of devices: 20 |Number of devices: 20
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Number of nets: 17 |Number of nets: 17
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-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
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Netlists match uniquely.
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Subcircuit pins:
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Circuit 1: simple_por |Circuit 2: simple_por
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--------------------------------------------------------------------------------------------|--------------------------------------------------------------------------------------------
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vdd3v3 |vdd3v3
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vdd1v8 |vdd1v8
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porb_h |porb_h
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por_l |por_l
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porb_l |porb_l
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vss1v8 |vss1v8
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por_l |por_l
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vss3v3 |vss3v3
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vdd3v3 |vdd3v3
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vss1v8 |vss1v8
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vdd1v8 |vdd1v8
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-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
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Cell pin lists are equivalent.
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Device classes simple_por and simple_por are equivalent.
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File diff suppressed because it is too large
Load Diff
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@ -1,3 +1,5 @@
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# NOTE: Hand-edited to change res_xhigh_po_0p69 resistors to res_xhigh_po resistors with W=0.69
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# because the former device does not get recognized when reading from GDS.
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.subckt simple_por vdd3v3 vss3v3 porb_h porb_l por_l vdd1v8 vss1v8
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*.iopin vdd3v3
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*.iopin vss3v3
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@ -14,14 +16,16 @@ XM1 net3 net7 net5 vdd3v3 sky130_fd_pr__pfet_g5v0d10v5 L=0.8 W=2 nf=1 ad='int((n
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XM2 net2 net3 vss3v3 vss3v3 sky130_fd_pr__nfet_g5v0d10v5 L=0.8 W=2 nf=1 ad='int((nf+1)/2) * W/nf * 0.29'
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+ as='int((nf+2)/2) * W/nf * 0.29' pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)'
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+ nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=1 m=1
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XR1 net4 vdd3v3 vss3v3 sky130_fd_pr__res_xhigh_po_0p69 L=500 mult=1 m=1
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# XR1 net4 vdd3v3 vss3v3 sky130_fd_pr__res_xhigh_po_0p69 L=500 mult=1 m=1
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XR1 net4 vdd3v3 vss3v3 sky130_fd_pr__res_xhigh_po W=0.69 L=500 mult=1 m=1
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XM4 net5 net6 vdd3v3 vdd3v3 sky130_fd_pr__pfet_g5v0d10v5 L=0.8 W=2 nf=1 ad='int((nf+1)/2) * W/nf * 0.29'
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+ as='int((nf+2)/2) * W/nf * 0.29' pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)'
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+ nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=1 m=1
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XM5 net3 net3 vss3v3 vss3v3 sky130_fd_pr__nfet_g5v0d10v5 L=0.8 W=14 nf=7 ad='int((nf+1)/2) * W/nf * 0.29'
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+ as='int((nf+2)/2) * W/nf * 0.29' pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)'
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+ nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=1 m=1
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XR2 vss3v3 net4 vss3v3 sky130_fd_pr__res_xhigh_po_0p69 L=150 mult=1 m=1
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# XR2 vss3v3 net4 vss3v3 sky130_fd_pr__res_xhigh_po_0p69 L=150 mult=1 m=1
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XR2 vss3v3 net4 vss3v3 sky130_fd_pr__res_xhigh_po W=0.69 L=150 mult=1 m=1
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XM7 net2 net2 net1 vdd3v3 sky130_fd_pr__pfet_g5v0d10v5 L=0.8 W=2 nf=1 ad='int((nf+1)/2) * W/nf * 0.29'
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+ as='int((nf+2)/2) * W/nf * 0.29' pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)'
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+ nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=1 m=1
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@ -43,7 +47,8 @@ XM12 net8 net1 vdd3v3 vdd3v3 sky130_fd_pr__pfet_g5v0d10v5 L=0.8 W=2 nf=1 ad='int
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XM13 net9 net2 net8 vdd3v3 sky130_fd_pr__pfet_g5v0d10v5 L=0.8 W=2 nf=1 ad='int((nf+1)/2) * W/nf * 0.29'
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+ as='int((nf+2)/2) * W/nf * 0.29' pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)'
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+ nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=1 m=1
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XR3 vss3v3 vss3v3 vss3v3 sky130_fd_pr__res_xhigh_po_0p69 L=25 mult=2 m=2
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# XR3 vss3v3 vss3v3 vss3v3 sky130_fd_pr__res_xhigh_po_0p69 L=25 mult=2 m=2
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XR3 vss3v3 vss3v3 vss3v3 sky130_fd_pr__res_xhigh_po W=0.69 L=25 mult=2 m=2
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x2 net10 vss3v3 vss3v3 vdd3v3 vdd3v3 porb_h sky130_fd_sc_hvl__buf_8
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x3 net10 vss1v8 vss1v8 vdd1v8 vdd1v8 porb_l sky130_fd_sc_hvl__buf_8
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x4 net10 vss1v8 vss1v8 vdd1v8 vdd1v8 por_l sky130_fd_sc_hvl__inv_8
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