mirror of https://github.com/efabless/caravel.git
update caravan STA logs
This commit is contained in:
Passant
parent
9f75ca7542
commit
542582a7b2
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@ -61,7 +61,7 @@ if {\
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# -filter is supported by PT but not in the read_sdc
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# add max_tran constraint as the default max_tran of the ss hd SCL is 10 so the violations are not caught in ss corners
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# apply the constraint to hd cells at the ss corner on caravel/caravan
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if {$::env(PROC_CORNER) == "s" & $::env(DESIGN) == "caravel" | $::env(DESIGN) == "caravan" } {
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if { $::env(DESIGN) == "caravel" | $::env(DESIGN) == "caravan" & $::env(PROC_CORNER) == "s" } {
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set max_tran 1.5
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puts "\[INFO\]: Setting maximum transition of HD cells in slow process corner to: $max_tran"
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puts "For HD cells in the hierarchy of $::env(DESIGN)"
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@ -15757,8 +15757,8 @@ Warning: Line 171, Cell 'sky130_ef_io__vssd_lvc_clamped_pad', pin 'AMUXBUS_B', T
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Technology library 'sky130_ef_io__vssd_lvc_clamped_pad_ff_n40C_1v95_5v50' read successfully
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Loading verilog file '/home/passant/caravel_mgmt_soc_litex/verilog/gl/RAM128.v'
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Loading db file '/home/passant/caravel/scripts/pt_libs/scs130hd_ff_1.95v_-40C.lib'
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Loading verilog file '/home/passant/caravel_mgmt_soc_litex/verilog/gl/mgmt_core_wrapper.v'
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Loading verilog file '/home/passant/caravel_mgmt_soc_litex/verilog/gl/RAM256.v'
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Loading verilog file '/home/passant/caravel_mgmt_soc_litex/verilog/gl/mgmt_core_wrapper.v'
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Loading verilog file '/home/passant/caravel/verilog/gl/mgmt_protect.v'
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Loading verilog file '/home/passant/caravel/verilog/gl/housekeeping.v'
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Loading verilog file '/home/passant/caravel/verilog/gl/caravel.v'
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@ -15790,27 +15790,27 @@ Loading verilog file '/home/passant/caravel/verilog/gl/gpio_logic_high.v'
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Loading verilog file '/home/passant/caravel/verilog/gl/xres_buf.v'
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Loading verilog file '/home/passant/caravel/verilog/gl/constant_block.v'
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Loading verilog file '/home/passant/caravel/verilog/gl/mgmt_protect_hv.v'
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Loading db file '/tmp/_pt1rIae5IC/1.db'
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Loading db file '/tmp/_pt1ryPnFoJ/1.db'
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Loading db file '/home/passant/caravel/scripts/pt_libs/scs130hvl_ff_5.5v_-40C.lib'
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Loading db file '/tmp/_pt1rfQMAfm/1.db'
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Loading db file '/tmp/_pt1ro9YQuB/1.db'
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Loading db file '/home/passant/caravel/scripts/pt_libs/scs130hvl_ff_5.5v_lowhv_5.5v_lv_1.95v_-40C.lib'
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Loading db file '/tmp/_pt1r4LPMTn/1.db'
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Loading db file '/tmp/_pt1re6W1QL/1.db'
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Loading db file '/home/passant/OpenLane/pdks/sky130A/libs.ref/sky130_fd_io/lib/sky130_fd_io__top_xres4v2_ff_ff_n40C_1v95_5v50.lib'
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Loading db file '/tmp/_pt1rXwHz1v/1.db'
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Loading db file '/tmp/_pt1ryo6lK2/1.db'
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Loading db file '/home/passant/OpenLane/pdks/sky130A/libs.ref/sky130_fd_io/lib/sky130_ef_io__gpiov2_pad_wrapped_ff_ff_n40C_1v95_5v50.lib'
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Loading db file '/tmp/_pt1rC3sZmc/1.db'
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Loading db file '/tmp/_pt1ro43sTR/1.db'
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Loading db file '/home/passant/OpenLane/pdks/sky130A/libs.ref/sky130_fd_io/lib/sky130_ef_io__vccd_lvc_clamped_pad_ff_n40C_1v95_5v50_5v50.lib'
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Loading db file '/tmp/_pt1rVSTizj/1.db'
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Loading db file '/tmp/_pt1ryiRyW7/1.db'
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Loading db file '/home/passant/OpenLane/pdks/sky130A/libs.ref/sky130_fd_io/lib/sky130_ef_io__vdda_hvc_clamped_pad_ff_n40C_1v95_5v50_5v50.lib'
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Loading db file '/tmp/_pt1rGLwFuy/1.db'
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Loading db file '/tmp/_pt1ri0G3Jv/1.db'
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Loading db file '/home/passant/OpenLane/pdks/sky130A/libs.ref/sky130_fd_io/lib/sky130_ef_io__vssa_hvc_clamped_pad_ff_n40C_1v95_5v50_5v50.lib'
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Loading db file '/tmp/_pt1rbsvwbR/1.db'
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Loading db file '/tmp/_pt1r0QG9iX/1.db'
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Loading db file '/home/passant/OpenLane/pdks/sky130A/libs.ref/sky130_fd_io/lib/sky130_ef_io__vssd_lvc_clamped3_pad_ff_n40C_1v95_5v50.lib'
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Loading db file '/tmp/_pt1rE3q3Dd/1.db'
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Loading db file '/tmp/_pt1raPzaEs/1.db'
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Loading db file '/home/passant/OpenLane/pdks/sky130A/libs.ref/sky130_fd_io/lib/sky130_ef_io__vccd_lvc_clamped3_pad_ff_n40C_1v95_5v50_5v50.lib'
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Loading db file '/tmp/_pt1rP0PlRD/1.db'
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Loading db file '/tmp/_pt1rO7fAK1/1.db'
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Loading db file '/home/passant/OpenLane/pdks/sky130A/libs.ref/sky130_fd_io/lib/sky130_ef_io__vssd_lvc_clamped_pad_ff_n40C_1v95_5v50.lib'
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Loading db file '/tmp/_pt1rGsyVO7/1.db'
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Loading db file '/tmp/_pt1rwGClCE/1.db'
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Linking design caravan...
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Warning: Unable to resolve reference to 'sky130_fd_sc_hd__fill_1' in 'caravan'. (LNK-005)
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Warning: Unable to resolve reference to 'sky130_fd_sc_hd__tapvpwrvgnd_1' in 'caravan'. (LNK-005)
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@ -16002,8 +16002,6 @@ Warning: Creating 'clock' on a hierarchical pin 'housekeeping/serial_load'. (UIT
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[INFO]: Input transition range: 1 : 4
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[INFO]: Setting derate factor to: 3.75 %
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1
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[INFO]: Setting maximum transition of HD cells in slow process corner to: 1.5
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For HD cells in the hierarchy of caravan
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Information: Checked out license 'PrimeTime-SI' (PT-019)
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Information: Log for 'read_parasitics command' will be generated in 'parasitics_command.log'. (PARA-107)
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Error: All instance paths in the -path option should correspond to valid and same sub-design. (PARA-097)
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@ -16117,25 +16115,25 @@ Warning: Conflicted logic driving pin padframe/flash_io1_pad/DM[1], setting reso
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Warning: Conflicted logic driving pin padframe/flash_io1_pad/DM[2], setting resolved logic value 1 on pin padframe/flash_io1_pad/DM[2]. (PTE-042)
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Warning: No clock-gating check is inferred for clock hkspi_clk at pins gpio_control_in_1[1]/_065_/A2 and gpio_control_in_1[1]/_065_/A1 of cell gpio_control_in_1[1]/_065_. (PTE-060)
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Warning: No clock-gating check is inferred for clock hkspi_clk at pins gpio_control_in_1[1]/_065_/B1 and gpio_control_in_1[1]/_065_/A1 of cell gpio_control_in_1[1]/_065_. (PTE-060)
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Warning: No clock-gating check is inferred for clock clk at pins clock_ctrl/_205_/A1 and clock_ctrl/_205_/A0 of cell clock_ctrl/_205_. (PTE-060)
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Warning: No clock-gating check is inferred for clock clk at pins clock_ctrl/_205_/S and clock_ctrl/_205_/A0 of cell clock_ctrl/_205_. (PTE-060)
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Warning: No clock-gating check is inferred for clock hkspi_clk at pins housekeeping/_3927_/A0 and housekeeping/_3927_/A1 of cell housekeeping/_3927_. (PTE-060)
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Warning: No clock-gating check is inferred for clock hkspi_clk at pins housekeeping/_3927_/S and housekeeping/_3927_/A1 of cell housekeeping/_3927_. (PTE-060)
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Warning: No clock-gating check is inferred for clock hkspi_clk at pins housekeeping/_3945_/A0 and housekeeping/_3945_/A1 of cell housekeeping/_3945_. (PTE-060)
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Warning: No clock-gating check is inferred for clock hkspi_clk at pins housekeeping/_3945_/S and housekeeping/_3945_/A1 of cell housekeeping/_3945_. (PTE-060)
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Warning: No clock-gating check is inferred for clock hkspi_clk at pins gpio_control_in_1[1]/_066_/A1 and gpio_control_in_1[1]/_066_/A2 of cell gpio_control_in_1[1]/_066_. (PTE-060)
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Warning: No clock-gating check is inferred for clock hkspi_clk at pins gpio_control_in_1[1]/_066_/B1 and gpio_control_in_1[1]/_066_/A2 of cell gpio_control_in_1[1]/_066_. (PTE-060)
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Warning: No clock-gating check is inferred for clock clk at pins clock_ctrl/_206_/A1 and clock_ctrl/_206_/A0 of cell clock_ctrl/_206_. (PTE-060)
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Warning: No clock-gating check is inferred for clock clk at pins clock_ctrl/_206_/S and clock_ctrl/_206_/A0 of cell clock_ctrl/_206_. (PTE-060)
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Warning: No clock-gating check is inferred for clock hkspi_clk at pins housekeeping/_3942_/A1 and housekeeping/_3942_/B2 of cell housekeeping/_3942_. (PTE-060)
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Warning: No clock-gating check is inferred for clock hkspi_clk at pins housekeeping/_3942_/A2 and housekeeping/_3942_/B2 of cell housekeeping/_3942_. (PTE-060)
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Warning: No clock-gating check is inferred for clock hkspi_clk at pins housekeeping/_3942_/B1 and housekeeping/_3942_/B2 of cell housekeeping/_3942_. (PTE-060)
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Warning: No clock-gating check is inferred for clock clk at pins clock_ctrl/_206_/A1 and clock_ctrl/_206_/A0 of cell clock_ctrl/_206_. (PTE-060)
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Warning: No clock-gating check is inferred for clock clk at pins clock_ctrl/_206_/S and clock_ctrl/_206_/A0 of cell clock_ctrl/_206_. (PTE-060)
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Warning: No clock-gating check is inferred for clock clk at pins clock_ctrl/_205_/A1 and clock_ctrl/_205_/A0 of cell clock_ctrl/_205_. (PTE-060)
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Warning: No clock-gating check is inferred for clock clk at pins clock_ctrl/_205_/S and clock_ctrl/_205_/A0 of cell clock_ctrl/_205_. (PTE-060)
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Warning: No clock-gating check is inferred for clock hkspi_clk at pins gpio_control_in_1[1]/_066_/A1 and gpio_control_in_1[1]/_066_/A2 of cell gpio_control_in_1[1]/_066_. (PTE-060)
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Warning: No clock-gating check is inferred for clock hkspi_clk at pins gpio_control_in_1[1]/_066_/B1 and gpio_control_in_1[1]/_066_/A2 of cell gpio_control_in_1[1]/_066_. (PTE-060)
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Warning: No clock-gating check is inferred for clock hkspi_clk at pins housekeeping/_3945_/A0 and housekeeping/_3945_/A1 of cell housekeeping/_3945_. (PTE-060)
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Warning: No clock-gating check is inferred for clock hkspi_clk at pins housekeeping/_3945_/S and housekeeping/_3945_/A1 of cell housekeeping/_3945_. (PTE-060)
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Information: Inferring 1 clock-gating checks. (PTE-017)
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Warning: The drive-resistance for the timing arc (sky130_fd_sc_hd__ff_1.95v_-40C/sky130_fd_sc_hd__buf_16) gpio_control_in_1a[2]/output6/A-->X (min rising & falling positive_unate) is much less than the network impedance to ground; PrimeTime has adjusted the drive-resistance to improve accuracy. (RC-009)
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Warning: The drive-resistance for the timing arc (sky130_fd_sc_hd__ff_1.95v_-40C/sky130_fd_sc_hd__buf_16) gpio_control_in_1a[2]/output6/A-->X (max rising & falling positive_unate) is much less than the network impedance to ground; PrimeTime has adjusted the drive-resistance to improve accuracy. (RC-009)
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Warning: The drive-resistance for the timing arc (sky130_fd_sc_hd__ff_1.95v_-40C/sky130_fd_sc_hd__dfxtp_4) soc/_28655_/CLK-->Q (min rising & falling rising_edge) is much less than the network impedance to ground; PrimeTime has adjusted the drive-resistance to improve accuracy. (RC-009)
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Warning: The drive-resistance for the timing arc (sky130_fd_sc_hd__ff_1.95v_-40C/sky130_fd_sc_hd__dfxtp_4) soc/_28652_/CLK-->Q (min rising & falling rising_edge) is much less than the network impedance to ground; PrimeTime has adjusted the drive-resistance to improve accuracy. (RC-009)
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Warning: The drive-resistance for the timing arc (sky130_fd_sc_hd__ff_1.95v_-40C/sky130_fd_sc_hd__dfxtp_4) soc/_28655_/CLK-->Q (max rising & falling rising_edge) is much less than the network impedance to ground; PrimeTime has adjusted the drive-resistance to improve accuracy. (RC-009)
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Warning: The drive-resistance for the timing arc (sky130_fd_sc_hd__ff_1.95v_-40C/sky130_fd_sc_hd__dfxtp_4) soc/_28652_/CLK-->Q (min rising & falling rising_edge) is much less than the network impedance to ground; PrimeTime has adjusted the drive-resistance to improve accuracy. (RC-009)
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Warning: The drive-resistance for the timing arc (sky130_fd_sc_hd__ff_1.95v_-40C/sky130_fd_sc_hd__dfxtp_4) soc/_28652_/CLK-->Q (max rising & falling rising_edge) is much less than the network impedance to ground; PrimeTime has adjusted the drive-resistance to improve accuracy. (RC-009)
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Warning: The drive-resistance for the timing arc (sky130_fd_sc_hd__ff_1.95v_-40C/sky130_fd_sc_hd__dfxtp_4) soc/_28662_/CLK-->Q (min rising & falling rising_edge) is much less than the network impedance to ground; PrimeTime has adjusted the drive-resistance to improve accuracy. (RC-009)
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Warning: The drive-resistance for the timing arc (sky130_fd_sc_hd__ff_1.95v_-40C/sky130_fd_sc_hd__dfxtp_4) soc/_28662_/CLK-->Q (max rising & falling rising_edge) is much less than the network impedance to ground; PrimeTime has adjusted the drive-resistance to improve accuracy. (RC-009)
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@ -16144,8 +16142,8 @@ Warning: The drive-resistance for the timing arc (sky130_fd_sc_hd__ff_1.95v_-40C
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Warning: The drive-resistance for the timing arc (sky130_fd_sc_hd__ff_1.95v_-40C/sky130_fd_sc_hd__dfxtp_4) soc/_28666_/CLK-->Q (min rising & falling rising_edge) is much less than the network impedance to ground; PrimeTime has adjusted the drive-resistance to improve accuracy. (RC-009)
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Warning: The drive-resistance for the timing arc (sky130_fd_sc_hd__ff_1.95v_-40C/sky130_fd_sc_hd__dfxtp_4) soc/_28666_/CLK-->Q (max rising & falling rising_edge) is much less than the network impedance to ground; PrimeTime has adjusted the drive-resistance to improve accuracy. (RC-009)
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Warning: The drive-resistance for the timing arc (sky130_fd_sc_hd__ff_1.95v_-40C/sky130_fd_sc_hd__dfxtp_4) soc/_28671_/CLK-->Q (min rising & falling rising_edge) is much less than the network impedance to ground; PrimeTime has adjusted the drive-resistance to improve accuracy. (RC-009)
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Warning: The drive-resistance for the timing arc (sky130_fd_sc_hd__ff_1.95v_-40C/sky130_fd_sc_hd__dfxtp_4) soc/_28672_/CLK-->Q (min rising & falling rising_edge) is much less than the network impedance to ground; PrimeTime has adjusted the drive-resistance to improve accuracy. (RC-009)
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Warning: The drive-resistance for the timing arc (sky130_fd_sc_hd__ff_1.95v_-40C/sky130_fd_sc_hd__dfxtp_4) soc/_28671_/CLK-->Q (max rising & falling rising_edge) is much less than the network impedance to ground; PrimeTime has adjusted the drive-resistance to improve accuracy. (RC-009)
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Warning: The drive-resistance for the timing arc (sky130_fd_sc_hd__ff_1.95v_-40C/sky130_fd_sc_hd__dfxtp_4) soc/_28672_/CLK-->Q (min rising & falling rising_edge) is much less than the network impedance to ground; PrimeTime has adjusted the drive-resistance to improve accuracy. (RC-009)
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Warning: The drive-resistance for the timing arc (sky130_fd_sc_hd__ff_1.95v_-40C/sky130_fd_sc_hd__dfxtp_4) soc/_28672_/CLK-->Q (max rising & falling rising_edge) is much less than the network impedance to ground; PrimeTime has adjusted the drive-resistance to improve accuracy. (RC-009)
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Warning: The drive-resistance for the timing arc (sky130_fd_sc_hd__ff_1.95v_-40C/sky130_fd_sc_hd__dfxtp_4) soc/_28648_/CLK-->Q (min rising & falling rising_edge) is much less than the network impedance to ground; PrimeTime has adjusted the drive-resistance to improve accuracy. (RC-009)
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Warning: The drive-resistance for the timing arc (sky130_fd_sc_hd__ff_1.95v_-40C/sky130_fd_sc_hd__dfxtp_4) soc/_28648_/CLK-->Q (max rising & falling rising_edge) is much less than the network impedance to ground; PrimeTime has adjusted the drive-resistance to improve accuracy. (RC-009)
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@ -16178,8 +16176,8 @@ Warning: The drive-resistance for the timing arc (sky130_fd_sc_hd__ff_1.95v_-40C
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Warning: The drive-resistance for the timing arc (sky130_fd_sc_hd__ff_1.95v_-40C/sky130_fd_sc_hd__buf_8) soc/fanout2042/A-->X (min rising & falling positive_unate) is much less than the network impedance to ground; PrimeTime has adjusted the drive-resistance to improve accuracy. (RC-009)
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Warning: The drive-resistance for the timing arc (sky130_fd_sc_hd__ff_1.95v_-40C/sky130_fd_sc_hd__buf_8) soc/fanout2042/A-->X (max rising & falling positive_unate) is much less than the network impedance to ground; PrimeTime has adjusted the drive-resistance to improve accuracy. (RC-009)
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Warning: The drive-resistance for the timing arc (sky130_fd_sc_hd__ff_1.95v_-40C/sky130_fd_sc_hd__buf_12) soc/fanout2059/A-->X (min rising & falling positive_unate) is much less than the network impedance to ground; PrimeTime has adjusted the drive-resistance to improve accuracy. (RC-009)
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Warning: The drive-resistance for the timing arc (sky130_fd_sc_hd__ff_1.95v_-40C/sky130_fd_sc_hd__buf_12) soc/fanout2059/A-->X (max rising & falling positive_unate) is much less than the network impedance to ground; PrimeTime has adjusted the drive-resistance to improve accuracy. (RC-009)
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Warning: The drive-resistance for the timing arc (sky130_fd_sc_hd__ff_1.95v_-40C/sky130_fd_sc_hd__buf_12) soc/fanout2058/A-->X (min rising & falling positive_unate) is much less than the network impedance to ground; PrimeTime has adjusted the drive-resistance to improve accuracy. (RC-009)
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Warning: The drive-resistance for the timing arc (sky130_fd_sc_hd__ff_1.95v_-40C/sky130_fd_sc_hd__buf_12) soc/fanout2059/A-->X (max rising & falling positive_unate) is much less than the network impedance to ground; PrimeTime has adjusted the drive-resistance to improve accuracy. (RC-009)
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Warning: The drive-resistance for the timing arc (sky130_fd_sc_hd__ff_1.95v_-40C/sky130_fd_sc_hd__buf_12) soc/fanout2058/A-->X (max rising & falling positive_unate) is much less than the network impedance to ground; PrimeTime has adjusted the drive-resistance to improve accuracy. (RC-009)
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Warning: The drive-resistance for the timing arc (sky130_fd_sc_hd__ff_1.95v_-40C/sky130_fd_sc_hd__buf_12) soc/fanout2065/A-->X (min rising & falling positive_unate) is much less than the network impedance to ground; PrimeTime has adjusted the drive-resistance to improve accuracy. (RC-009)
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Warning: The drive-resistance for the timing arc (sky130_fd_sc_hd__ff_1.95v_-40C/sky130_fd_sc_hd__buf_12) soc/fanout2065/A-->X (max rising & falling positive_unate) is much less than the network impedance to ground; PrimeTime has adjusted the drive-resistance to improve accuracy. (RC-009)
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@ -16238,7 +16236,7 @@ Information: Number of nets evaluated in the previous iteration: 59945. (XTALK-1
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Report : write_sdf /home/passant/caravel/signoff/caravan/primetime-signoff/sdf/max/caravan.ff.sdf
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Design : caravan
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Version: T-2022.03-SP3
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Date : Sun Oct 30 07:25:12 2022
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Date : Mon Oct 31 14:25:26 2022
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****************************************
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Warning: Clock 'hkspi_clk'has source on hierachical pin 'housekeeping/mgmt_gpio_in[4]'. Consider moving to: gpio_control_in_1a[2]/output6/X
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@ -16262,6 +16260,10 @@ Warning: The drive-resistance for the timing arc (sky130_fd_sc_hd__ff_1.95v_-40C
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Warning: The drive-resistance for the timing arc (sky130_fd_sc_hd__ff_1.95v_-40C/sky130_fd_sc_hd__buf_16) gpio_control_in_1a[2]/output6/A-->X (max rising & falling positive_unate) is much less than the network impedance to ground; PrimeTime has adjusted the drive-resistance to improve accuracy. (RC-009)
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Warning: The drive-resistance for the timing arc (sky130_fd_sc_hd__ff_1.95v_-40C/sky130_fd_sc_hd__buf_12) soc/input213/A-->X (min rising positive_unate) is much less than the network impedance to ground; PrimeTime has adjusted the drive-resistance to improve accuracy. (RC-009)
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Warning: The drive-resistance for the timing arc (sky130_fd_sc_hd__ff_1.95v_-40C/sky130_fd_sc_hd__buf_12) soc/input213/A-->X (min rising positive_unate) is much less than the network impedance to ground; PrimeTime has adjusted the drive-resistance to improve accuracy. (RC-009)
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Warning: The drive-resistance for the timing arc (sky130_fd_sc_hd__ff_1.95v_-40C/sky130_fd_sc_hd__buf_12) housekeeping/output244/A-->X (min rising & falling positive_unate) is much less than the network impedance to ground; PrimeTime has adjusted the drive-resistance to improve accuracy. (RC-009)
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Warning: The drive-resistance for the timing arc (sky130_fd_sc_hd__ff_1.95v_-40C/sky130_fd_sc_hd__buf_12) housekeeping/output244/A-->X (max rising & falling positive_unate) is much less than the network impedance to ground; PrimeTime has adjusted the drive-resistance to improve accuracy. (RC-009)
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Warning: The drive-resistance for the timing arc (sky130_fd_sc_hd__ff_1.95v_-40C/sky130_fd_sc_hd__buf_12) housekeeping/output245/A-->X (min rising & falling positive_unate) is much less than the network impedance to ground; PrimeTime has adjusted the drive-resistance to improve accuracy. (RC-009)
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Warning: The drive-resistance for the timing arc (sky130_fd_sc_hd__ff_1.95v_-40C/sky130_fd_sc_hd__buf_12) housekeeping/output245/A-->X (max rising & falling positive_unate) is much less than the network impedance to ground; PrimeTime has adjusted the drive-resistance to improve accuracy. (RC-009)
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Warning: The drive-resistance for the timing arc (sky130_fd_sc_hd__ff_1.95v_-40C/sky130_fd_sc_hd__buf_12) housekeeping/input58/A-->X (min rising & falling positive_unate) is much less than the network impedance to ground; PrimeTime has adjusted the drive-resistance to improve accuracy. (RC-009)
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||||
Warning: The drive-resistance for the timing arc (sky130_fd_sc_hd__ff_1.95v_-40C/sky130_fd_sc_hd__buf_12) housekeeping/input58/A-->X (max rising & falling positive_unate) is much less than the network impedance to ground; PrimeTime has adjusted the drive-resistance to improve accuracy. (RC-009)
|
||||
Warning: The drive-resistance for the timing arc (sky130_fd_sc_hd__ff_1.95v_-40C/sky130_fd_sc_hd__buf_12) housekeeping/output245/A-->X (min rising & falling positive_unate) is much less than the network impedance to ground; PrimeTime has adjusted the drive-resistance to improve accuracy. (RC-009)
|
||||
|
|
@ -16275,10 +16277,6 @@ Warning: The drive-resistance for the timing arc (sky130_fd_sc_hd__ff_1.95v_-40C
|
|||
Warning: The drive-resistance for the timing arc (sky130_fd_sc_hd__ff_1.95v_-40C/sky130_fd_sc_hd__buf_12) soc/wire1964/A-->X (max rising & falling positive_unate) is much less than the network impedance to ground; PrimeTime has adjusted the drive-resistance to improve accuracy. (RC-009)
|
||||
Warning: The drive-resistance for the timing arc (sky130_fd_sc_hd__ff_1.95v_-40C/sky130_fd_sc_hd__buf_12) housekeeping/output245/A-->X (min rising & falling positive_unate) is much less than the network impedance to ground; PrimeTime has adjusted the drive-resistance to improve accuracy. (RC-009)
|
||||
Warning: The drive-resistance for the timing arc (sky130_fd_sc_hd__ff_1.95v_-40C/sky130_fd_sc_hd__buf_12) housekeeping/output245/A-->X (max rising & falling positive_unate) is much less than the network impedance to ground; PrimeTime has adjusted the drive-resistance to improve accuracy. (RC-009)
|
||||
Warning: The drive-resistance for the timing arc (sky130_fd_sc_hd__ff_1.95v_-40C/sky130_fd_sc_hd__buf_12) housekeeping/output244/A-->X (min rising & falling positive_unate) is much less than the network impedance to ground; PrimeTime has adjusted the drive-resistance to improve accuracy. (RC-009)
|
||||
Warning: The drive-resistance for the timing arc (sky130_fd_sc_hd__ff_1.95v_-40C/sky130_fd_sc_hd__buf_12) housekeeping/output244/A-->X (max rising & falling positive_unate) is much less than the network impedance to ground; PrimeTime has adjusted the drive-resistance to improve accuracy. (RC-009)
|
||||
Warning: The drive-resistance for the timing arc (sky130_fd_sc_hd__ff_1.95v_-40C/sky130_fd_sc_hd__buf_12) housekeeping/output245/A-->X (min rising & falling positive_unate) is much less than the network impedance to ground; PrimeTime has adjusted the drive-resistance to improve accuracy. (RC-009)
|
||||
Warning: The drive-resistance for the timing arc (sky130_fd_sc_hd__ff_1.95v_-40C/sky130_fd_sc_hd__buf_12) housekeeping/output245/A-->X (max rising & falling positive_unate) is much less than the network impedance to ground; PrimeTime has adjusted the drive-resistance to improve accuracy. (RC-009)
|
||||
Warning: The drive-resistance for the timing arc (sky130_fd_sc_hd__ff_1.95v_-40C/sky130_fd_sc_hd__buf_12) soc/input213/A-->X (min rising positive_unate) is much less than the network impedance to ground; PrimeTime has adjusted the drive-resistance to improve accuracy. (RC-009)
|
||||
Warning: The drive-resistance for the timing arc (sky130_fd_sc_hd__ff_1.95v_-40C/sky130_fd_sc_hd__buf_12) soc/input213/A-->X (min rising positive_unate) is much less than the network impedance to ground; PrimeTime has adjusted the drive-resistance to improve accuracy. (RC-009)
|
||||
Warning: The drive-resistance for the timing arc (sky130_fd_sc_hd__ff_1.95v_-40C/sky130_fd_sc_hd__buf_12) housekeeping/output245/A-->X (min rising & falling positive_unate) is much less than the network impedance to ground; PrimeTime has adjusted the drive-resistance to improve accuracy. (RC-009)
|
||||
|
|
@ -16293,6 +16291,10 @@ Warning: The drive-resistance for the timing arc (sky130_fd_sc_hd__ff_1.95v_-40C
|
|||
Warning: The drive-resistance for the timing arc (sky130_fd_sc_hd__ff_1.95v_-40C/sky130_fd_sc_hd__buf_16) gpio_control_in_1a[2]/output6/A-->X (max rising & falling positive_unate) is much less than the network impedance to ground; PrimeTime has adjusted the drive-resistance to improve accuracy. (RC-009)
|
||||
Warning: The drive-resistance for the timing arc (sky130_fd_sc_hd__ff_1.95v_-40C/sky130_fd_sc_hd__buf_12) soc/input213/A-->X (max rising positive_unate) is much less than the network impedance to ground; PrimeTime has adjusted the drive-resistance to improve accuracy. (RC-009)
|
||||
Warning: The drive-resistance for the timing arc (sky130_fd_sc_hd__ff_1.95v_-40C/sky130_fd_sc_hd__buf_12) soc/input213/A-->X (max rising positive_unate) is much less than the network impedance to ground; PrimeTime has adjusted the drive-resistance to improve accuracy. (RC-009)
|
||||
Warning: The drive-resistance for the timing arc (sky130_fd_sc_hd__ff_1.95v_-40C/sky130_fd_sc_hd__buf_12) housekeeping/output244/A-->X (min rising & falling positive_unate) is much less than the network impedance to ground; PrimeTime has adjusted the drive-resistance to improve accuracy. (RC-009)
|
||||
Warning: The drive-resistance for the timing arc (sky130_fd_sc_hd__ff_1.95v_-40C/sky130_fd_sc_hd__buf_12) housekeeping/output244/A-->X (max rising & falling positive_unate) is much less than the network impedance to ground; PrimeTime has adjusted the drive-resistance to improve accuracy. (RC-009)
|
||||
Warning: The drive-resistance for the timing arc (sky130_fd_sc_hd__ff_1.95v_-40C/sky130_fd_sc_hd__buf_12) housekeeping/output245/A-->X (min rising & falling positive_unate) is much less than the network impedance to ground; PrimeTime has adjusted the drive-resistance to improve accuracy. (RC-009)
|
||||
Warning: The drive-resistance for the timing arc (sky130_fd_sc_hd__ff_1.95v_-40C/sky130_fd_sc_hd__buf_12) housekeeping/output245/A-->X (max rising & falling positive_unate) is much less than the network impedance to ground; PrimeTime has adjusted the drive-resistance to improve accuracy. (RC-009)
|
||||
Warning: The drive-resistance for the timing arc (sky130_fd_sc_hd__ff_1.95v_-40C/sky130_fd_sc_hd__buf_12) housekeeping/input58/A-->X (min rising & falling positive_unate) is much less than the network impedance to ground; PrimeTime has adjusted the drive-resistance to improve accuracy. (RC-009)
|
||||
Warning: The drive-resistance for the timing arc (sky130_fd_sc_hd__ff_1.95v_-40C/sky130_fd_sc_hd__buf_12) housekeeping/input58/A-->X (max rising & falling positive_unate) is much less than the network impedance to ground; PrimeTime has adjusted the drive-resistance to improve accuracy. (RC-009)
|
||||
Warning: The drive-resistance for the timing arc (sky130_fd_sc_hd__ff_1.95v_-40C/sky130_fd_sc_hd__buf_12) housekeeping/output245/A-->X (min rising & falling positive_unate) is much less than the network impedance to ground; PrimeTime has adjusted the drive-resistance to improve accuracy. (RC-009)
|
||||
|
|
@ -16306,10 +16308,6 @@ Warning: The drive-resistance for the timing arc (sky130_fd_sc_hd__ff_1.95v_-40C
|
|||
Warning: The drive-resistance for the timing arc (sky130_fd_sc_hd__ff_1.95v_-40C/sky130_fd_sc_hd__buf_12) soc/wire1964/A-->X (max rising & falling positive_unate) is much less than the network impedance to ground; PrimeTime has adjusted the drive-resistance to improve accuracy. (RC-009)
|
||||
Warning: The drive-resistance for the timing arc (sky130_fd_sc_hd__ff_1.95v_-40C/sky130_fd_sc_hd__buf_12) housekeeping/output245/A-->X (min rising & falling positive_unate) is much less than the network impedance to ground; PrimeTime has adjusted the drive-resistance to improve accuracy. (RC-009)
|
||||
Warning: The drive-resistance for the timing arc (sky130_fd_sc_hd__ff_1.95v_-40C/sky130_fd_sc_hd__buf_12) housekeeping/output245/A-->X (max rising & falling positive_unate) is much less than the network impedance to ground; PrimeTime has adjusted the drive-resistance to improve accuracy. (RC-009)
|
||||
Warning: The drive-resistance for the timing arc (sky130_fd_sc_hd__ff_1.95v_-40C/sky130_fd_sc_hd__buf_12) housekeeping/output244/A-->X (min rising & falling positive_unate) is much less than the network impedance to ground; PrimeTime has adjusted the drive-resistance to improve accuracy. (RC-009)
|
||||
Warning: The drive-resistance for the timing arc (sky130_fd_sc_hd__ff_1.95v_-40C/sky130_fd_sc_hd__buf_12) housekeeping/output244/A-->X (max rising & falling positive_unate) is much less than the network impedance to ground; PrimeTime has adjusted the drive-resistance to improve accuracy. (RC-009)
|
||||
Warning: The drive-resistance for the timing arc (sky130_fd_sc_hd__ff_1.95v_-40C/sky130_fd_sc_hd__buf_12) housekeeping/output245/A-->X (min rising & falling positive_unate) is much less than the network impedance to ground; PrimeTime has adjusted the drive-resistance to improve accuracy. (RC-009)
|
||||
Warning: The drive-resistance for the timing arc (sky130_fd_sc_hd__ff_1.95v_-40C/sky130_fd_sc_hd__buf_12) housekeeping/output245/A-->X (max rising & falling positive_unate) is much less than the network impedance to ground; PrimeTime has adjusted the drive-resistance to improve accuracy. (RC-009)
|
||||
Information: For model extraction, min_period and min_pulse_width arcs are extracted at the context slew. (MEXT-105)
|
||||
Information: Elapsed time for model extraction: 4 seconds (MEXT-096)
|
||||
Wrote the LIB file /home/passant/caravel/signoff/caravan/primetime-signoff/lib/max/caravan.ff.lib
|
||||
|
|
@ -16317,7 +16315,6 @@ Wrote model to '/home/passant/caravel/signoff/caravan/primetime-signoff/lib/max/
|
|||
Wrote test design to '/home/passant/caravel/signoff/caravan/primetime-signoff/lib/max/caravan.ff_test.db'
|
||||
Information: Elapsed time for lib file writing: 0 seconds (MEXT-096)
|
||||
Information: Defining new variable 'verilog'. (CMD-041)
|
||||
Information: Defining new variable 'max_tran'. (CMD-041)
|
||||
Suppressed Messages Summary:
|
||||
Id Severity Occurrences Suppressed
|
||||
-------------------------------------------------------------------------------
|
||||
|
|
@ -16328,10 +16325,10 @@ RC-009 Warning 764 602
|
|||
LNK-043 Information 190190 190090
|
||||
SVR-2 Information 2 2
|
||||
Total 6 types of messages are suppressed
|
||||
Maximum memory usage for this session: 2795.13 MB
|
||||
CPU usage for this session: 208 seconds
|
||||
Elapsed time for this session: 78 seconds
|
||||
Diagnostics summary: 69 errors, 307 warnings, 124 informationals
|
||||
Maximum memory usage for this session: 2815.26 MB
|
||||
CPU usage for this session: 219 seconds
|
||||
Elapsed time for this session: 82 seconds
|
||||
Diagnostics summary: 69 errors, 307 warnings, 123 informationals
|
||||
|
||||
Thank you for using pt_shell!
|
||||
STA run Passed!
|
||||
|
|
|
|||
|
|
@ -61,7 +61,7 @@ if {\
|
|||
# -filter is supported by PT but not in the read_sdc
|
||||
# add max_tran constraint as the default max_tran of the ss hd SCL is 10 so the violations are not caught in ss corners
|
||||
# apply the constraint to hd cells at the ss corner on caravel/caravan
|
||||
if {$::env(PROC_CORNER) == "s" & $::env(DESIGN) == "caravel" | $::env(DESIGN) == "caravan" } {
|
||||
if { $::env(DESIGN) == "caravel" | $::env(DESIGN) == "caravan" & $::env(PROC_CORNER) == "s" } {
|
||||
set max_tran 1.5
|
||||
puts "\[INFO\]: Setting maximum transition of HD cells in slow process corner to: $max_tran"
|
||||
puts "For HD cells in the hierarchy of $::env(DESIGN)"
|
||||
|
|
@ -5099,9 +5099,9 @@ Warning: Line 171, Cell 'sky130_ef_io__vssd_lvc_clamped_pad', pin 'AMUXBUS_B', T
|
|||
Warning: Line 171, Cell 'sky130_ef_io__vssd_lvc_clamped_pad', pin 'AMUXBUS_B', The pin 'AMUXBUS_B' does not have a internal_power group. (LBDB-607)
|
||||
Technology library 'sky130_ef_io__vssd_lvc_clamped_pad_ss_100C_1v60_3v00' read successfully
|
||||
Loading verilog file '/home/passant/caravel_mgmt_soc_litex/verilog/gl/RAM128.v'
|
||||
Loading verilog file '/home/passant/caravel_mgmt_soc_litex/verilog/gl/mgmt_core_wrapper.v'
|
||||
Loading verilog file '/home/passant/caravel_mgmt_soc_litex/verilog/gl/RAM256.v'
|
||||
Loading db file '/home/passant/caravel/scripts/pt_libs/scs130hd_ss_1.40v_100C.lib'
|
||||
Loading verilog file '/home/passant/caravel_mgmt_soc_litex/verilog/gl/mgmt_core_wrapper.v'
|
||||
Loading verilog file '/home/passant/caravel/verilog/gl/mgmt_protect.v'
|
||||
Loading verilog file '/home/passant/caravel/verilog/gl/housekeeping.v'
|
||||
Loading verilog file '/home/passant/caravel/verilog/gl/caravel.v'
|
||||
|
|
@ -5133,25 +5133,25 @@ Loading verilog file '/home/passant/caravel/verilog/gl/gpio_logic_high.v'
|
|||
Loading verilog file '/home/passant/caravel/verilog/gl/xres_buf.v'
|
||||
Loading verilog file '/home/passant/caravel/verilog/gl/constant_block.v'
|
||||
Loading verilog file '/home/passant/caravel/verilog/gl/mgmt_protect_hv.v'
|
||||
Loading db file '/tmp/_pt1rgosuFQ/1.db'
|
||||
Loading db file '/tmp/_pt1rNGb1Jg/1.db'
|
||||
Loading db file '/home/passant/caravel/scripts/pt_libs/scs130hvl_ss_3.00v_100C.lib'
|
||||
Loading db file '/tmp/_pt1r8lEs9x/1.db'
|
||||
Loading db file '/tmp/_pt1rjzRjNz/1.db'
|
||||
Loading db file '/home/passant/OpenLane/pdks/sky130A/libs.ref/sky130_fd_io/lib/sky130_fd_io__top_xres4v2_ss_ss_100C_1v60_3v00.lib'
|
||||
Loading db file '/tmp/_pt1reSyXLu/1.db'
|
||||
Loading db file '/tmp/_pt1rZevlt7/1.db'
|
||||
Loading db file '/home/passant/OpenLane/pdks/sky130A/libs.ref/sky130_fd_io/lib/sky130_ef_io__gpiov2_pad_wrapped_ss_ss_100C_1v60_3v00.lib'
|
||||
Loading db file '/tmp/_pt1rM51DDw/1.db'
|
||||
Loading db file '/tmp/_pt1rljhMeK/1.db'
|
||||
Loading db file '/home/passant/OpenLane/pdks/sky130A/libs.ref/sky130_fd_io/lib/sky130_ef_io__vccd_lvc_clamped_pad_ss_100C_1v60_3v00_3v00.lib'
|
||||
Loading db file '/tmp/_pt1ruyTYYC/1.db'
|
||||
Loading db file '/tmp/_pt1rpGeMgr/1.db'
|
||||
Loading db file '/home/passant/OpenLane/pdks/sky130A/libs.ref/sky130_fd_io/lib/sky130_ef_io__vdda_hvc_clamped_pad_ss_100C_1v60_3v00_3v00.lib'
|
||||
Loading db file '/tmp/_pt1rMKWewN/1.db'
|
||||
Loading db file '/tmp/_pt1rPneljc/1.db'
|
||||
Loading db file '/home/passant/OpenLane/pdks/sky130A/libs.ref/sky130_fd_io/lib/sky130_ef_io__vssa_hvc_clamped_pad_ss_100C_1v60_3v00_3v00.lib'
|
||||
Loading db file '/tmp/_pt1rgOQ8X1/1.db'
|
||||
Loading db file '/tmp/_pt1rn5BJ70/1.db'
|
||||
Loading db file '/home/passant/OpenLane/pdks/sky130A/libs.ref/sky130_fd_io/lib/sky130_ef_io__vssd_lvc_clamped3_pad_ss_100C_1v60_3v00.lib'
|
||||
Loading db file '/tmp/_pt1r69Jqgk/1.db'
|
||||
Loading db file '/tmp/_pt1rZR5AHT/1.db'
|
||||
Loading db file '/home/passant/OpenLane/pdks/sky130A/libs.ref/sky130_fd_io/lib/sky130_ef_io__vccd_lvc_clamped3_pad_ss_100C_1v60_3v00_3v00.lib'
|
||||
Loading db file '/tmp/_pt1rY3M2mG/1.db'
|
||||
Loading db file '/tmp/_pt1rZil12P/1.db'
|
||||
Loading db file '/home/passant/OpenLane/pdks/sky130A/libs.ref/sky130_fd_io/lib/sky130_ef_io__vssd_lvc_clamped_pad_ss_100C_1v60_3v00.lib'
|
||||
Loading db file '/tmp/_pt1r2kr8g6/1.db'
|
||||
Loading db file '/tmp/_pt1rvS5MaQ/1.db'
|
||||
Linking design caravan...
|
||||
Warning: Unable to resolve reference to 'sky130_fd_sc_hd__fill_1' in 'caravan'. (LNK-005)
|
||||
Warning: Unable to resolve reference to 'sky130_fd_sc_hd__tapvpwrvgnd_1' in 'caravan'. (LNK-005)
|
||||
|
|
@ -5458,21 +5458,21 @@ Warning: Some timing arcs have been disabled for breaking timing loops or becaus
|
|||
Warning: Conflicted logic driving pin padframe/flash_io1_pad/DM[0], setting resolved logic value 0 on pin padframe/flash_io1_pad/DM[0]. (PTE-042)
|
||||
Warning: Conflicted logic driving pin padframe/flash_io1_pad/DM[1], setting resolved logic value 1 on pin padframe/flash_io1_pad/DM[1]. (PTE-042)
|
||||
Warning: Conflicted logic driving pin padframe/flash_io1_pad/DM[2], setting resolved logic value 1 on pin padframe/flash_io1_pad/DM[2]. (PTE-042)
|
||||
Warning: No clock-gating check is inferred for clock clk at pins clock_ctrl/_206_/A1 and clock_ctrl/_206_/A0 of cell clock_ctrl/_206_. (PTE-060)
|
||||
Warning: No clock-gating check is inferred for clock clk at pins clock_ctrl/_206_/S and clock_ctrl/_206_/A0 of cell clock_ctrl/_206_. (PTE-060)
|
||||
Warning: No clock-gating check is inferred for clock hkspi_clk at pins housekeeping/_3927_/A0 and housekeeping/_3927_/A1 of cell housekeeping/_3927_. (PTE-060)
|
||||
Warning: No clock-gating check is inferred for clock hkspi_clk at pins housekeeping/_3927_/S and housekeeping/_3927_/A1 of cell housekeeping/_3927_. (PTE-060)
|
||||
Warning: No clock-gating check is inferred for clock clk at pins clock_ctrl/_206_/A1 and clock_ctrl/_206_/A0 of cell clock_ctrl/_206_. (PTE-060)
|
||||
Warning: No clock-gating check is inferred for clock clk at pins clock_ctrl/_206_/S and clock_ctrl/_206_/A0 of cell clock_ctrl/_206_. (PTE-060)
|
||||
Warning: No clock-gating check is inferred for clock hkspi_clk at pins gpio_control_in_1[1]/_066_/A1 and gpio_control_in_1[1]/_066_/A2 of cell gpio_control_in_1[1]/_066_. (PTE-060)
|
||||
Warning: No clock-gating check is inferred for clock hkspi_clk at pins gpio_control_in_1[1]/_066_/B1 and gpio_control_in_1[1]/_066_/A2 of cell gpio_control_in_1[1]/_066_. (PTE-060)
|
||||
Warning: No clock-gating check is inferred for clock hkspi_clk at pins gpio_control_in_1[1]/_065_/A2 and gpio_control_in_1[1]/_065_/A1 of cell gpio_control_in_1[1]/_065_. (PTE-060)
|
||||
Warning: No clock-gating check is inferred for clock hkspi_clk at pins gpio_control_in_1[1]/_065_/B1 and gpio_control_in_1[1]/_065_/A1 of cell gpio_control_in_1[1]/_065_. (PTE-060)
|
||||
Warning: No clock-gating check is inferred for clock clk at pins clock_ctrl/_205_/A1 and clock_ctrl/_205_/A0 of cell clock_ctrl/_205_. (PTE-060)
|
||||
Warning: No clock-gating check is inferred for clock clk at pins clock_ctrl/_205_/S and clock_ctrl/_205_/A0 of cell clock_ctrl/_205_. (PTE-060)
|
||||
Warning: No clock-gating check is inferred for clock hkspi_clk at pins housekeeping/_3945_/A0 and housekeeping/_3945_/A1 of cell housekeeping/_3945_. (PTE-060)
|
||||
Warning: No clock-gating check is inferred for clock hkspi_clk at pins housekeeping/_3945_/S and housekeeping/_3945_/A1 of cell housekeeping/_3945_. (PTE-060)
|
||||
Warning: No clock-gating check is inferred for clock hkspi_clk at pins housekeeping/_3942_/A1 and housekeeping/_3942_/B2 of cell housekeeping/_3942_. (PTE-060)
|
||||
Warning: No clock-gating check is inferred for clock hkspi_clk at pins housekeeping/_3942_/A2 and housekeeping/_3942_/B2 of cell housekeeping/_3942_. (PTE-060)
|
||||
Warning: No clock-gating check is inferred for clock hkspi_clk at pins housekeeping/_3942_/B1 and housekeeping/_3942_/B2 of cell housekeeping/_3942_. (PTE-060)
|
||||
Warning: No clock-gating check is inferred for clock hkspi_clk at pins gpio_control_in_1[1]/_065_/A2 and gpio_control_in_1[1]/_065_/A1 of cell gpio_control_in_1[1]/_065_. (PTE-060)
|
||||
Warning: No clock-gating check is inferred for clock hkspi_clk at pins gpio_control_in_1[1]/_065_/B1 and gpio_control_in_1[1]/_065_/A1 of cell gpio_control_in_1[1]/_065_. (PTE-060)
|
||||
Warning: No clock-gating check is inferred for clock clk at pins clock_ctrl/_205_/A1 and clock_ctrl/_205_/A0 of cell clock_ctrl/_205_. (PTE-060)
|
||||
Warning: No clock-gating check is inferred for clock clk at pins clock_ctrl/_205_/S and clock_ctrl/_205_/A0 of cell clock_ctrl/_205_. (PTE-060)
|
||||
Information: Inferring 1 clock-gating checks. (PTE-017)
|
||||
Warning: The drive-resistance for the timing arc (sky130_fd_sc_hd__ss_1.40v_100C/sky130_fd_sc_hd__buf_12) soc/fanout1256/A-->X (min rising & falling positive_unate) is much less than the network impedance to ground; PrimeTime has adjusted the drive-resistance to improve accuracy. (RC-009)
|
||||
Warning: The drive-resistance for the timing arc (sky130_fd_sc_hd__ss_1.40v_100C/sky130_fd_sc_hd__buf_12) soc/fanout1256/A-->X (max rising & falling positive_unate) is much less than the network impedance to ground; PrimeTime has adjusted the drive-resistance to improve accuracy. (RC-009)
|
||||
|
|
@ -5483,7 +5483,7 @@ Information: Number of nets evaluated in the previous iteration: 59816. (XTALK-1
|
|||
Report : write_sdf /home/passant/caravel/signoff/caravan/primetime-signoff/sdf/max/caravan.ss.sdf
|
||||
Design : caravan
|
||||
Version: T-2022.03-SP3
|
||||
Date : Sun Oct 30 07:21:22 2022
|
||||
Date : Mon Oct 31 14:21:30 2022
|
||||
****************************************
|
||||
|
||||
Warning: Clock 'hkspi_clk'has source on hierachical pin 'housekeeping/mgmt_gpio_in[4]'. Consider moving to: gpio_control_in_1a[2]/output6/X
|
||||
|
|
@ -5510,9 +5510,9 @@ PARA-040 Warning 330243 329843
|
|||
LNK-043 Information 190193 190093
|
||||
SVR-2 Information 2 2
|
||||
Total 5 types of messages are suppressed
|
||||
Maximum memory usage for this session: 2792.14 MB
|
||||
CPU usage for this session: 212 seconds
|
||||
Elapsed time for this session: 72 seconds
|
||||
Maximum memory usage for this session: 2791.79 MB
|
||||
CPU usage for this session: 214 seconds
|
||||
Elapsed time for this session: 73 seconds
|
||||
Diagnostics summary: 69 errors, 149 warnings, 124 informationals
|
||||
|
||||
Thank you for using pt_shell!
|
||||
|
|
|
|||
|
|
@ -61,7 +61,7 @@ if {\
|
|||
# -filter is supported by PT but not in the read_sdc
|
||||
# add max_tran constraint as the default max_tran of the ss hd SCL is 10 so the violations are not caught in ss corners
|
||||
# apply the constraint to hd cells at the ss corner on caravel/caravan
|
||||
if {$::env(PROC_CORNER) == "s" & $::env(DESIGN) == "caravel" | $::env(DESIGN) == "caravan" } {
|
||||
if { $::env(DESIGN) == "caravel" | $::env(DESIGN) == "caravan" & $::env(PROC_CORNER) == "s" } {
|
||||
set max_tran 1.5
|
||||
puts "\[INFO\]: Setting maximum transition of HD cells in slow process corner to: $max_tran"
|
||||
puts "For HD cells in the hierarchy of $::env(DESIGN)"
|
||||
|
|
@ -5434,9 +5434,9 @@ Warning: Line 171, Cell 'sky130_ef_io__vssd_lvc_clamped_pad', pin 'AMUXBUS_B', T
|
|||
Warning: Line 171, Cell 'sky130_ef_io__vssd_lvc_clamped_pad', pin 'AMUXBUS_B', The pin 'AMUXBUS_B' does not have a internal_power group. (LBDB-607)
|
||||
Technology library 'sky130_ef_io__vssd_lvc_clamped_pad_tt_025C_1v80_3v30' read successfully
|
||||
Loading verilog file '/home/passant/caravel_mgmt_soc_litex/verilog/gl/RAM128.v'
|
||||
Loading db file '/home/passant/caravel/scripts/pt_libs/scs130hd_tt_1.80v_25C.lib'
|
||||
Loading verilog file '/home/passant/caravel_mgmt_soc_litex/verilog/gl/mgmt_core_wrapper.v'
|
||||
Loading verilog file '/home/passant/caravel_mgmt_soc_litex/verilog/gl/RAM256.v'
|
||||
Loading db file '/home/passant/caravel/scripts/pt_libs/scs130hd_tt_1.80v_25C.lib'
|
||||
Loading verilog file '/home/passant/caravel/verilog/gl/mgmt_protect.v'
|
||||
Loading verilog file '/home/passant/caravel/verilog/gl/housekeeping.v'
|
||||
Loading verilog file '/home/passant/caravel/verilog/gl/caravel.v'
|
||||
|
|
@ -5468,27 +5468,27 @@ Loading verilog file '/home/passant/caravel/verilog/gl/gpio_logic_high.v'
|
|||
Loading verilog file '/home/passant/caravel/verilog/gl/xres_buf.v'
|
||||
Loading verilog file '/home/passant/caravel/verilog/gl/constant_block.v'
|
||||
Loading verilog file '/home/passant/caravel/verilog/gl/mgmt_protect_hv.v'
|
||||
Loading db file '/tmp/_pt1rqJPGma/1.db'
|
||||
Loading db file '/tmp/_pt1rZumHxz/1.db'
|
||||
Loading db file '/home/passant/caravel/scripts/pt_libs/scs130hvl_tt_3.3v_25C.lib'
|
||||
Loading db file '/tmp/_pt1rBQcXAg/1.db'
|
||||
Loading db file '/tmp/_pt1rPYDkqy/1.db'
|
||||
Loading db file '/home/passant/caravel/scripts/pt_libs/scs130hvl_tt_3.3v_lowhv_3.3v_lv_1.8v_25C.lib'
|
||||
Loading db file '/tmp/_pt1rAU3xRC/1.db'
|
||||
Loading db file '/tmp/_pt1rNU72PM/1.db'
|
||||
Loading db file '/home/passant/OpenLane/pdks/sky130A/libs.ref/sky130_fd_io/lib/sky130_fd_io__top_xres4v2_tt_tt_025C_1v80_3v30.lib'
|
||||
Loading db file '/tmp/_pt1rvIXPT4/1.db'
|
||||
Loading db file '/tmp/_pt1rluViU6/1.db'
|
||||
Loading db file '/home/passant/OpenLane/pdks/sky130A/libs.ref/sky130_fd_io/lib/sky130_ef_io__gpiov2_pad_tt_tt_025C_1v80_3v30.lib'
|
||||
Loading db file '/tmp/_pt1rsweBRA/1.db'
|
||||
Loading db file '/tmp/_pt1rdGaFUu/1.db'
|
||||
Loading db file '/home/passant/OpenLane/pdks/sky130A/libs.ref/sky130_fd_io/lib/sky130_ef_io__vccd_lvc_clamped_pad_tt_025C_1v80_3v30_3v30.lib'
|
||||
Loading db file '/tmp/_pt1rjFlB4a/1.db'
|
||||
Loading db file '/tmp/_pt1rTyNEdX/1.db'
|
||||
Loading db file '/home/passant/OpenLane/pdks/sky130A/libs.ref/sky130_fd_io/lib/sky130_ef_io__vdda_hvc_clamped_pad_tt_025C_1v80_3v30_3v30.lib'
|
||||
Loading db file '/tmp/_pt1rKan3gP/1.db'
|
||||
Loading db file '/tmp/_pt1rfisezt/1.db'
|
||||
Loading db file '/home/passant/OpenLane/pdks/sky130A/libs.ref/sky130_fd_io/lib/sky130_ef_io__vssa_hvc_clamped_pad_tt_025C_1v80_3v30_3v30.lib'
|
||||
Loading db file '/tmp/_pt1r5XlQex/1.db'
|
||||
Loading db file '/tmp/_pt1rXpnPH3/1.db'
|
||||
Loading db file '/home/passant/OpenLane/pdks/sky130A/libs.ref/sky130_fd_io/lib/sky130_ef_io__vssd_lvc_clamped3_pad_tt_025C_1v80_3v30.lib'
|
||||
Loading db file '/tmp/_pt1raGFvYi/1.db'
|
||||
Loading db file '/tmp/_pt1rrv9JCH/1.db'
|
||||
Loading db file '/home/passant/OpenLane/pdks/sky130A/libs.ref/sky130_fd_io/lib/sky130_ef_io__vccd_lvc_clamped3_pad_tt_025C_1v80_3v30_3v30.lib'
|
||||
Loading db file '/tmp/_pt1rDATtu8/1.db'
|
||||
Loading db file '/tmp/_pt1rj0Q9kp/1.db'
|
||||
Loading db file '/home/passant/OpenLane/pdks/sky130A/libs.ref/sky130_fd_io/lib/sky130_ef_io__vssd_lvc_clamped_pad_tt_025C_1v80_3v30.lib'
|
||||
Loading db file '/tmp/_pt1r0yGlO1/1.db'
|
||||
Loading db file '/tmp/_pt1r9Az7Pa/1.db'
|
||||
Linking design caravan...
|
||||
Warning: Unable to resolve reference to 'sky130_fd_sc_hd__fill_1' in 'caravan'. (LNK-005)
|
||||
Warning: Unable to resolve reference to 'sky130_fd_sc_hd__tapvpwrvgnd_1' in 'caravan'. (LNK-005)
|
||||
|
|
@ -5680,8 +5680,6 @@ Warning: Creating 'clock' on a hierarchical pin 'housekeeping/serial_load'. (UIT
|
|||
[INFO]: Input transition range: 1 : 4
|
||||
[INFO]: Setting derate factor to: 3.75 %
|
||||
1
|
||||
[INFO]: Setting maximum transition of HD cells in slow process corner to: 1.5
|
||||
For HD cells in the hierarchy of caravan:
|
||||
Information: Checked out license 'PrimeTime-SI' (PT-019)
|
||||
Information: Log for 'read_parasitics command' will be generated in 'parasitics_command.log'. (PARA-107)
|
||||
Error: All instance paths in the -path option should correspond to valid and same sub-design. (PARA-097)
|
||||
|
|
@ -5793,21 +5791,21 @@ Warning: Some timing arcs have been disabled for breaking timing loops or becaus
|
|||
Warning: Conflicted logic driving pin padframe/flash_io1_pad/DM[0], setting resolved logic value 0 on pin padframe/flash_io1_pad/DM[0]. (PTE-042)
|
||||
Warning: Conflicted logic driving pin padframe/flash_io1_pad/DM[1], setting resolved logic value 1 on pin padframe/flash_io1_pad/DM[1]. (PTE-042)
|
||||
Warning: Conflicted logic driving pin padframe/flash_io1_pad/DM[2], setting resolved logic value 1 on pin padframe/flash_io1_pad/DM[2]. (PTE-042)
|
||||
Warning: No clock-gating check is inferred for clock hkspi_clk at pins gpio_control_in_1[1]/_066_/A1 and gpio_control_in_1[1]/_066_/A2 of cell gpio_control_in_1[1]/_066_. (PTE-060)
|
||||
Warning: No clock-gating check is inferred for clock hkspi_clk at pins gpio_control_in_1[1]/_066_/B1 and gpio_control_in_1[1]/_066_/A2 of cell gpio_control_in_1[1]/_066_. (PTE-060)
|
||||
Warning: No clock-gating check is inferred for clock hkspi_clk at pins gpio_control_in_1[1]/_065_/A2 and gpio_control_in_1[1]/_065_/A1 of cell gpio_control_in_1[1]/_065_. (PTE-060)
|
||||
Warning: No clock-gating check is inferred for clock hkspi_clk at pins gpio_control_in_1[1]/_065_/B1 and gpio_control_in_1[1]/_065_/A1 of cell gpio_control_in_1[1]/_065_. (PTE-060)
|
||||
Warning: No clock-gating check is inferred for clock hkspi_clk at pins housekeeping/_3927_/A0 and housekeeping/_3927_/A1 of cell housekeeping/_3927_. (PTE-060)
|
||||
Warning: No clock-gating check is inferred for clock hkspi_clk at pins housekeeping/_3927_/S and housekeeping/_3927_/A1 of cell housekeeping/_3927_. (PTE-060)
|
||||
Warning: No clock-gating check is inferred for clock clk at pins clock_ctrl/_206_/A1 and clock_ctrl/_206_/A0 of cell clock_ctrl/_206_. (PTE-060)
|
||||
Warning: No clock-gating check is inferred for clock clk at pins clock_ctrl/_206_/S and clock_ctrl/_206_/A0 of cell clock_ctrl/_206_. (PTE-060)
|
||||
Warning: No clock-gating check is inferred for clock hkspi_clk at pins gpio_control_in_1[1]/_066_/A1 and gpio_control_in_1[1]/_066_/A2 of cell gpio_control_in_1[1]/_066_. (PTE-060)
|
||||
Warning: No clock-gating check is inferred for clock hkspi_clk at pins gpio_control_in_1[1]/_066_/B1 and gpio_control_in_1[1]/_066_/A2 of cell gpio_control_in_1[1]/_066_. (PTE-060)
|
||||
Warning: No clock-gating check is inferred for clock clk at pins clock_ctrl/_205_/A1 and clock_ctrl/_205_/A0 of cell clock_ctrl/_205_. (PTE-060)
|
||||
Warning: No clock-gating check is inferred for clock clk at pins clock_ctrl/_205_/S and clock_ctrl/_205_/A0 of cell clock_ctrl/_205_. (PTE-060)
|
||||
Warning: No clock-gating check is inferred for clock hkspi_clk at pins housekeeping/_3945_/A0 and housekeeping/_3945_/A1 of cell housekeeping/_3945_. (PTE-060)
|
||||
Warning: No clock-gating check is inferred for clock hkspi_clk at pins housekeeping/_3945_/S and housekeeping/_3945_/A1 of cell housekeeping/_3945_. (PTE-060)
|
||||
Warning: No clock-gating check is inferred for clock hkspi_clk at pins housekeeping/_3942_/A1 and housekeeping/_3942_/B2 of cell housekeeping/_3942_. (PTE-060)
|
||||
Warning: No clock-gating check is inferred for clock hkspi_clk at pins housekeeping/_3942_/A2 and housekeeping/_3942_/B2 of cell housekeeping/_3942_. (PTE-060)
|
||||
Warning: No clock-gating check is inferred for clock hkspi_clk at pins housekeeping/_3942_/B1 and housekeeping/_3942_/B2 of cell housekeeping/_3942_. (PTE-060)
|
||||
Warning: No clock-gating check is inferred for clock hkspi_clk at pins gpio_control_in_1[1]/_065_/A2 and gpio_control_in_1[1]/_065_/A1 of cell gpio_control_in_1[1]/_065_. (PTE-060)
|
||||
Warning: No clock-gating check is inferred for clock hkspi_clk at pins gpio_control_in_1[1]/_065_/B1 and gpio_control_in_1[1]/_065_/A1 of cell gpio_control_in_1[1]/_065_. (PTE-060)
|
||||
Warning: No clock-gating check is inferred for clock clk at pins clock_ctrl/_205_/A1 and clock_ctrl/_205_/A0 of cell clock_ctrl/_205_. (PTE-060)
|
||||
Warning: No clock-gating check is inferred for clock clk at pins clock_ctrl/_205_/S and clock_ctrl/_205_/A0 of cell clock_ctrl/_205_. (PTE-060)
|
||||
Warning: No clock-gating check is inferred for clock hkspi_clk at pins housekeeping/_3927_/A0 and housekeeping/_3927_/A1 of cell housekeeping/_3927_. (PTE-060)
|
||||
Warning: No clock-gating check is inferred for clock hkspi_clk at pins housekeeping/_3927_/S and housekeeping/_3927_/A1 of cell housekeeping/_3927_. (PTE-060)
|
||||
Warning: No clock-gating check is inferred for clock hkspi_clk at pins housekeeping/_3945_/A0 and housekeeping/_3945_/A1 of cell housekeeping/_3945_. (PTE-060)
|
||||
Warning: No clock-gating check is inferred for clock hkspi_clk at pins housekeeping/_3945_/S and housekeeping/_3945_/A1 of cell housekeeping/_3945_. (PTE-060)
|
||||
Information: Inferring 1 clock-gating checks. (PTE-017)
|
||||
Warning: The drive-resistance for the timing arc (sky130_fd_sc_hd__tt_1.80v_25C/sky130_fd_sc_hd__buf_16) gpio_control_in_1a[2]/output6/A-->X (min rising & falling positive_unate) is much less than the network impedance to ground; PrimeTime has adjusted the drive-resistance to improve accuracy. (RC-009)
|
||||
Warning: The drive-resistance for the timing arc (sky130_fd_sc_hd__tt_1.80v_25C/sky130_fd_sc_hd__buf_16) gpio_control_in_1a[2]/output6/A-->X (max rising & falling positive_unate) is much less than the network impedance to ground; PrimeTime has adjusted the drive-resistance to improve accuracy. (RC-009)
|
||||
|
|
@ -5856,8 +5854,8 @@ Warning: The drive-resistance for the timing arc (sky130_fd_sc_hd__tt_1.80v_25C/
|
|||
Warning: The drive-resistance for the timing arc (sky130_fd_sc_hd__tt_1.80v_25C/sky130_fd_sc_hd__buf_12) soc/fanout1687/A-->X (min rising & falling positive_unate) is much less than the network impedance to ground; PrimeTime has adjusted the drive-resistance to improve accuracy. (RC-009)
|
||||
Warning: The drive-resistance for the timing arc (sky130_fd_sc_hd__tt_1.80v_25C/sky130_fd_sc_hd__buf_12) soc/fanout1687/A-->X (max rising & falling positive_unate) is much less than the network impedance to ground; PrimeTime has adjusted the drive-resistance to improve accuracy. (RC-009)
|
||||
Warning: The drive-resistance for the timing arc (sky130_fd_sc_hd__tt_1.80v_25C/sky130_fd_sc_hd__buf_12) soc/fanout1689/A-->X (min rising & falling positive_unate) is much less than the network impedance to ground; PrimeTime has adjusted the drive-resistance to improve accuracy. (RC-009)
|
||||
Warning: The drive-resistance for the timing arc (sky130_fd_sc_hd__tt_1.80v_25C/sky130_fd_sc_hd__buf_12) soc/fanout1689/A-->X (max rising & falling positive_unate) is much less than the network impedance to ground; PrimeTime has adjusted the drive-resistance to improve accuracy. (RC-009)
|
||||
Warning: The drive-resistance for the timing arc (sky130_fd_sc_hd__tt_1.80v_25C/sky130_fd_sc_hd__buf_12) soc/fanout1691/A-->X (min rising & falling positive_unate) is much less than the network impedance to ground; PrimeTime has adjusted the drive-resistance to improve accuracy. (RC-009)
|
||||
Warning: The drive-resistance for the timing arc (sky130_fd_sc_hd__tt_1.80v_25C/sky130_fd_sc_hd__buf_12) soc/fanout1689/A-->X (max rising & falling positive_unate) is much less than the network impedance to ground; PrimeTime has adjusted the drive-resistance to improve accuracy. (RC-009)
|
||||
Warning: The drive-resistance for the timing arc (sky130_fd_sc_hd__tt_1.80v_25C/sky130_fd_sc_hd__buf_12) soc/fanout1691/A-->X (max rising & falling positive_unate) is much less than the network impedance to ground; PrimeTime has adjusted the drive-resistance to improve accuracy. (RC-009)
|
||||
Warning: The drive-resistance for the timing arc (sky130_fd_sc_hd__tt_1.80v_25C/sky130_fd_sc_hd__buf_12) soc/fanout1693/A-->X (min rising & falling positive_unate) is much less than the network impedance to ground; PrimeTime has adjusted the drive-resistance to improve accuracy. (RC-009)
|
||||
Warning: The drive-resistance for the timing arc (sky130_fd_sc_hd__tt_1.80v_25C/sky130_fd_sc_hd__buf_12) soc/fanout1693/A-->X (max rising & falling positive_unate) is much less than the network impedance to ground; PrimeTime has adjusted the drive-resistance to improve accuracy. (RC-009)
|
||||
|
|
@ -5905,10 +5903,10 @@ Warning: The drive-resistance for the timing arc (sky130_fd_sc_hd__tt_1.80v_25C/
|
|||
Warning: The drive-resistance for the timing arc (sky130_fd_sc_hd__tt_1.80v_25C/sky130_fd_sc_hd__buf_12) soc/_32602_/A-->X (max rising & falling positive_unate) is much less than the network impedance to ground; PrimeTime has adjusted the drive-resistance to improve accuracy. (RC-009)
|
||||
Warning: The drive-resistance for the timing arc (sky130_fd_sc_hd__tt_1.80v_25C/sky130_fd_sc_hd__buf_16) gpio_control_in_1a[2]/output6/A-->X (min rising & falling positive_unate) is much less than the network impedance to ground; PrimeTime has adjusted the drive-resistance to improve accuracy. (RC-009)
|
||||
Warning: The drive-resistance for the timing arc (sky130_fd_sc_hd__tt_1.80v_25C/sky130_fd_sc_hd__buf_16) gpio_control_in_1a[2]/output6/A-->X (max rising & falling positive_unate) is much less than the network impedance to ground; PrimeTime has adjusted the drive-resistance to improve accuracy. (RC-009)
|
||||
Warning: The drive-resistance for the timing arc (sky130_fd_sc_hd__tt_1.80v_25C/sky130_fd_sc_hd__buf_12) soc/wire1421/A-->X (min rising & falling positive_unate) is much less than the network impedance to ground; PrimeTime has adjusted the drive-resistance to improve accuracy. (RC-009)
|
||||
Warning: The drive-resistance for the timing arc (sky130_fd_sc_hd__tt_1.80v_25C/sky130_fd_sc_hd__buf_12) soc/wire1421/A-->X (max rising & falling positive_unate) is much less than the network impedance to ground; PrimeTime has adjusted the drive-resistance to improve accuracy. (RC-009)
|
||||
Warning: The drive-resistance for the timing arc (sky130_fd_sc_hd__tt_1.80v_25C/sky130_fd_sc_hd__buf_12) soc/fanout1429/A-->X (min rising & falling positive_unate) is much less than the network impedance to ground; PrimeTime has adjusted the drive-resistance to improve accuracy. (RC-009)
|
||||
Warning: The drive-resistance for the timing arc (sky130_fd_sc_hd__tt_1.80v_25C/sky130_fd_sc_hd__buf_12) soc/wire1421/A-->X (min rising & falling positive_unate) is much less than the network impedance to ground; PrimeTime has adjusted the drive-resistance to improve accuracy. (RC-009)
|
||||
Warning: The drive-resistance for the timing arc (sky130_fd_sc_hd__tt_1.80v_25C/sky130_fd_sc_hd__buf_12) soc/fanout1429/A-->X (max rising & falling positive_unate) is much less than the network impedance to ground; PrimeTime has adjusted the drive-resistance to improve accuracy. (RC-009)
|
||||
Warning: The drive-resistance for the timing arc (sky130_fd_sc_hd__tt_1.80v_25C/sky130_fd_sc_hd__buf_12) soc/wire1421/A-->X (max rising & falling positive_unate) is much less than the network impedance to ground; PrimeTime has adjusted the drive-resistance to improve accuracy. (RC-009)
|
||||
Information: Starting crosstalk aware timing iteration 1. (XTALK-001)
|
||||
Information: Starting crosstalk aware timing iteration 2. (XTALK-001)
|
||||
Information: Number of nets evaluated in the previous iteration: 59873. (XTALK-105)
|
||||
|
|
@ -5916,7 +5914,7 @@ Information: Number of nets evaluated in the previous iteration: 59873. (XTALK-1
|
|||
Report : write_sdf /home/passant/caravel/signoff/caravan/primetime-signoff/sdf/max/caravan.tt.sdf
|
||||
Design : caravan
|
||||
Version: T-2022.03-SP3
|
||||
Date : Sun Oct 30 07:17:38 2022
|
||||
Date : Mon Oct 31 14:17:46 2022
|
||||
****************************************
|
||||
|
||||
Warning: Clock 'hkspi_clk'has source on hierachical pin 'housekeeping/mgmt_gpio_in[4]'. Consider moving to: gpio_control_in_1a[2]/output6/X
|
||||
|
|
@ -5938,10 +5936,10 @@ Warning: The drive-resistance for the timing arc (sky130_fd_sc_hd__tt_1.80v_25C/
|
|||
Warning: The drive-resistance for the timing arc (sky130_fd_sc_hd__tt_1.80v_25C/sky130_fd_sc_hd__buf_16) gpio_control_in_1a[2]/output6/A-->X (max rising & falling positive_unate) is much less than the network impedance to ground; PrimeTime has adjusted the drive-resistance to improve accuracy. (RC-009)
|
||||
Warning: The drive-resistance for the timing arc (sky130_fd_sc_hd__tt_1.80v_25C/sky130_fd_sc_hd__buf_12) soc/input213/A-->X (min rising & falling positive_unate) is much less than the network impedance to ground; PrimeTime has adjusted the drive-resistance to improve accuracy. (RC-009)
|
||||
Warning: The drive-resistance for the timing arc (sky130_fd_sc_hd__tt_1.80v_25C/sky130_fd_sc_hd__buf_12) soc/input213/A-->X (min rising & falling positive_unate) is much less than the network impedance to ground; PrimeTime has adjusted the drive-resistance to improve accuracy. (RC-009)
|
||||
Warning: The drive-resistance for the timing arc (sky130_fd_sc_hd__tt_1.80v_25C/sky130_fd_sc_hd__buf_12) soc/wire1964/A-->X (min rising & falling positive_unate) is much less than the network impedance to ground; PrimeTime has adjusted the drive-resistance to improve accuracy. (RC-009)
|
||||
Warning: The drive-resistance for the timing arc (sky130_fd_sc_hd__tt_1.80v_25C/sky130_fd_sc_hd__buf_12) soc/wire1964/A-->X (max rising & falling positive_unate) is much less than the network impedance to ground; PrimeTime has adjusted the drive-resistance to improve accuracy. (RC-009)
|
||||
Warning: The drive-resistance for the timing arc (sky130_fd_sc_hd__tt_1.80v_25C/sky130_fd_sc_hd__buf_12) housekeeping/output245/A-->X (min rising & falling positive_unate) is much less than the network impedance to ground; PrimeTime has adjusted the drive-resistance to improve accuracy. (RC-009)
|
||||
Warning: The drive-resistance for the timing arc (sky130_fd_sc_hd__tt_1.80v_25C/sky130_fd_sc_hd__buf_12) housekeeping/output245/A-->X (max rising & falling positive_unate) is much less than the network impedance to ground; PrimeTime has adjusted the drive-resistance to improve accuracy. (RC-009)
|
||||
Warning: The drive-resistance for the timing arc (sky130_fd_sc_hd__tt_1.80v_25C/sky130_fd_sc_hd__buf_12) soc/wire1964/A-->X (min rising & falling positive_unate) is much less than the network impedance to ground; PrimeTime has adjusted the drive-resistance to improve accuracy. (RC-009)
|
||||
Warning: The drive-resistance for the timing arc (sky130_fd_sc_hd__tt_1.80v_25C/sky130_fd_sc_hd__buf_12) soc/wire1964/A-->X (max rising & falling positive_unate) is much less than the network impedance to ground; PrimeTime has adjusted the drive-resistance to improve accuracy. (RC-009)
|
||||
Warning: The drive-resistance for the timing arc (sky130_fd_sc_hd__tt_1.80v_25C/sky130_fd_sc_hd__buf_12) housekeeping/output245/A-->X (min rising & falling positive_unate) is much less than the network impedance to ground; PrimeTime has adjusted the drive-resistance to improve accuracy. (RC-009)
|
||||
Warning: The drive-resistance for the timing arc (sky130_fd_sc_hd__tt_1.80v_25C/sky130_fd_sc_hd__buf_12) housekeeping/output245/A-->X (max rising & falling positive_unate) is much less than the network impedance to ground; PrimeTime has adjusted the drive-resistance to improve accuracy. (RC-009)
|
||||
Warning: The drive-resistance for the timing arc (sky130_fd_sc_hd__tt_1.80v_25C/sky130_fd_sc_hd__buf_12) housekeeping/output245/A-->X (min rising & falling positive_unate) is much less than the network impedance to ground; PrimeTime has adjusted the drive-resistance to improve accuracy. (RC-009)
|
||||
|
|
@ -5958,10 +5956,10 @@ Warning: The drive-resistance for the timing arc (sky130_fd_sc_hd__tt_1.80v_25C/
|
|||
Warning: The drive-resistance for the timing arc (sky130_fd_sc_hd__tt_1.80v_25C/sky130_fd_sc_hd__buf_16) gpio_control_in_1a[2]/output6/A-->X (max rising & falling positive_unate) is much less than the network impedance to ground; PrimeTime has adjusted the drive-resistance to improve accuracy. (RC-009)
|
||||
Warning: The drive-resistance for the timing arc (sky130_fd_sc_hd__tt_1.80v_25C/sky130_fd_sc_hd__buf_12) soc/input213/A-->X (max rising & falling positive_unate) is much less than the network impedance to ground; PrimeTime has adjusted the drive-resistance to improve accuracy. (RC-009)
|
||||
Warning: The drive-resistance for the timing arc (sky130_fd_sc_hd__tt_1.80v_25C/sky130_fd_sc_hd__buf_12) soc/input213/A-->X (max rising & falling positive_unate) is much less than the network impedance to ground; PrimeTime has adjusted the drive-resistance to improve accuracy. (RC-009)
|
||||
Warning: The drive-resistance for the timing arc (sky130_fd_sc_hd__tt_1.80v_25C/sky130_fd_sc_hd__buf_12) soc/wire1964/A-->X (min rising & falling positive_unate) is much less than the network impedance to ground; PrimeTime has adjusted the drive-resistance to improve accuracy. (RC-009)
|
||||
Warning: The drive-resistance for the timing arc (sky130_fd_sc_hd__tt_1.80v_25C/sky130_fd_sc_hd__buf_12) soc/wire1964/A-->X (max rising & falling positive_unate) is much less than the network impedance to ground; PrimeTime has adjusted the drive-resistance to improve accuracy. (RC-009)
|
||||
Warning: The drive-resistance for the timing arc (sky130_fd_sc_hd__tt_1.80v_25C/sky130_fd_sc_hd__buf_12) housekeeping/output245/A-->X (min rising & falling positive_unate) is much less than the network impedance to ground; PrimeTime has adjusted the drive-resistance to improve accuracy. (RC-009)
|
||||
Warning: The drive-resistance for the timing arc (sky130_fd_sc_hd__tt_1.80v_25C/sky130_fd_sc_hd__buf_12) housekeeping/output245/A-->X (max rising & falling positive_unate) is much less than the network impedance to ground; PrimeTime has adjusted the drive-resistance to improve accuracy. (RC-009)
|
||||
Warning: The drive-resistance for the timing arc (sky130_fd_sc_hd__tt_1.80v_25C/sky130_fd_sc_hd__buf_12) soc/wire1964/A-->X (min rising & falling positive_unate) is much less than the network impedance to ground; PrimeTime has adjusted the drive-resistance to improve accuracy. (RC-009)
|
||||
Warning: The drive-resistance for the timing arc (sky130_fd_sc_hd__tt_1.80v_25C/sky130_fd_sc_hd__buf_12) soc/wire1964/A-->X (max rising & falling positive_unate) is much less than the network impedance to ground; PrimeTime has adjusted the drive-resistance to improve accuracy. (RC-009)
|
||||
Warning: The drive-resistance for the timing arc (sky130_fd_sc_hd__tt_1.80v_25C/sky130_fd_sc_hd__buf_12) housekeeping/output245/A-->X (min rising & falling positive_unate) is much less than the network impedance to ground; PrimeTime has adjusted the drive-resistance to improve accuracy. (RC-009)
|
||||
Warning: The drive-resistance for the timing arc (sky130_fd_sc_hd__tt_1.80v_25C/sky130_fd_sc_hd__buf_12) housekeeping/output245/A-->X (max rising & falling positive_unate) is much less than the network impedance to ground; PrimeTime has adjusted the drive-resistance to improve accuracy. (RC-009)
|
||||
Warning: The drive-resistance for the timing arc (sky130_fd_sc_hd__tt_1.80v_25C/sky130_fd_sc_hd__buf_12) housekeeping/output245/A-->X (min rising & falling positive_unate) is much less than the network impedance to ground; PrimeTime has adjusted the drive-resistance to improve accuracy. (RC-009)
|
||||
|
|
@ -5973,7 +5971,6 @@ Wrote model to '/home/passant/caravel/signoff/caravan/primetime-signoff/lib/max/
|
|||
Wrote test design to '/home/passant/caravel/signoff/caravan/primetime-signoff/lib/max/caravan.tt_test.db'
|
||||
Information: Elapsed time for lib file writing: 1 seconds (MEXT-096)
|
||||
Information: Defining new variable 'verilog'. (CMD-041)
|
||||
Information: Defining new variable 'max_tran'. (CMD-041)
|
||||
Suppressed Messages Summary:
|
||||
Id Severity Occurrences Suppressed
|
||||
-------------------------------------------------------------------------------
|
||||
|
|
@ -5984,10 +5981,10 @@ RC-009 Warning 426 286
|
|||
LNK-043 Information 190190 190090
|
||||
SVR-2 Information 2 2
|
||||
Total 6 types of messages are suppressed
|
||||
Maximum memory usage for this session: 2814.20 MB
|
||||
CPU usage for this session: 214 seconds
|
||||
Elapsed time for this session: 74 seconds
|
||||
Diagnostics summary: 69 errors, 285 warnings, 124 informationals
|
||||
Maximum memory usage for this session: 2824.04 MB
|
||||
CPU usage for this session: 211 seconds
|
||||
Elapsed time for this session: 73 seconds
|
||||
Diagnostics summary: 69 errors, 285 warnings, 123 informationals
|
||||
|
||||
Thank you for using pt_shell!
|
||||
STA run Passed!
|
||||
|
|
|
|||
|
|
@ -61,7 +61,7 @@ if {\
|
|||
# -filter is supported by PT but not in the read_sdc
|
||||
# add max_tran constraint as the default max_tran of the ss hd SCL is 10 so the violations are not caught in ss corners
|
||||
# apply the constraint to hd cells at the ss corner on caravel/caravan
|
||||
if {$::env(PROC_CORNER) == "s" & $::env(DESIGN) == "caravel" | $::env(DESIGN) == "caravan" } {
|
||||
if { $::env(DESIGN) == "caravel" | $::env(DESIGN) == "caravan" & $::env(PROC_CORNER) == "s" } {
|
||||
set max_tran 1.5
|
||||
puts "\[INFO\]: Setting maximum transition of HD cells in slow process corner to: $max_tran"
|
||||
puts "For HD cells in the hierarchy of $::env(DESIGN)"
|
||||
|
|
@ -15790,27 +15790,27 @@ Loading verilog file '/home/passant/caravel/verilog/gl/gpio_logic_high.v'
|
|||
Loading verilog file '/home/passant/caravel/verilog/gl/xres_buf.v'
|
||||
Loading verilog file '/home/passant/caravel/verilog/gl/constant_block.v'
|
||||
Loading verilog file '/home/passant/caravel/verilog/gl/mgmt_protect_hv.v'
|
||||
Loading db file '/tmp/_pt1rbfuxd3/1.db'
|
||||
Loading db file '/tmp/_pt1rkYD8gl/1.db'
|
||||
Loading db file '/home/passant/caravel/scripts/pt_libs/scs130hvl_ff_5.5v_-40C.lib'
|
||||
Loading db file '/tmp/_pt1rR1IkJJ/1.db'
|
||||
Loading db file '/tmp/_pt1re0zn1W/1.db'
|
||||
Loading db file '/home/passant/caravel/scripts/pt_libs/scs130hvl_ff_5.5v_lowhv_5.5v_lv_1.95v_-40C.lib'
|
||||
Loading db file '/tmp/_pt1rrCAHnI/1.db'
|
||||
Loading db file '/tmp/_pt1rSFqTRR/1.db'
|
||||
Loading db file '/home/passant/OpenLane/pdks/sky130A/libs.ref/sky130_fd_io/lib/sky130_fd_io__top_xres4v2_ff_ff_n40C_1v95_5v50.lib'
|
||||
Loading db file '/tmp/_pt1rVqoJwN/1.db'
|
||||
Loading db file '/tmp/_pt1rCYoQyT/1.db'
|
||||
Loading db file '/home/passant/OpenLane/pdks/sky130A/libs.ref/sky130_fd_io/lib/sky130_ef_io__gpiov2_pad_wrapped_ff_ff_n40C_1v95_5v50.lib'
|
||||
Loading db file '/tmp/_pt1rtaOQ0q/1.db'
|
||||
Loading db file '/tmp/_pt1rIVaUvv/1.db'
|
||||
Loading db file '/home/passant/OpenLane/pdks/sky130A/libs.ref/sky130_fd_io/lib/sky130_ef_io__vccd_lvc_clamped_pad_ff_n40C_1v95_5v50_5v50.lib'
|
||||
Loading db file '/tmp/_pt1rRJx7mv/1.db'
|
||||
Loading db file '/tmp/_pt1rMeJQzA/1.db'
|
||||
Loading db file '/home/passant/OpenLane/pdks/sky130A/libs.ref/sky130_fd_io/lib/sky130_ef_io__vdda_hvc_clamped_pad_ff_n40C_1v95_5v50_5v50.lib'
|
||||
Loading db file '/tmp/_pt1rvlkdqH/1.db'
|
||||
Loading db file '/tmp/_pt1rEwjciO/1.db'
|
||||
Loading db file '/home/passant/OpenLane/pdks/sky130A/libs.ref/sky130_fd_io/lib/sky130_ef_io__vssa_hvc_clamped_pad_ff_n40C_1v95_5v50_5v50.lib'
|
||||
Loading db file '/tmp/_pt1rtq13cX/1.db'
|
||||
Loading db file '/tmp/_pt1riFULa6/1.db'
|
||||
Loading db file '/home/passant/OpenLane/pdks/sky130A/libs.ref/sky130_fd_io/lib/sky130_ef_io__vssd_lvc_clamped3_pad_ff_n40C_1v95_5v50.lib'
|
||||
Loading db file '/tmp/_pt1rFCWuJg/1.db'
|
||||
Loading db file '/tmp/_pt1rmHbjYr/1.db'
|
||||
Loading db file '/home/passant/OpenLane/pdks/sky130A/libs.ref/sky130_fd_io/lib/sky130_ef_io__vccd_lvc_clamped3_pad_ff_n40C_1v95_5v50_5v50.lib'
|
||||
Loading db file '/tmp/_pt1rnVQ0YD/1.db'
|
||||
Loading db file '/tmp/_pt1riRgcAR/1.db'
|
||||
Loading db file '/home/passant/OpenLane/pdks/sky130A/libs.ref/sky130_fd_io/lib/sky130_ef_io__vssd_lvc_clamped_pad_ff_n40C_1v95_5v50.lib'
|
||||
Loading db file '/tmp/_pt1rNOVUY4/1.db'
|
||||
Loading db file '/tmp/_pt1ricANZk/1.db'
|
||||
Linking design caravan...
|
||||
Warning: Unable to resolve reference to 'sky130_fd_sc_hd__fill_1' in 'caravan'. (LNK-005)
|
||||
Warning: Unable to resolve reference to 'sky130_fd_sc_hd__tapvpwrvgnd_1' in 'caravan'. (LNK-005)
|
||||
|
|
@ -16002,8 +16002,6 @@ Warning: Creating 'clock' on a hierarchical pin 'housekeeping/serial_load'. (UIT
|
|||
[INFO]: Input transition range: 1 : 4
|
||||
[INFO]: Setting derate factor to: 3.75 %
|
||||
1
|
||||
[INFO]: Setting maximum transition of HD cells in slow process corner to: 1.5
|
||||
For HD cells in the hierarchy of caravan
|
||||
Information: Checked out license 'PrimeTime-SI' (PT-019)
|
||||
Information: Log for 'read_parasitics command' will be generated in 'parasitics_command.log'. (PARA-107)
|
||||
Error: All instance paths in the -path option should correspond to valid and same sub-design. (PARA-097)
|
||||
|
|
@ -16122,14 +16120,14 @@ Warning: No clock-gating check is inferred for clock hkspi_clk at pins housekeep
|
|||
Warning: No clock-gating check is inferred for clock hkspi_clk at pins housekeeping/_3942_/B1 and housekeeping/_3942_/B2 of cell housekeeping/_3942_. (PTE-060)
|
||||
Warning: No clock-gating check is inferred for clock clk at pins clock_ctrl/_206_/A1 and clock_ctrl/_206_/A0 of cell clock_ctrl/_206_. (PTE-060)
|
||||
Warning: No clock-gating check is inferred for clock clk at pins clock_ctrl/_206_/S and clock_ctrl/_206_/A0 of cell clock_ctrl/_206_. (PTE-060)
|
||||
Warning: No clock-gating check is inferred for clock hkspi_clk at pins housekeeping/_3927_/A0 and housekeeping/_3927_/A1 of cell housekeeping/_3927_. (PTE-060)
|
||||
Warning: No clock-gating check is inferred for clock hkspi_clk at pins housekeeping/_3927_/S and housekeeping/_3927_/A1 of cell housekeeping/_3927_. (PTE-060)
|
||||
Warning: No clock-gating check is inferred for clock clk at pins clock_ctrl/_205_/A1 and clock_ctrl/_205_/A0 of cell clock_ctrl/_205_. (PTE-060)
|
||||
Warning: No clock-gating check is inferred for clock clk at pins clock_ctrl/_205_/S and clock_ctrl/_205_/A0 of cell clock_ctrl/_205_. (PTE-060)
|
||||
Warning: No clock-gating check is inferred for clock hkspi_clk at pins housekeeping/_3945_/A0 and housekeeping/_3945_/A1 of cell housekeeping/_3945_. (PTE-060)
|
||||
Warning: No clock-gating check is inferred for clock hkspi_clk at pins housekeeping/_3945_/S and housekeeping/_3945_/A1 of cell housekeeping/_3945_. (PTE-060)
|
||||
Warning: No clock-gating check is inferred for clock hkspi_clk at pins gpio_control_in_1[1]/_065_/A2 and gpio_control_in_1[1]/_065_/A1 of cell gpio_control_in_1[1]/_065_. (PTE-060)
|
||||
Warning: No clock-gating check is inferred for clock hkspi_clk at pins gpio_control_in_1[1]/_065_/B1 and gpio_control_in_1[1]/_065_/A1 of cell gpio_control_in_1[1]/_065_. (PTE-060)
|
||||
Warning: No clock-gating check is inferred for clock clk at pins clock_ctrl/_205_/A1 and clock_ctrl/_205_/A0 of cell clock_ctrl/_205_. (PTE-060)
|
||||
Warning: No clock-gating check is inferred for clock clk at pins clock_ctrl/_205_/S and clock_ctrl/_205_/A0 of cell clock_ctrl/_205_. (PTE-060)
|
||||
Warning: No clock-gating check is inferred for clock hkspi_clk at pins housekeeping/_3927_/A0 and housekeeping/_3927_/A1 of cell housekeeping/_3927_. (PTE-060)
|
||||
Warning: No clock-gating check is inferred for clock hkspi_clk at pins housekeeping/_3927_/S and housekeeping/_3927_/A1 of cell housekeeping/_3927_. (PTE-060)
|
||||
Warning: No clock-gating check is inferred for clock hkspi_clk at pins housekeeping/_3945_/A0 and housekeeping/_3945_/A1 of cell housekeeping/_3945_. (PTE-060)
|
||||
Warning: No clock-gating check is inferred for clock hkspi_clk at pins housekeeping/_3945_/S and housekeeping/_3945_/A1 of cell housekeeping/_3945_. (PTE-060)
|
||||
Information: Inferring 1 clock-gating checks. (PTE-017)
|
||||
Warning: The drive-resistance for the timing arc (sky130_fd_sc_hd__ff_1.95v_-40C/sky130_fd_sc_hd__buf_12) soc/wire1964/A-->X (min rising & falling positive_unate) is much less than the network impedance to ground; PrimeTime has adjusted the drive-resistance to improve accuracy. (RC-009)
|
||||
Warning: The drive-resistance for the timing arc (sky130_fd_sc_hd__ff_1.95v_-40C/sky130_fd_sc_hd__buf_12) soc/wire1964/A-->X (max rising & falling positive_unate) is much less than the network impedance to ground; PrimeTime has adjusted the drive-resistance to improve accuracy. (RC-009)
|
||||
|
|
@ -16186,7 +16184,7 @@ Information: Number of nets evaluated in the previous iteration: 59920. (XTALK-1
|
|||
Report : write_sdf /home/passant/caravel/signoff/caravan/primetime-signoff/sdf/min/caravan.ff.sdf
|
||||
Design : caravan
|
||||
Version: T-2022.03-SP3
|
||||
Date : Sun Oct 30 07:26:30 2022
|
||||
Date : Mon Oct 31 14:26:48 2022
|
||||
****************************************
|
||||
|
||||
Warning: Clock 'hkspi_clk'has source on hierachical pin 'housekeeping/mgmt_gpio_in[4]'. Consider moving to: gpio_control_in_1a[2]/output6/X
|
||||
|
|
@ -16211,7 +16209,6 @@ Wrote model to '/home/passant/caravel/signoff/caravan/primetime-signoff/lib/min/
|
|||
Wrote test design to '/home/passant/caravel/signoff/caravan/primetime-signoff/lib/min/caravan.ff_test.db'
|
||||
Information: Elapsed time for lib file writing: 0 seconds (MEXT-096)
|
||||
Information: Defining new variable 'verilog'. (CMD-041)
|
||||
Information: Defining new variable 'max_tran'. (CMD-041)
|
||||
Suppressed Messages Summary:
|
||||
Id Severity Occurrences Suppressed
|
||||
-------------------------------------------------------------------------------
|
||||
|
|
@ -16221,10 +16218,10 @@ PARA-040 Warning 314319 313919
|
|||
LNK-043 Information 190190 190090
|
||||
SVR-2 Information 2 2
|
||||
Total 5 types of messages are suppressed
|
||||
Maximum memory usage for this session: 2793.31 MB
|
||||
CPU usage for this session: 206 seconds
|
||||
Elapsed time for this session: 77 seconds
|
||||
Diagnostics summary: 69 errors, 201 warnings, 124 informationals
|
||||
Maximum memory usage for this session: 2810.65 MB
|
||||
CPU usage for this session: 210 seconds
|
||||
Elapsed time for this session: 80 seconds
|
||||
Diagnostics summary: 69 errors, 201 warnings, 123 informationals
|
||||
|
||||
Thank you for using pt_shell!
|
||||
STA run Passed!
|
||||
|
|
@ -61,7 +61,7 @@ if {\
|
|||
# -filter is supported by PT but not in the read_sdc
|
||||
# add max_tran constraint as the default max_tran of the ss hd SCL is 10 so the violations are not caught in ss corners
|
||||
# apply the constraint to hd cells at the ss corner on caravel/caravan
|
||||
if {$::env(PROC_CORNER) == "s" & $::env(DESIGN) == "caravel" | $::env(DESIGN) == "caravan" } {
|
||||
if { $::env(DESIGN) == "caravel" | $::env(DESIGN) == "caravan" & $::env(PROC_CORNER) == "s" } {
|
||||
set max_tran 1.5
|
||||
puts "\[INFO\]: Setting maximum transition of HD cells in slow process corner to: $max_tran"
|
||||
puts "For HD cells in the hierarchy of $::env(DESIGN)"
|
||||
|
|
@ -5099,9 +5099,9 @@ Warning: Line 171, Cell 'sky130_ef_io__vssd_lvc_clamped_pad', pin 'AMUXBUS_B', T
|
|||
Warning: Line 171, Cell 'sky130_ef_io__vssd_lvc_clamped_pad', pin 'AMUXBUS_B', The pin 'AMUXBUS_B' does not have a internal_power group. (LBDB-607)
|
||||
Technology library 'sky130_ef_io__vssd_lvc_clamped_pad_ss_100C_1v60_3v00' read successfully
|
||||
Loading verilog file '/home/passant/caravel_mgmt_soc_litex/verilog/gl/RAM128.v'
|
||||
Loading db file '/home/passant/caravel/scripts/pt_libs/scs130hd_ss_1.40v_100C.lib'
|
||||
Loading verilog file '/home/passant/caravel_mgmt_soc_litex/verilog/gl/RAM256.v'
|
||||
Loading verilog file '/home/passant/caravel_mgmt_soc_litex/verilog/gl/mgmt_core_wrapper.v'
|
||||
Loading db file '/home/passant/caravel/scripts/pt_libs/scs130hd_ss_1.40v_100C.lib'
|
||||
Loading verilog file '/home/passant/caravel/verilog/gl/mgmt_protect.v'
|
||||
Loading verilog file '/home/passant/caravel/verilog/gl/housekeeping.v'
|
||||
Loading verilog file '/home/passant/caravel/verilog/gl/caravel.v'
|
||||
|
|
@ -5133,25 +5133,25 @@ Loading verilog file '/home/passant/caravel/verilog/gl/gpio_logic_high.v'
|
|||
Loading verilog file '/home/passant/caravel/verilog/gl/xres_buf.v'
|
||||
Loading verilog file '/home/passant/caravel/verilog/gl/constant_block.v'
|
||||
Loading verilog file '/home/passant/caravel/verilog/gl/mgmt_protect_hv.v'
|
||||
Loading db file '/tmp/_pt1rT2ll5g/1.db'
|
||||
Loading db file '/tmp/_pt1rJtALan/1.db'
|
||||
Loading db file '/home/passant/caravel/scripts/pt_libs/scs130hvl_ss_3.00v_100C.lib'
|
||||
Loading db file '/tmp/_pt1r3z9ebY/1.db'
|
||||
Loading db file '/tmp/_pt1rssQlYR/1.db'
|
||||
Loading db file '/home/passant/OpenLane/pdks/sky130A/libs.ref/sky130_fd_io/lib/sky130_fd_io__top_xres4v2_ss_ss_100C_1v60_3v00.lib'
|
||||
Loading db file '/tmp/_pt1rjPMEQT/1.db'
|
||||
Loading db file '/tmp/_pt1rBcUNtB/1.db'
|
||||
Loading db file '/home/passant/OpenLane/pdks/sky130A/libs.ref/sky130_fd_io/lib/sky130_ef_io__gpiov2_pad_wrapped_ss_ss_100C_1v60_3v00.lib'
|
||||
Loading db file '/tmp/_pt1rvo2FAU/1.db'
|
||||
Loading db file '/tmp/_pt1rMu7e4p/1.db'
|
||||
Loading db file '/home/passant/OpenLane/pdks/sky130A/libs.ref/sky130_fd_io/lib/sky130_ef_io__vccd_lvc_clamped_pad_ss_100C_1v60_3v00_3v00.lib'
|
||||
Loading db file '/tmp/_pt1rDDIJAZ/1.db'
|
||||
Loading db file '/tmp/_pt1rbwmmWi/1.db'
|
||||
Loading db file '/home/passant/OpenLane/pdks/sky130A/libs.ref/sky130_fd_io/lib/sky130_ef_io__vdda_hvc_clamped_pad_ss_100C_1v60_3v00_3v00.lib'
|
||||
Loading db file '/tmp/_pt1rHgDnz8/1.db'
|
||||
Loading db file '/tmp/_pt1rATlWPf/1.db'
|
||||
Loading db file '/home/passant/OpenLane/pdks/sky130A/libs.ref/sky130_fd_io/lib/sky130_ef_io__vssa_hvc_clamped_pad_ss_100C_1v60_3v00_3v00.lib'
|
||||
Loading db file '/tmp/_pt1rBe71hl/1.db'
|
||||
Loading db file '/tmp/_pt1rTAQiwg/1.db'
|
||||
Loading db file '/home/passant/OpenLane/pdks/sky130A/libs.ref/sky130_fd_io/lib/sky130_ef_io__vssd_lvc_clamped3_pad_ss_100C_1v60_3v00.lib'
|
||||
Loading db file '/tmp/_pt1rH6c0KB/1.db'
|
||||
Loading db file '/tmp/_pt1riW64Xk/1.db'
|
||||
Loading db file '/home/passant/OpenLane/pdks/sky130A/libs.ref/sky130_fd_io/lib/sky130_ef_io__vccd_lvc_clamped3_pad_ss_100C_1v60_3v00_3v00.lib'
|
||||
Loading db file '/tmp/_pt1rL0gYZV/1.db'
|
||||
Loading db file '/tmp/_pt1rHVREbt/1.db'
|
||||
Loading db file '/home/passant/OpenLane/pdks/sky130A/libs.ref/sky130_fd_io/lib/sky130_ef_io__vssd_lvc_clamped_pad_ss_100C_1v60_3v00.lib'
|
||||
Loading db file '/tmp/_pt1rrpSA0j/1.db'
|
||||
Loading db file '/tmp/_pt1rwgTebF/1.db'
|
||||
Linking design caravan...
|
||||
Warning: Unable to resolve reference to 'sky130_fd_sc_hd__fill_1' in 'caravan'. (LNK-005)
|
||||
Warning: Unable to resolve reference to 'sky130_fd_sc_hd__tapvpwrvgnd_1' in 'caravan'. (LNK-005)
|
||||
|
|
@ -5458,21 +5458,21 @@ Warning: Some timing arcs have been disabled for breaking timing loops or becaus
|
|||
Warning: Conflicted logic driving pin padframe/flash_io1_pad/DM[0], setting resolved logic value 0 on pin padframe/flash_io1_pad/DM[0]. (PTE-042)
|
||||
Warning: Conflicted logic driving pin padframe/flash_io1_pad/DM[1], setting resolved logic value 1 on pin padframe/flash_io1_pad/DM[1]. (PTE-042)
|
||||
Warning: Conflicted logic driving pin padframe/flash_io1_pad/DM[2], setting resolved logic value 1 on pin padframe/flash_io1_pad/DM[2]. (PTE-042)
|
||||
Warning: No clock-gating check is inferred for clock hkspi_clk at pins housekeeping/_3927_/A0 and housekeeping/_3927_/A1 of cell housekeeping/_3927_. (PTE-060)
|
||||
Warning: No clock-gating check is inferred for clock hkspi_clk at pins housekeeping/_3927_/S and housekeeping/_3927_/A1 of cell housekeeping/_3927_. (PTE-060)
|
||||
Warning: No clock-gating check is inferred for clock clk at pins clock_ctrl/_206_/A1 and clock_ctrl/_206_/A0 of cell clock_ctrl/_206_. (PTE-060)
|
||||
Warning: No clock-gating check is inferred for clock clk at pins clock_ctrl/_206_/S and clock_ctrl/_206_/A0 of cell clock_ctrl/_206_. (PTE-060)
|
||||
Warning: No clock-gating check is inferred for clock hkspi_clk at pins gpio_control_in_1[1]/_066_/A1 and gpio_control_in_1[1]/_066_/A2 of cell gpio_control_in_1[1]/_066_. (PTE-060)
|
||||
Warning: No clock-gating check is inferred for clock hkspi_clk at pins gpio_control_in_1[1]/_066_/B1 and gpio_control_in_1[1]/_066_/A2 of cell gpio_control_in_1[1]/_066_. (PTE-060)
|
||||
Warning: No clock-gating check is inferred for clock hkspi_clk at pins gpio_control_in_1[1]/_065_/A2 and gpio_control_in_1[1]/_065_/A1 of cell gpio_control_in_1[1]/_065_. (PTE-060)
|
||||
Warning: No clock-gating check is inferred for clock hkspi_clk at pins gpio_control_in_1[1]/_065_/B1 and gpio_control_in_1[1]/_065_/A1 of cell gpio_control_in_1[1]/_065_. (PTE-060)
|
||||
Warning: No clock-gating check is inferred for clock clk at pins clock_ctrl/_205_/A1 and clock_ctrl/_205_/A0 of cell clock_ctrl/_205_. (PTE-060)
|
||||
Warning: No clock-gating check is inferred for clock clk at pins clock_ctrl/_205_/S and clock_ctrl/_205_/A0 of cell clock_ctrl/_205_. (PTE-060)
|
||||
Warning: No clock-gating check is inferred for clock hkspi_clk at pins housekeeping/_3945_/A0 and housekeeping/_3945_/A1 of cell housekeeping/_3945_. (PTE-060)
|
||||
Warning: No clock-gating check is inferred for clock hkspi_clk at pins housekeeping/_3945_/S and housekeeping/_3945_/A1 of cell housekeeping/_3945_. (PTE-060)
|
||||
Warning: No clock-gating check is inferred for clock hkspi_clk at pins housekeeping/_3942_/A1 and housekeeping/_3942_/B2 of cell housekeeping/_3942_. (PTE-060)
|
||||
Warning: No clock-gating check is inferred for clock hkspi_clk at pins housekeeping/_3942_/A2 and housekeeping/_3942_/B2 of cell housekeeping/_3942_. (PTE-060)
|
||||
Warning: No clock-gating check is inferred for clock hkspi_clk at pins housekeeping/_3942_/B1 and housekeeping/_3942_/B2 of cell housekeeping/_3942_. (PTE-060)
|
||||
Warning: No clock-gating check is inferred for clock clk at pins clock_ctrl/_206_/A1 and clock_ctrl/_206_/A0 of cell clock_ctrl/_206_. (PTE-060)
|
||||
Warning: No clock-gating check is inferred for clock clk at pins clock_ctrl/_206_/S and clock_ctrl/_206_/A0 of cell clock_ctrl/_206_. (PTE-060)
|
||||
Warning: No clock-gating check is inferred for clock clk at pins clock_ctrl/_205_/A1 and clock_ctrl/_205_/A0 of cell clock_ctrl/_205_. (PTE-060)
|
||||
Warning: No clock-gating check is inferred for clock clk at pins clock_ctrl/_205_/S and clock_ctrl/_205_/A0 of cell clock_ctrl/_205_. (PTE-060)
|
||||
Warning: No clock-gating check is inferred for clock hkspi_clk at pins housekeeping/_3927_/A0 and housekeeping/_3927_/A1 of cell housekeeping/_3927_. (PTE-060)
|
||||
Warning: No clock-gating check is inferred for clock hkspi_clk at pins housekeeping/_3927_/S and housekeeping/_3927_/A1 of cell housekeeping/_3927_. (PTE-060)
|
||||
Warning: No clock-gating check is inferred for clock hkspi_clk at pins gpio_control_in_1[1]/_065_/A2 and gpio_control_in_1[1]/_065_/A1 of cell gpio_control_in_1[1]/_065_. (PTE-060)
|
||||
Warning: No clock-gating check is inferred for clock hkspi_clk at pins gpio_control_in_1[1]/_065_/B1 and gpio_control_in_1[1]/_065_/A1 of cell gpio_control_in_1[1]/_065_. (PTE-060)
|
||||
Warning: No clock-gating check is inferred for clock hkspi_clk at pins housekeeping/_3945_/A0 and housekeeping/_3945_/A1 of cell housekeeping/_3945_. (PTE-060)
|
||||
Warning: No clock-gating check is inferred for clock hkspi_clk at pins housekeeping/_3945_/S and housekeeping/_3945_/A1 of cell housekeeping/_3945_. (PTE-060)
|
||||
Information: Inferring 1 clock-gating checks. (PTE-017)
|
||||
Information: Starting crosstalk aware timing iteration 1. (XTALK-001)
|
||||
Information: Starting crosstalk aware timing iteration 2. (XTALK-001)
|
||||
|
|
@ -5481,7 +5481,7 @@ Information: Number of nets evaluated in the previous iteration: 59811. (XTALK-1
|
|||
Report : write_sdf /home/passant/caravel/signoff/caravan/primetime-signoff/sdf/min/caravan.ss.sdf
|
||||
Design : caravan
|
||||
Version: T-2022.03-SP3
|
||||
Date : Sun Oct 30 07:22:35 2022
|
||||
Date : Mon Oct 31 14:22:44 2022
|
||||
****************************************
|
||||
|
||||
Warning: Clock 'hkspi_clk'has source on hierachical pin 'housekeeping/mgmt_gpio_in[4]'. Consider moving to: gpio_control_in_1a[2]/output6/X
|
||||
|
|
@ -5492,7 +5492,7 @@ Warning: Clock 'hk_serial_load'has source on hierachical pin 'housekeeping/seria
|
|||
(MEXT-20)
|
||||
Warning: Variable si_filter_keep_all_port_aggressors is set to FALSE (MEXT-80)
|
||||
Information: For model extraction, min_period and min_pulse_width arcs are extracted at the context slew. (MEXT-105)
|
||||
Information: Elapsed time for model extraction: 2 seconds (MEXT-096)
|
||||
Information: Elapsed time for model extraction: 1 seconds (MEXT-096)
|
||||
Wrote the LIB file /home/passant/caravel/signoff/caravan/primetime-signoff/lib/min/caravan.ss.lib
|
||||
Wrote model to '/home/passant/caravel/signoff/caravan/primetime-signoff/lib/min/caravan.ss_lib.db'
|
||||
Wrote test design to '/home/passant/caravel/signoff/caravan/primetime-signoff/lib/min/caravan.ss_test.db'
|
||||
|
|
@ -5508,9 +5508,9 @@ PARA-040 Warning 314319 313919
|
|||
LNK-043 Information 190193 190093
|
||||
SVR-2 Information 2 2
|
||||
Total 5 types of messages are suppressed
|
||||
Maximum memory usage for this session: 2780.86 MB
|
||||
CPU usage for this session: 211 seconds
|
||||
Elapsed time for this session: 72 seconds
|
||||
Maximum memory usage for this session: 2803.89 MB
|
||||
CPU usage for this session: 212 seconds
|
||||
Elapsed time for this session: 73 seconds
|
||||
Diagnostics summary: 69 errors, 147 warnings, 124 informationals
|
||||
|
||||
Thank you for using pt_shell!
|
||||
|
|
|
|||
|
|
@ -61,7 +61,7 @@ if {\
|
|||
# -filter is supported by PT but not in the read_sdc
|
||||
# add max_tran constraint as the default max_tran of the ss hd SCL is 10 so the violations are not caught in ss corners
|
||||
# apply the constraint to hd cells at the ss corner on caravel/caravan
|
||||
if {$::env(PROC_CORNER) == "s" & $::env(DESIGN) == "caravel" | $::env(DESIGN) == "caravan" } {
|
||||
if { $::env(DESIGN) == "caravel" | $::env(DESIGN) == "caravan" & $::env(PROC_CORNER) == "s" } {
|
||||
set max_tran 1.5
|
||||
puts "\[INFO\]: Setting maximum transition of HD cells in slow process corner to: $max_tran"
|
||||
puts "For HD cells in the hierarchy of $::env(DESIGN)"
|
||||
|
|
@ -5434,8 +5434,8 @@ Warning: Line 171, Cell 'sky130_ef_io__vssd_lvc_clamped_pad', pin 'AMUXBUS_B', T
|
|||
Warning: Line 171, Cell 'sky130_ef_io__vssd_lvc_clamped_pad', pin 'AMUXBUS_B', The pin 'AMUXBUS_B' does not have a internal_power group. (LBDB-607)
|
||||
Technology library 'sky130_ef_io__vssd_lvc_clamped_pad_tt_025C_1v80_3v30' read successfully
|
||||
Loading verilog file '/home/passant/caravel_mgmt_soc_litex/verilog/gl/RAM128.v'
|
||||
Loading db file '/home/passant/caravel/scripts/pt_libs/scs130hd_tt_1.80v_25C.lib'
|
||||
Loading verilog file '/home/passant/caravel_mgmt_soc_litex/verilog/gl/RAM256.v'
|
||||
Loading db file '/home/passant/caravel/scripts/pt_libs/scs130hd_tt_1.80v_25C.lib'
|
||||
Loading verilog file '/home/passant/caravel_mgmt_soc_litex/verilog/gl/mgmt_core_wrapper.v'
|
||||
Loading verilog file '/home/passant/caravel/verilog/gl/mgmt_protect.v'
|
||||
Loading verilog file '/home/passant/caravel/verilog/gl/housekeeping.v'
|
||||
|
|
@ -5468,27 +5468,27 @@ Loading verilog file '/home/passant/caravel/verilog/gl/gpio_logic_high.v'
|
|||
Loading verilog file '/home/passant/caravel/verilog/gl/xres_buf.v'
|
||||
Loading verilog file '/home/passant/caravel/verilog/gl/constant_block.v'
|
||||
Loading verilog file '/home/passant/caravel/verilog/gl/mgmt_protect_hv.v'
|
||||
Loading db file '/tmp/_pt1rbwJdKL/1.db'
|
||||
Loading db file '/tmp/_pt1rDnnDbB/1.db'
|
||||
Loading db file '/home/passant/caravel/scripts/pt_libs/scs130hvl_tt_3.3v_25C.lib'
|
||||
Loading db file '/tmp/_pt1rImQIa9/1.db'
|
||||
Loading db file '/tmp/_pt1rQH8Z9K/1.db'
|
||||
Loading db file '/home/passant/caravel/scripts/pt_libs/scs130hvl_tt_3.3v_lowhv_3.3v_lv_1.8v_25C.lib'
|
||||
Loading db file '/tmp/_pt1rXATA6L/1.db'
|
||||
Loading db file '/tmp/_pt1rhqgsCa/1.db'
|
||||
Loading db file '/home/passant/OpenLane/pdks/sky130A/libs.ref/sky130_fd_io/lib/sky130_fd_io__top_xres4v2_tt_tt_025C_1v80_3v30.lib'
|
||||
Loading db file '/tmp/_pt1rwfMhPu/1.db'
|
||||
Loading db file '/tmp/_pt1rcrpoLF/1.db'
|
||||
Loading db file '/home/passant/OpenLane/pdks/sky130A/libs.ref/sky130_fd_io/lib/sky130_ef_io__gpiov2_pad_tt_tt_025C_1v80_3v30.lib'
|
||||
Loading db file '/tmp/_pt1rhEuMzh/1.db'
|
||||
Loading db file '/tmp/_pt1rX4tySe/1.db'
|
||||
Loading db file '/home/passant/OpenLane/pdks/sky130A/libs.ref/sky130_fd_io/lib/sky130_ef_io__vccd_lvc_clamped_pad_tt_025C_1v80_3v30_3v30.lib'
|
||||
Loading db file '/tmp/_pt1rs2fpE8/1.db'
|
||||
Loading db file '/tmp/_pt1rQDi4hS/1.db'
|
||||
Loading db file '/home/passant/OpenLane/pdks/sky130A/libs.ref/sky130_fd_io/lib/sky130_ef_io__vdda_hvc_clamped_pad_tt_025C_1v80_3v30_3v30.lib'
|
||||
Loading db file '/tmp/_pt1rdbIOK3/1.db'
|
||||
Loading db file '/tmp/_pt1rDxu5Jz/1.db'
|
||||
Loading db file '/home/passant/OpenLane/pdks/sky130A/libs.ref/sky130_fd_io/lib/sky130_ef_io__vssa_hvc_clamped_pad_tt_025C_1v80_3v30_3v30.lib'
|
||||
Loading db file '/tmp/_pt1rAaZwE2/1.db'
|
||||
Loading db file '/tmp/_pt1r20HB0k/1.db'
|
||||
Loading db file '/home/passant/OpenLane/pdks/sky130A/libs.ref/sky130_fd_io/lib/sky130_ef_io__vssd_lvc_clamped3_pad_tt_025C_1v80_3v30.lib'
|
||||
Loading db file '/tmp/_pt1rXVttm5/1.db'
|
||||
Loading db file '/tmp/_pt1rVp1u49/1.db'
|
||||
Loading db file '/home/passant/OpenLane/pdks/sky130A/libs.ref/sky130_fd_io/lib/sky130_ef_io__vccd_lvc_clamped3_pad_tt_025C_1v80_3v30_3v30.lib'
|
||||
Loading db file '/tmp/_pt1rUC3pRb/1.db'
|
||||
Loading db file '/tmp/_pt1r2FZ7V2/1.db'
|
||||
Loading db file '/home/passant/OpenLane/pdks/sky130A/libs.ref/sky130_fd_io/lib/sky130_ef_io__vssd_lvc_clamped_pad_tt_025C_1v80_3v30.lib'
|
||||
Loading db file '/tmp/_pt1rX6hEbm/1.db'
|
||||
Loading db file '/tmp/_pt1rvkQFzZ/1.db'
|
||||
Linking design caravan...
|
||||
Warning: Unable to resolve reference to 'sky130_fd_sc_hd__fill_1' in 'caravan'. (LNK-005)
|
||||
Warning: Unable to resolve reference to 'sky130_fd_sc_hd__tapvpwrvgnd_1' in 'caravan'. (LNK-005)
|
||||
|
|
@ -5680,8 +5680,6 @@ Warning: Creating 'clock' on a hierarchical pin 'housekeeping/serial_load'. (UIT
|
|||
[INFO]: Input transition range: 1 : 4
|
||||
[INFO]: Setting derate factor to: 3.75 %
|
||||
1
|
||||
[INFO]: Setting maximum transition of HD cells in slow process corner to: 1.5
|
||||
For HD cells in the hierarchy of caravan
|
||||
Information: Checked out license 'PrimeTime-SI' (PT-019)
|
||||
Information: Log for 'read_parasitics command' will be generated in 'parasitics_command.log'. (PARA-107)
|
||||
Error: All instance paths in the -path option should correspond to valid and same sub-design. (PARA-097)
|
||||
|
|
@ -5790,24 +5788,24 @@ Error: All instance paths in the -path option should correspond to valid and sam
|
|||
Information: Setting rc_cache_min_max_rise_fall_ceff to TRUE. (XTALK-015)
|
||||
Information: Building multi voltage information for entire design. (MV-022)
|
||||
Warning: Some timing arcs have been disabled for breaking timing loops or because of constant propagation. Use the 'report_disable_timing' command to get the list of these disabled timing arcs. (PTE-003)
|
||||
Warning: Conflicted logic driving pin padframe/flash_io1_pad/DM[0], setting resolved logic value 0 on pin padframe/flash_io1_pad/DM[0]. (PTE-042)
|
||||
Warning: Conflicted logic driving pin padframe/flash_io1_pad/DM[1], setting resolved logic value 1 on pin padframe/flash_io1_pad/DM[1]. (PTE-042)
|
||||
Warning: Conflicted logic driving pin padframe/flash_io1_pad/DM[2], setting resolved logic value 1 on pin padframe/flash_io1_pad/DM[2]. (PTE-042)
|
||||
Warning: Conflicted logic driving pin padframe/flash_io1_pad/DM[0], setting resolved logic value 0 on pin padframe/flash_io1_pad/DM[0]. (PTE-042)
|
||||
Warning: No clock-gating check is inferred for clock hkspi_clk at pins gpio_control_in_1[1]/_065_/A2 and gpio_control_in_1[1]/_065_/A1 of cell gpio_control_in_1[1]/_065_. (PTE-060)
|
||||
Warning: No clock-gating check is inferred for clock hkspi_clk at pins gpio_control_in_1[1]/_065_/B1 and gpio_control_in_1[1]/_065_/A1 of cell gpio_control_in_1[1]/_065_. (PTE-060)
|
||||
Warning: No clock-gating check is inferred for clock hkspi_clk at pins housekeeping/_3927_/A0 and housekeeping/_3927_/A1 of cell housekeeping/_3927_. (PTE-060)
|
||||
Warning: No clock-gating check is inferred for clock hkspi_clk at pins housekeeping/_3927_/S and housekeeping/_3927_/A1 of cell housekeeping/_3927_. (PTE-060)
|
||||
Warning: No clock-gating check is inferred for clock hkspi_clk at pins housekeeping/_3942_/A1 and housekeeping/_3942_/B2 of cell housekeeping/_3942_. (PTE-060)
|
||||
Warning: No clock-gating check is inferred for clock hkspi_clk at pins housekeeping/_3942_/A2 and housekeeping/_3942_/B2 of cell housekeeping/_3942_. (PTE-060)
|
||||
Warning: No clock-gating check is inferred for clock hkspi_clk at pins housekeeping/_3942_/B1 and housekeeping/_3942_/B2 of cell housekeeping/_3942_. (PTE-060)
|
||||
Warning: No clock-gating check is inferred for clock hkspi_clk at pins gpio_control_in_1[1]/_066_/A1 and gpio_control_in_1[1]/_066_/A2 of cell gpio_control_in_1[1]/_066_. (PTE-060)
|
||||
Warning: No clock-gating check is inferred for clock hkspi_clk at pins gpio_control_in_1[1]/_066_/B1 and gpio_control_in_1[1]/_066_/A2 of cell gpio_control_in_1[1]/_066_. (PTE-060)
|
||||
Warning: No clock-gating check is inferred for clock clk at pins clock_ctrl/_206_/A1 and clock_ctrl/_206_/A0 of cell clock_ctrl/_206_. (PTE-060)
|
||||
Warning: No clock-gating check is inferred for clock clk at pins clock_ctrl/_206_/S and clock_ctrl/_206_/A0 of cell clock_ctrl/_206_. (PTE-060)
|
||||
Warning: No clock-gating check is inferred for clock hkspi_clk at pins gpio_control_in_1[1]/_066_/A1 and gpio_control_in_1[1]/_066_/A2 of cell gpio_control_in_1[1]/_066_. (PTE-060)
|
||||
Warning: No clock-gating check is inferred for clock hkspi_clk at pins gpio_control_in_1[1]/_066_/B1 and gpio_control_in_1[1]/_066_/A2 of cell gpio_control_in_1[1]/_066_. (PTE-060)
|
||||
Warning: No clock-gating check is inferred for clock clk at pins clock_ctrl/_205_/A1 and clock_ctrl/_205_/A0 of cell clock_ctrl/_205_. (PTE-060)
|
||||
Warning: No clock-gating check is inferred for clock clk at pins clock_ctrl/_205_/S and clock_ctrl/_205_/A0 of cell clock_ctrl/_205_. (PTE-060)
|
||||
Warning: No clock-gating check is inferred for clock hkspi_clk at pins housekeeping/_3945_/A0 and housekeeping/_3945_/A1 of cell housekeeping/_3945_. (PTE-060)
|
||||
Warning: No clock-gating check is inferred for clock hkspi_clk at pins housekeeping/_3945_/S and housekeeping/_3945_/A1 of cell housekeeping/_3945_. (PTE-060)
|
||||
Warning: No clock-gating check is inferred for clock hkspi_clk at pins gpio_control_in_1[1]/_065_/A2 and gpio_control_in_1[1]/_065_/A1 of cell gpio_control_in_1[1]/_065_. (PTE-060)
|
||||
Warning: No clock-gating check is inferred for clock hkspi_clk at pins gpio_control_in_1[1]/_065_/B1 and gpio_control_in_1[1]/_065_/A1 of cell gpio_control_in_1[1]/_065_. (PTE-060)
|
||||
Warning: No clock-gating check is inferred for clock hkspi_clk at pins housekeeping/_3942_/A1 and housekeeping/_3942_/B2 of cell housekeeping/_3942_. (PTE-060)
|
||||
Warning: No clock-gating check is inferred for clock hkspi_clk at pins housekeeping/_3942_/A2 and housekeeping/_3942_/B2 of cell housekeeping/_3942_. (PTE-060)
|
||||
Warning: No clock-gating check is inferred for clock hkspi_clk at pins housekeeping/_3942_/B1 and housekeeping/_3942_/B2 of cell housekeeping/_3942_. (PTE-060)
|
||||
Information: Inferring 1 clock-gating checks. (PTE-017)
|
||||
Warning: The drive-resistance for the timing arc (sky130_fd_sc_hd__tt_1.80v_25C/sky130_fd_sc_hd__buf_12) soc/wire1964/A-->X (min rising & falling positive_unate) is much less than the network impedance to ground; PrimeTime has adjusted the drive-resistance to improve accuracy. (RC-009)
|
||||
Warning: The drive-resistance for the timing arc (sky130_fd_sc_hd__tt_1.80v_25C/sky130_fd_sc_hd__buf_12) soc/wire1964/A-->X (max rising & falling positive_unate) is much less than the network impedance to ground; PrimeTime has adjusted the drive-resistance to improve accuracy. (RC-009)
|
||||
|
|
@ -5822,7 +5820,7 @@ Information: Number of nets evaluated in the previous iteration: 59861. (XTALK-1
|
|||
Report : write_sdf /home/passant/caravel/signoff/caravan/primetime-signoff/sdf/min/caravan.tt.sdf
|
||||
Design : caravan
|
||||
Version: T-2022.03-SP3
|
||||
Date : Sun Oct 30 07:18:52 2022
|
||||
Date : Mon Oct 31 14:19:00 2022
|
||||
****************************************
|
||||
|
||||
Warning: Clock 'hkspi_clk'has source on hierachical pin 'housekeeping/mgmt_gpio_in[4]'. Consider moving to: gpio_control_in_1a[2]/output6/X
|
||||
|
|
@ -5869,13 +5867,12 @@ Warning: The drive-resistance for the timing arc (sky130_fd_sc_hd__tt_1.80v_25C/
|
|||
Warning: The drive-resistance for the timing arc (sky130_fd_sc_hd__tt_1.80v_25C/sky130_fd_sc_hd__buf_12) soc/wire1964/A-->X (min rising & falling positive_unate) is much less than the network impedance to ground; PrimeTime has adjusted the drive-resistance to improve accuracy. (RC-009)
|
||||
Warning: The drive-resistance for the timing arc (sky130_fd_sc_hd__tt_1.80v_25C/sky130_fd_sc_hd__buf_12) soc/wire1964/A-->X (max rising & falling positive_unate) is much less than the network impedance to ground; PrimeTime has adjusted the drive-resistance to improve accuracy. (RC-009)
|
||||
Information: For model extraction, min_period and min_pulse_width arcs are extracted at the context slew. (MEXT-105)
|
||||
Information: Elapsed time for model extraction: 4 seconds (MEXT-096)
|
||||
Information: Elapsed time for model extraction: 3 seconds (MEXT-096)
|
||||
Wrote the LIB file /home/passant/caravel/signoff/caravan/primetime-signoff/lib/min/caravan.tt.lib
|
||||
Wrote model to '/home/passant/caravel/signoff/caravan/primetime-signoff/lib/min/caravan.tt_lib.db'
|
||||
Wrote test design to '/home/passant/caravel/signoff/caravan/primetime-signoff/lib/min/caravan.tt_test.db'
|
||||
Information: Elapsed time for lib file writing: 0 seconds (MEXT-096)
|
||||
Information: Elapsed time for lib file writing: 1 seconds (MEXT-096)
|
||||
Information: Defining new variable 'verilog'. (CMD-041)
|
||||
Information: Defining new variable 'max_tran'. (CMD-041)
|
||||
Suppressed Messages Summary:
|
||||
Id Severity Occurrences Suppressed
|
||||
-------------------------------------------------------------------------------
|
||||
|
|
@ -5885,10 +5882,10 @@ PARA-040 Warning 314319 313919
|
|||
LNK-043 Information 190190 190090
|
||||
SVR-2 Information 2 2
|
||||
Total 5 types of messages are suppressed
|
||||
Maximum memory usage for this session: 2790.07 MB
|
||||
CPU usage for this session: 211 seconds
|
||||
Maximum memory usage for this session: 2808.28 MB
|
||||
CPU usage for this session: 208 seconds
|
||||
Elapsed time for this session: 73 seconds
|
||||
Diagnostics summary: 69 errors, 187 warnings, 124 informationals
|
||||
Diagnostics summary: 69 errors, 187 warnings, 123 informationals
|
||||
|
||||
Thank you for using pt_shell!
|
||||
STA run Passed!
|
||||
|
|
|
|||
|
|
@ -61,7 +61,7 @@ if {\
|
|||
# -filter is supported by PT but not in the read_sdc
|
||||
# add max_tran constraint as the default max_tran of the ss hd SCL is 10 so the violations are not caught in ss corners
|
||||
# apply the constraint to hd cells at the ss corner on caravel/caravan
|
||||
if {$::env(PROC_CORNER) == "s" & $::env(DESIGN) == "caravel" | $::env(DESIGN) == "caravan" } {
|
||||
if { $::env(DESIGN) == "caravel" | $::env(DESIGN) == "caravan" & $::env(PROC_CORNER) == "s" } {
|
||||
set max_tran 1.5
|
||||
puts "\[INFO\]: Setting maximum transition of HD cells in slow process corner to: $max_tran"
|
||||
puts "For HD cells in the hierarchy of $::env(DESIGN)"
|
||||
|
|
@ -15756,8 +15756,8 @@ Warning: Line 171, Cell 'sky130_ef_io__vssd_lvc_clamped_pad', pin 'AMUXBUS_B', T
|
|||
Warning: Line 171, Cell 'sky130_ef_io__vssd_lvc_clamped_pad', pin 'AMUXBUS_B', The pin 'AMUXBUS_B' does not have a internal_power group. (LBDB-607)
|
||||
Technology library 'sky130_ef_io__vssd_lvc_clamped_pad_ff_n40C_1v95_5v50' read successfully
|
||||
Loading verilog file '/home/passant/caravel_mgmt_soc_litex/verilog/gl/RAM128.v'
|
||||
Loading verilog file '/home/passant/caravel_mgmt_soc_litex/verilog/gl/RAM256.v'
|
||||
Loading db file '/home/passant/caravel/scripts/pt_libs/scs130hd_ff_1.95v_-40C.lib'
|
||||
Loading verilog file '/home/passant/caravel_mgmt_soc_litex/verilog/gl/RAM256.v'
|
||||
Loading verilog file '/home/passant/caravel_mgmt_soc_litex/verilog/gl/mgmt_core_wrapper.v'
|
||||
Loading verilog file '/home/passant/caravel/verilog/gl/mgmt_protect.v'
|
||||
Loading verilog file '/home/passant/caravel/verilog/gl/housekeeping.v'
|
||||
|
|
@ -15790,27 +15790,27 @@ Loading verilog file '/home/passant/caravel/verilog/gl/gpio_logic_high.v'
|
|||
Loading verilog file '/home/passant/caravel/verilog/gl/xres_buf.v'
|
||||
Loading verilog file '/home/passant/caravel/verilog/gl/constant_block.v'
|
||||
Loading verilog file '/home/passant/caravel/verilog/gl/mgmt_protect_hv.v'
|
||||
Loading db file '/tmp/_pt1r4VFJH7/1.db'
|
||||
Loading db file '/tmp/_pt1rVUmlvH/1.db'
|
||||
Loading db file '/home/passant/caravel/scripts/pt_libs/scs130hvl_ff_5.5v_-40C.lib'
|
||||
Loading db file '/tmp/_pt1rCuD2QO/1.db'
|
||||
Loading db file '/tmp/_pt1rRMkhEm/1.db'
|
||||
Loading db file '/home/passant/caravel/scripts/pt_libs/scs130hvl_ff_5.5v_lowhv_5.5v_lv_1.95v_-40C.lib'
|
||||
Loading db file '/tmp/_pt1rODyObO/1.db'
|
||||
Loading db file '/tmp/_pt1rPxjp1j/1.db'
|
||||
Loading db file '/home/passant/OpenLane/pdks/sky130A/libs.ref/sky130_fd_io/lib/sky130_fd_io__top_xres4v2_ff_ff_n40C_1v95_5v50.lib'
|
||||
Loading db file '/tmp/_pt1ruEun2T/1.db'
|
||||
Loading db file '/tmp/_pt1rdm3RVn/1.db'
|
||||
Loading db file '/home/passant/OpenLane/pdks/sky130A/libs.ref/sky130_fd_io/lib/sky130_ef_io__gpiov2_pad_wrapped_ff_ff_n40C_1v95_5v50.lib'
|
||||
Loading db file '/tmp/_pt1rq1IA2x/1.db'
|
||||
Loading db file '/tmp/_pt1rJzc71Z/1.db'
|
||||
Loading db file '/home/passant/OpenLane/pdks/sky130A/libs.ref/sky130_fd_io/lib/sky130_ef_io__vccd_lvc_clamped_pad_ff_n40C_1v95_5v50_5v50.lib'
|
||||
Loading db file '/tmp/_pt1rajH4PC/1.db'
|
||||
Loading db file '/tmp/_pt1rv5Wn02/1.db'
|
||||
Loading db file '/home/passant/OpenLane/pdks/sky130A/libs.ref/sky130_fd_io/lib/sky130_ef_io__vdda_hvc_clamped_pad_ff_n40C_1v95_5v50_5v50.lib'
|
||||
Loading db file '/tmp/_pt1rQtickP/1.db'
|
||||
Loading db file '/tmp/_pt1rbeoDJd/1.db'
|
||||
Loading db file '/home/passant/OpenLane/pdks/sky130A/libs.ref/sky130_fd_io/lib/sky130_ef_io__vssa_hvc_clamped_pad_ff_n40C_1v95_5v50_5v50.lib'
|
||||
Loading db file '/tmp/_pt1re0Fcy5/1.db'
|
||||
Loading db file '/tmp/_pt1r7Lpzfs/1.db'
|
||||
Loading db file '/home/passant/OpenLane/pdks/sky130A/libs.ref/sky130_fd_io/lib/sky130_ef_io__vssd_lvc_clamped3_pad_ff_n40C_1v95_5v50.lib'
|
||||
Loading db file '/tmp/_pt1r4uxBxp/1.db'
|
||||
Loading db file '/tmp/_pt1rvuSCxK/1.db'
|
||||
Loading db file '/home/passant/OpenLane/pdks/sky130A/libs.ref/sky130_fd_io/lib/sky130_ef_io__vccd_lvc_clamped3_pad_ff_n40C_1v95_5v50_5v50.lib'
|
||||
Loading db file '/tmp/_pt1r0RAZhN/1.db'
|
||||
Loading db file '/tmp/_pt1r9hWgB6/1.db'
|
||||
Loading db file '/home/passant/OpenLane/pdks/sky130A/libs.ref/sky130_fd_io/lib/sky130_ef_io__vssd_lvc_clamped_pad_ff_n40C_1v95_5v50.lib'
|
||||
Loading db file '/tmp/_pt1r0aDjNe/1.db'
|
||||
Loading db file '/tmp/_pt1r39vPrw/1.db'
|
||||
Linking design caravan...
|
||||
Warning: Unable to resolve reference to 'sky130_fd_sc_hd__fill_1' in 'caravan'. (LNK-005)
|
||||
Warning: Unable to resolve reference to 'sky130_fd_sc_hd__tapvpwrvgnd_1' in 'caravan'. (LNK-005)
|
||||
|
|
@ -16002,8 +16002,6 @@ Warning: Creating 'clock' on a hierarchical pin 'housekeeping/serial_load'. (UIT
|
|||
[INFO]: Input transition range: 1 : 4
|
||||
[INFO]: Setting derate factor to: 3.75 %
|
||||
1
|
||||
[INFO]: Setting maximum transition of HD cells in slow process corner to: 1.5
|
||||
For HD cells in the hierarchy of caravan
|
||||
Information: Checked out license 'PrimeTime-SI' (PT-019)
|
||||
Information: Log for 'read_parasitics command' will be generated in 'parasitics_command.log'. (PARA-107)
|
||||
Error: All instance paths in the -path option should correspond to valid and same sub-design. (PARA-097)
|
||||
|
|
@ -16115,21 +16113,21 @@ Warning: Some timing arcs have been disabled for breaking timing loops or becaus
|
|||
Warning: Conflicted logic driving pin padframe/flash_io1_pad/DM[0], setting resolved logic value 0 on pin padframe/flash_io1_pad/DM[0]. (PTE-042)
|
||||
Warning: Conflicted logic driving pin padframe/flash_io1_pad/DM[1], setting resolved logic value 1 on pin padframe/flash_io1_pad/DM[1]. (PTE-042)
|
||||
Warning: Conflicted logic driving pin padframe/flash_io1_pad/DM[2], setting resolved logic value 1 on pin padframe/flash_io1_pad/DM[2]. (PTE-042)
|
||||
Warning: No clock-gating check is inferred for clock hkspi_clk at pins gpio_control_in_1[1]/_066_/A1 and gpio_control_in_1[1]/_066_/A2 of cell gpio_control_in_1[1]/_066_. (PTE-060)
|
||||
Warning: No clock-gating check is inferred for clock hkspi_clk at pins gpio_control_in_1[1]/_066_/B1 and gpio_control_in_1[1]/_066_/A2 of cell gpio_control_in_1[1]/_066_. (PTE-060)
|
||||
Warning: No clock-gating check is inferred for clock clk at pins clock_ctrl/_206_/A1 and clock_ctrl/_206_/A0 of cell clock_ctrl/_206_. (PTE-060)
|
||||
Warning: No clock-gating check is inferred for clock clk at pins clock_ctrl/_206_/S and clock_ctrl/_206_/A0 of cell clock_ctrl/_206_. (PTE-060)
|
||||
Warning: No clock-gating check is inferred for clock hkspi_clk at pins housekeeping/_3942_/A1 and housekeeping/_3942_/B2 of cell housekeeping/_3942_. (PTE-060)
|
||||
Warning: No clock-gating check is inferred for clock hkspi_clk at pins housekeeping/_3942_/A2 and housekeeping/_3942_/B2 of cell housekeeping/_3942_. (PTE-060)
|
||||
Warning: No clock-gating check is inferred for clock hkspi_clk at pins housekeeping/_3942_/B1 and housekeeping/_3942_/B2 of cell housekeeping/_3942_. (PTE-060)
|
||||
Warning: No clock-gating check is inferred for clock hkspi_clk at pins gpio_control_in_1[1]/_065_/A2 and gpio_control_in_1[1]/_065_/A1 of cell gpio_control_in_1[1]/_065_. (PTE-060)
|
||||
Warning: No clock-gating check is inferred for clock hkspi_clk at pins gpio_control_in_1[1]/_065_/B1 and gpio_control_in_1[1]/_065_/A1 of cell gpio_control_in_1[1]/_065_. (PTE-060)
|
||||
Warning: No clock-gating check is inferred for clock hkspi_clk at pins housekeeping/_3927_/A0 and housekeeping/_3927_/A1 of cell housekeeping/_3927_. (PTE-060)
|
||||
Warning: No clock-gating check is inferred for clock hkspi_clk at pins housekeeping/_3927_/S and housekeeping/_3927_/A1 of cell housekeeping/_3927_. (PTE-060)
|
||||
Warning: No clock-gating check is inferred for clock hkspi_clk at pins housekeeping/_3942_/A1 and housekeeping/_3942_/B2 of cell housekeeping/_3942_. (PTE-060)
|
||||
Warning: No clock-gating check is inferred for clock hkspi_clk at pins housekeeping/_3942_/A2 and housekeeping/_3942_/B2 of cell housekeeping/_3942_. (PTE-060)
|
||||
Warning: No clock-gating check is inferred for clock hkspi_clk at pins housekeeping/_3942_/B1 and housekeeping/_3942_/B2 of cell housekeeping/_3942_. (PTE-060)
|
||||
Warning: No clock-gating check is inferred for clock hkspi_clk at pins housekeeping/_3945_/A0 and housekeeping/_3945_/A1 of cell housekeeping/_3945_. (PTE-060)
|
||||
Warning: No clock-gating check is inferred for clock hkspi_clk at pins housekeeping/_3945_/S and housekeeping/_3945_/A1 of cell housekeeping/_3945_. (PTE-060)
|
||||
Warning: No clock-gating check is inferred for clock clk at pins clock_ctrl/_206_/A1 and clock_ctrl/_206_/A0 of cell clock_ctrl/_206_. (PTE-060)
|
||||
Warning: No clock-gating check is inferred for clock clk at pins clock_ctrl/_206_/S and clock_ctrl/_206_/A0 of cell clock_ctrl/_206_. (PTE-060)
|
||||
Warning: No clock-gating check is inferred for clock hkspi_clk at pins gpio_control_in_1[1]/_066_/A1 and gpio_control_in_1[1]/_066_/A2 of cell gpio_control_in_1[1]/_066_. (PTE-060)
|
||||
Warning: No clock-gating check is inferred for clock hkspi_clk at pins gpio_control_in_1[1]/_066_/B1 and gpio_control_in_1[1]/_066_/A2 of cell gpio_control_in_1[1]/_066_. (PTE-060)
|
||||
Warning: No clock-gating check is inferred for clock clk at pins clock_ctrl/_205_/A1 and clock_ctrl/_205_/A0 of cell clock_ctrl/_205_. (PTE-060)
|
||||
Warning: No clock-gating check is inferred for clock clk at pins clock_ctrl/_205_/S and clock_ctrl/_205_/A0 of cell clock_ctrl/_205_. (PTE-060)
|
||||
Warning: No clock-gating check is inferred for clock hkspi_clk at pins housekeeping/_3945_/A0 and housekeeping/_3945_/A1 of cell housekeeping/_3945_. (PTE-060)
|
||||
Warning: No clock-gating check is inferred for clock hkspi_clk at pins housekeeping/_3945_/S and housekeeping/_3945_/A1 of cell housekeeping/_3945_. (PTE-060)
|
||||
Information: Inferring 1 clock-gating checks. (PTE-017)
|
||||
Warning: The drive-resistance for the timing arc (sky130_fd_sc_hd__ff_1.95v_-40C/sky130_fd_sc_hd__buf_16) gpio_control_in_1a[2]/output6/A-->X (min rising & falling positive_unate) is much less than the network impedance to ground; PrimeTime has adjusted the drive-resistance to improve accuracy. (RC-009)
|
||||
Warning: The drive-resistance for the timing arc (sky130_fd_sc_hd__ff_1.95v_-40C/sky130_fd_sc_hd__buf_16) gpio_control_in_1a[2]/output6/A-->X (max rising & falling positive_unate) is much less than the network impedance to ground; PrimeTime has adjusted the drive-resistance to improve accuracy. (RC-009)
|
||||
|
|
@ -16161,10 +16159,10 @@ Warning: The drive-resistance for the timing arc (sky130_fd_sc_hd__ff_1.95v_-40C
|
|||
Warning: The drive-resistance for the timing arc (sky130_fd_sc_hd__ff_1.95v_-40C/sky130_fd_sc_hd__buf_12) soc/fanout1680/A-->X (max rising & falling positive_unate) is much less than the network impedance to ground; PrimeTime has adjusted the drive-resistance to improve accuracy. (RC-009)
|
||||
Warning: The drive-resistance for the timing arc (sky130_fd_sc_hd__ff_1.95v_-40C/sky130_fd_sc_hd__buf_12) soc/fanout1685/A-->X (min rising & falling positive_unate) is much less than the network impedance to ground; PrimeTime has adjusted the drive-resistance to improve accuracy. (RC-009)
|
||||
Warning: The drive-resistance for the timing arc (sky130_fd_sc_hd__ff_1.95v_-40C/sky130_fd_sc_hd__buf_12) soc/fanout1685/A-->X (max rising & falling positive_unate) is much less than the network impedance to ground; PrimeTime has adjusted the drive-resistance to improve accuracy. (RC-009)
|
||||
Warning: The drive-resistance for the timing arc (sky130_fd_sc_hd__ff_1.95v_-40C/sky130_fd_sc_hd__buf_12) soc/fanout1689/A-->X (min rising & falling positive_unate) is much less than the network impedance to ground; PrimeTime has adjusted the drive-resistance to improve accuracy. (RC-009)
|
||||
Warning: The drive-resistance for the timing arc (sky130_fd_sc_hd__ff_1.95v_-40C/sky130_fd_sc_hd__buf_12) soc/fanout1687/A-->X (min rising & falling positive_unate) is much less than the network impedance to ground; PrimeTime has adjusted the drive-resistance to improve accuracy. (RC-009)
|
||||
Warning: The drive-resistance for the timing arc (sky130_fd_sc_hd__ff_1.95v_-40C/sky130_fd_sc_hd__buf_12) soc/fanout1689/A-->X (max rising & falling positive_unate) is much less than the network impedance to ground; PrimeTime has adjusted the drive-resistance to improve accuracy. (RC-009)
|
||||
Warning: The drive-resistance for the timing arc (sky130_fd_sc_hd__ff_1.95v_-40C/sky130_fd_sc_hd__buf_12) soc/fanout1687/A-->X (max rising & falling positive_unate) is much less than the network impedance to ground; PrimeTime has adjusted the drive-resistance to improve accuracy. (RC-009)
|
||||
Warning: The drive-resistance for the timing arc (sky130_fd_sc_hd__ff_1.95v_-40C/sky130_fd_sc_hd__buf_12) soc/fanout1689/A-->X (min rising & falling positive_unate) is much less than the network impedance to ground; PrimeTime has adjusted the drive-resistance to improve accuracy. (RC-009)
|
||||
Warning: The drive-resistance for the timing arc (sky130_fd_sc_hd__ff_1.95v_-40C/sky130_fd_sc_hd__buf_12) soc/fanout1689/A-->X (max rising & falling positive_unate) is much less than the network impedance to ground; PrimeTime has adjusted the drive-resistance to improve accuracy. (RC-009)
|
||||
Warning: The drive-resistance for the timing arc (sky130_fd_sc_hd__ff_1.95v_-40C/sky130_fd_sc_hd__buf_12) soc/fanout1693/A-->X (min rising & falling positive_unate) is much less than the network impedance to ground; PrimeTime has adjusted the drive-resistance to improve accuracy. (RC-009)
|
||||
Warning: The drive-resistance for the timing arc (sky130_fd_sc_hd__ff_1.95v_-40C/sky130_fd_sc_hd__buf_12) soc/fanout1693/A-->X (max rising & falling positive_unate) is much less than the network impedance to ground; PrimeTime has adjusted the drive-resistance to improve accuracy. (RC-009)
|
||||
Warning: The drive-resistance for the timing arc (sky130_fd_sc_hd__ff_1.95v_-40C/sky130_fd_sc_hd__buf_12) soc/fanout1741/A-->X (min rising & falling positive_unate) is much less than the network impedance to ground; PrimeTime has adjusted the drive-resistance to improve accuracy. (RC-009)
|
||||
|
|
@ -16225,10 +16223,10 @@ Warning: The drive-resistance for the timing arc (sky130_fd_sc_hd__ff_1.95v_-40C
|
|||
Warning: The drive-resistance for the timing arc (sky130_fd_sc_hd__ff_1.95v_-40C/sky130_fd_sc_hd__buf_12) soc/fanout1618/A-->X (max rising & falling positive_unate) is much less than the network impedance to ground; PrimeTime has adjusted the drive-resistance to improve accuracy. (RC-009)
|
||||
Warning: The drive-resistance for the timing arc (sky130_fd_sc_hd__ff_1.95v_-40C/sky130_fd_sc_hd__buf_12) soc/fanout1630/A-->X (min rising & falling positive_unate) is much less than the network impedance to ground; PrimeTime has adjusted the drive-resistance to improve accuracy. (RC-009)
|
||||
Warning: The drive-resistance for the timing arc (sky130_fd_sc_hd__ff_1.95v_-40C/sky130_fd_sc_hd__buf_12) soc/fanout1630/A-->X (max rising & falling positive_unate) is much less than the network impedance to ground; PrimeTime has adjusted the drive-resistance to improve accuracy. (RC-009)
|
||||
Warning: The drive-resistance for the timing arc (sky130_fd_sc_hd__ff_1.95v_-40C/sky130_fd_sc_hd__buf_12) soc/fanout1632/A-->X (min rising & falling positive_unate) is much less than the network impedance to ground; PrimeTime has adjusted the drive-resistance to improve accuracy. (RC-009)
|
||||
Warning: The drive-resistance for the timing arc (sky130_fd_sc_hd__ff_1.95v_-40C/sky130_fd_sc_hd__buf_12) soc/fanout1632/A-->X (max rising & falling positive_unate) is much less than the network impedance to ground; PrimeTime has adjusted the drive-resistance to improve accuracy. (RC-009)
|
||||
Warning: The drive-resistance for the timing arc (sky130_fd_sc_hd__ff_1.95v_-40C/sky130_fd_sc_hd__buf_12) soc/fanout1631/A-->X (min rising & falling positive_unate) is much less than the network impedance to ground; PrimeTime has adjusted the drive-resistance to improve accuracy. (RC-009)
|
||||
Warning: The drive-resistance for the timing arc (sky130_fd_sc_hd__ff_1.95v_-40C/sky130_fd_sc_hd__buf_12) soc/fanout1631/A-->X (max rising & falling positive_unate) is much less than the network impedance to ground; PrimeTime has adjusted the drive-resistance to improve accuracy. (RC-009)
|
||||
Warning: The drive-resistance for the timing arc (sky130_fd_sc_hd__ff_1.95v_-40C/sky130_fd_sc_hd__buf_12) soc/fanout1632/A-->X (min rising & falling positive_unate) is much less than the network impedance to ground; PrimeTime has adjusted the drive-resistance to improve accuracy. (RC-009)
|
||||
Warning: The drive-resistance for the timing arc (sky130_fd_sc_hd__ff_1.95v_-40C/sky130_fd_sc_hd__buf_12) soc/fanout1632/A-->X (max rising & falling positive_unate) is much less than the network impedance to ground; PrimeTime has adjusted the drive-resistance to improve accuracy. (RC-009)
|
||||
Warning: The drive-resistance for the timing arc (sky130_fd_sc_hd__ff_1.95v_-40C/sky130_fd_sc_hd__buf_12) soc/fanout1634/A-->X (min rising & falling positive_unate) is much less than the network impedance to ground; PrimeTime has adjusted the drive-resistance to improve accuracy. (RC-009)
|
||||
Warning: The drive-resistance for the timing arc (sky130_fd_sc_hd__ff_1.95v_-40C/sky130_fd_sc_hd__buf_12) soc/fanout1634/A-->X (max rising & falling positive_unate) is much less than the network impedance to ground; PrimeTime has adjusted the drive-resistance to improve accuracy. (RC-009)
|
||||
Information: Starting crosstalk aware timing iteration 1. (XTALK-001)
|
||||
|
|
@ -16238,7 +16236,7 @@ Information: Number of nets evaluated in the previous iteration: 59972. (XTALK-1
|
|||
Report : write_sdf /home/passant/caravel/signoff/caravan/primetime-signoff/sdf/nom/caravan.ff.sdf
|
||||
Design : caravan
|
||||
Version: T-2022.03-SP3
|
||||
Date : Sun Oct 30 07:23:52 2022
|
||||
Date : Mon Oct 31 14:24:02 2022
|
||||
****************************************
|
||||
|
||||
Warning: Clock 'hkspi_clk'has source on hierachical pin 'housekeeping/mgmt_gpio_in[4]'. Consider moving to: gpio_control_in_1a[2]/output6/X
|
||||
|
|
@ -16291,13 +16289,12 @@ Warning: The drive-resistance for the timing arc (sky130_fd_sc_hd__ff_1.95v_-40C
|
|||
Warning: The drive-resistance for the timing arc (sky130_fd_sc_hd__ff_1.95v_-40C/sky130_fd_sc_hd__buf_12) housekeeping/output245/A-->X (min rising & falling positive_unate) is much less than the network impedance to ground; PrimeTime has adjusted the drive-resistance to improve accuracy. (RC-009)
|
||||
Warning: The drive-resistance for the timing arc (sky130_fd_sc_hd__ff_1.95v_-40C/sky130_fd_sc_hd__buf_12) housekeeping/output245/A-->X (max rising & falling positive_unate) is much less than the network impedance to ground; PrimeTime has adjusted the drive-resistance to improve accuracy. (RC-009)
|
||||
Information: For model extraction, min_period and min_pulse_width arcs are extracted at the context slew. (MEXT-105)
|
||||
Information: Elapsed time for model extraction: 4 seconds (MEXT-096)
|
||||
Information: Elapsed time for model extraction: 3 seconds (MEXT-096)
|
||||
Wrote the LIB file /home/passant/caravel/signoff/caravan/primetime-signoff/lib/nom/caravan.ff.lib
|
||||
Wrote model to '/home/passant/caravel/signoff/caravan/primetime-signoff/lib/nom/caravan.ff_lib.db'
|
||||
Wrote test design to '/home/passant/caravel/signoff/caravan/primetime-signoff/lib/nom/caravan.ff_test.db'
|
||||
Information: Elapsed time for lib file writing: 1 seconds (MEXT-096)
|
||||
Information: Defining new variable 'verilog'. (CMD-041)
|
||||
Information: Defining new variable 'max_tran'. (CMD-041)
|
||||
Suppressed Messages Summary:
|
||||
Id Severity Occurrences Suppressed
|
||||
-------------------------------------------------------------------------------
|
||||
|
|
@ -16308,10 +16305,10 @@ RC-009 Warning 277 135
|
|||
LNK-043 Information 190190 190090
|
||||
SVR-2 Information 2 2
|
||||
Total 6 types of messages are suppressed
|
||||
Maximum memory usage for this session: 2782.31 MB
|
||||
CPU usage for this session: 207 seconds
|
||||
Elapsed time for this session: 78 seconds
|
||||
Diagnostics summary: 69 errors, 287 warnings, 124 informationals
|
||||
Maximum memory usage for this session: 2795.19 MB
|
||||
CPU usage for this session: 209 seconds
|
||||
Elapsed time for this session: 79 seconds
|
||||
Diagnostics summary: 69 errors, 287 warnings, 123 informationals
|
||||
|
||||
Thank you for using pt_shell!
|
||||
STA run Passed!
|
||||
|
|
@ -61,7 +61,7 @@ if {\
|
|||
# -filter is supported by PT but not in the read_sdc
|
||||
# add max_tran constraint as the default max_tran of the ss hd SCL is 10 so the violations are not caught in ss corners
|
||||
# apply the constraint to hd cells at the ss corner on caravel/caravan
|
||||
if {$::env(PROC_CORNER) == "s" & $::env(DESIGN) == "caravel" | $::env(DESIGN) == "caravan" } {
|
||||
if { $::env(DESIGN) == "caravel" | $::env(DESIGN) == "caravan" & $::env(PROC_CORNER) == "s" } {
|
||||
set max_tran 1.5
|
||||
puts "\[INFO\]: Setting maximum transition of HD cells in slow process corner to: $max_tran"
|
||||
puts "For HD cells in the hierarchy of $::env(DESIGN)"
|
||||
|
|
@ -5100,8 +5100,8 @@ Warning: Line 171, Cell 'sky130_ef_io__vssd_lvc_clamped_pad', pin 'AMUXBUS_B', T
|
|||
Technology library 'sky130_ef_io__vssd_lvc_clamped_pad_ss_100C_1v60_3v00' read successfully
|
||||
Loading verilog file '/home/passant/caravel_mgmt_soc_litex/verilog/gl/RAM128.v'
|
||||
Loading db file '/home/passant/caravel/scripts/pt_libs/scs130hd_ss_1.40v_100C.lib'
|
||||
Loading verilog file '/home/passant/caravel_mgmt_soc_litex/verilog/gl/mgmt_core_wrapper.v'
|
||||
Loading verilog file '/home/passant/caravel_mgmt_soc_litex/verilog/gl/RAM256.v'
|
||||
Loading verilog file '/home/passant/caravel_mgmt_soc_litex/verilog/gl/mgmt_core_wrapper.v'
|
||||
Loading verilog file '/home/passant/caravel/verilog/gl/mgmt_protect.v'
|
||||
Loading verilog file '/home/passant/caravel/verilog/gl/housekeeping.v'
|
||||
Loading verilog file '/home/passant/caravel/verilog/gl/caravel.v'
|
||||
|
|
@ -5133,25 +5133,25 @@ Loading verilog file '/home/passant/caravel/verilog/gl/gpio_logic_high.v'
|
|||
Loading verilog file '/home/passant/caravel/verilog/gl/xres_buf.v'
|
||||
Loading verilog file '/home/passant/caravel/verilog/gl/constant_block.v'
|
||||
Loading verilog file '/home/passant/caravel/verilog/gl/mgmt_protect_hv.v'
|
||||
Loading db file '/tmp/_pt1ridW85K/1.db'
|
||||
Loading db file '/tmp/_pt1rVpn8im/1.db'
|
||||
Loading db file '/home/passant/caravel/scripts/pt_libs/scs130hvl_ss_3.00v_100C.lib'
|
||||
Loading db file '/tmp/_pt1rFVYQ6k/1.db'
|
||||
Loading db file '/tmp/_pt1rsbyvNC/1.db'
|
||||
Loading db file '/home/passant/OpenLane/pdks/sky130A/libs.ref/sky130_fd_io/lib/sky130_fd_io__top_xres4v2_ss_ss_100C_1v60_3v00.lib'
|
||||
Loading db file '/tmp/_pt1rUd3Fja/1.db'
|
||||
Loading db file '/tmp/_pt1r5A6j57/1.db'
|
||||
Loading db file '/home/passant/OpenLane/pdks/sky130A/libs.ref/sky130_fd_io/lib/sky130_ef_io__gpiov2_pad_wrapped_ss_ss_100C_1v60_3v00.lib'
|
||||
Loading db file '/tmp/_pt1rxHsYU4/1.db'
|
||||
Loading db file '/tmp/_pt1rm2f2sI/1.db'
|
||||
Loading db file '/home/passant/OpenLane/pdks/sky130A/libs.ref/sky130_fd_io/lib/sky130_ef_io__vccd_lvc_clamped_pad_ss_100C_1v60_3v00_3v00.lib'
|
||||
Loading db file '/tmp/_pt1rkNfY03/1.db'
|
||||
Loading db file '/tmp/_pt1rfOFH8m/1.db'
|
||||
Loading db file '/home/passant/OpenLane/pdks/sky130A/libs.ref/sky130_fd_io/lib/sky130_ef_io__vdda_hvc_clamped_pad_ss_100C_1v60_3v00_3v00.lib'
|
||||
Loading db file '/tmp/_pt1rr9Vte7/1.db'
|
||||
Loading db file '/tmp/_pt1r82gUO5/1.db'
|
||||
Loading db file '/home/passant/OpenLane/pdks/sky130A/libs.ref/sky130_fd_io/lib/sky130_ef_io__vssa_hvc_clamped_pad_ss_100C_1v60_3v00_3v00.lib'
|
||||
Loading db file '/tmp/_pt1r6FNlee/1.db'
|
||||
Loading db file '/tmp/_pt1rxfTEgS/1.db'
|
||||
Loading db file '/home/passant/OpenLane/pdks/sky130A/libs.ref/sky130_fd_io/lib/sky130_ef_io__vssd_lvc_clamped3_pad_ss_100C_1v60_3v00.lib'
|
||||
Loading db file '/tmp/_pt1rDmto0o/1.db'
|
||||
Loading db file '/tmp/_pt1rmDrmuI/1.db'
|
||||
Loading db file '/home/passant/OpenLane/pdks/sky130A/libs.ref/sky130_fd_io/lib/sky130_ef_io__vccd_lvc_clamped3_pad_ss_100C_1v60_3v00_3v00.lib'
|
||||
Loading db file '/tmp/_pt1rOkNBAD/1.db'
|
||||
Loading db file '/tmp/_pt1r91j0vC/1.db'
|
||||
Loading db file '/home/passant/OpenLane/pdks/sky130A/libs.ref/sky130_fd_io/lib/sky130_ef_io__vssd_lvc_clamped_pad_ss_100C_1v60_3v00.lib'
|
||||
Loading db file '/tmp/_pt1rpir1XV/1.db'
|
||||
Loading db file '/tmp/_pt1rAgaFkA/1.db'
|
||||
Linking design caravan...
|
||||
Warning: Unable to resolve reference to 'sky130_fd_sc_hd__fill_1' in 'caravan'. (LNK-005)
|
||||
Warning: Unable to resolve reference to 'sky130_fd_sc_hd__tapvpwrvgnd_1' in 'caravan'. (LNK-005)
|
||||
|
|
@ -5458,21 +5458,21 @@ Warning: Some timing arcs have been disabled for breaking timing loops or becaus
|
|||
Warning: Conflicted logic driving pin padframe/flash_io1_pad/DM[0], setting resolved logic value 0 on pin padframe/flash_io1_pad/DM[0]. (PTE-042)
|
||||
Warning: Conflicted logic driving pin padframe/flash_io1_pad/DM[1], setting resolved logic value 1 on pin padframe/flash_io1_pad/DM[1]. (PTE-042)
|
||||
Warning: Conflicted logic driving pin padframe/flash_io1_pad/DM[2], setting resolved logic value 1 on pin padframe/flash_io1_pad/DM[2]. (PTE-042)
|
||||
Warning: No clock-gating check is inferred for clock hkspi_clk at pins housekeeping/_3942_/A1 and housekeeping/_3942_/B2 of cell housekeeping/_3942_. (PTE-060)
|
||||
Warning: No clock-gating check is inferred for clock hkspi_clk at pins housekeeping/_3942_/A2 and housekeeping/_3942_/B2 of cell housekeeping/_3942_. (PTE-060)
|
||||
Warning: No clock-gating check is inferred for clock hkspi_clk at pins housekeeping/_3942_/B1 and housekeeping/_3942_/B2 of cell housekeeping/_3942_. (PTE-060)
|
||||
Warning: No clock-gating check is inferred for clock hkspi_clk at pins housekeeping/_3945_/A0 and housekeeping/_3945_/A1 of cell housekeeping/_3945_. (PTE-060)
|
||||
Warning: No clock-gating check is inferred for clock hkspi_clk at pins housekeeping/_3945_/S and housekeeping/_3945_/A1 of cell housekeeping/_3945_. (PTE-060)
|
||||
Warning: No clock-gating check is inferred for clock hkspi_clk at pins gpio_control_in_1[1]/_065_/A2 and gpio_control_in_1[1]/_065_/A1 of cell gpio_control_in_1[1]/_065_. (PTE-060)
|
||||
Warning: No clock-gating check is inferred for clock hkspi_clk at pins gpio_control_in_1[1]/_065_/B1 and gpio_control_in_1[1]/_065_/A1 of cell gpio_control_in_1[1]/_065_. (PTE-060)
|
||||
Warning: No clock-gating check is inferred for clock clk at pins clock_ctrl/_205_/A1 and clock_ctrl/_205_/A0 of cell clock_ctrl/_205_. (PTE-060)
|
||||
Warning: No clock-gating check is inferred for clock clk at pins clock_ctrl/_205_/S and clock_ctrl/_205_/A0 of cell clock_ctrl/_205_. (PTE-060)
|
||||
Warning: No clock-gating check is inferred for clock clk at pins clock_ctrl/_206_/A1 and clock_ctrl/_206_/A0 of cell clock_ctrl/_206_. (PTE-060)
|
||||
Warning: No clock-gating check is inferred for clock clk at pins clock_ctrl/_206_/S and clock_ctrl/_206_/A0 of cell clock_ctrl/_206_. (PTE-060)
|
||||
Warning: No clock-gating check is inferred for clock hkspi_clk at pins housekeeping/_3942_/A1 and housekeeping/_3942_/B2 of cell housekeeping/_3942_. (PTE-060)
|
||||
Warning: No clock-gating check is inferred for clock hkspi_clk at pins housekeeping/_3942_/A2 and housekeeping/_3942_/B2 of cell housekeeping/_3942_. (PTE-060)
|
||||
Warning: No clock-gating check is inferred for clock hkspi_clk at pins housekeeping/_3942_/B1 and housekeeping/_3942_/B2 of cell housekeeping/_3942_. (PTE-060)
|
||||
Warning: No clock-gating check is inferred for clock hkspi_clk at pins gpio_control_in_1[1]/_066_/A1 and gpio_control_in_1[1]/_066_/A2 of cell gpio_control_in_1[1]/_066_. (PTE-060)
|
||||
Warning: No clock-gating check is inferred for clock hkspi_clk at pins gpio_control_in_1[1]/_066_/B1 and gpio_control_in_1[1]/_066_/A2 of cell gpio_control_in_1[1]/_066_. (PTE-060)
|
||||
Warning: No clock-gating check is inferred for clock hkspi_clk at pins gpio_control_in_1[1]/_065_/A2 and gpio_control_in_1[1]/_065_/A1 of cell gpio_control_in_1[1]/_065_. (PTE-060)
|
||||
Warning: No clock-gating check is inferred for clock hkspi_clk at pins gpio_control_in_1[1]/_065_/B1 and gpio_control_in_1[1]/_065_/A1 of cell gpio_control_in_1[1]/_065_. (PTE-060)
|
||||
Warning: No clock-gating check is inferred for clock hkspi_clk at pins housekeeping/_3927_/A0 and housekeeping/_3927_/A1 of cell housekeeping/_3927_. (PTE-060)
|
||||
Warning: No clock-gating check is inferred for clock hkspi_clk at pins housekeeping/_3927_/S and housekeeping/_3927_/A1 of cell housekeeping/_3927_. (PTE-060)
|
||||
Warning: No clock-gating check is inferred for clock hkspi_clk at pins housekeeping/_3945_/A0 and housekeeping/_3945_/A1 of cell housekeeping/_3945_. (PTE-060)
|
||||
Warning: No clock-gating check is inferred for clock hkspi_clk at pins housekeeping/_3945_/S and housekeeping/_3945_/A1 of cell housekeeping/_3945_. (PTE-060)
|
||||
Warning: No clock-gating check is inferred for clock hkspi_clk at pins gpio_control_in_1[1]/_066_/A1 and gpio_control_in_1[1]/_066_/A2 of cell gpio_control_in_1[1]/_066_. (PTE-060)
|
||||
Warning: No clock-gating check is inferred for clock hkspi_clk at pins gpio_control_in_1[1]/_066_/B1 and gpio_control_in_1[1]/_066_/A2 of cell gpio_control_in_1[1]/_066_. (PTE-060)
|
||||
Information: Inferring 1 clock-gating checks. (PTE-017)
|
||||
Information: Starting crosstalk aware timing iteration 1. (XTALK-001)
|
||||
Information: Starting crosstalk aware timing iteration 2. (XTALK-001)
|
||||
|
|
@ -5481,7 +5481,7 @@ Information: Number of nets evaluated in the previous iteration: 59840. (XTALK-1
|
|||
Report : write_sdf /home/passant/caravel/signoff/caravan/primetime-signoff/sdf/nom/caravan.ss.sdf
|
||||
Design : caravan
|
||||
Version: T-2022.03-SP3
|
||||
Date : Sun Oct 30 07:20:08 2022
|
||||
Date : Mon Oct 31 14:20:15 2022
|
||||
****************************************
|
||||
|
||||
Warning: Clock 'hkspi_clk'has source on hierachical pin 'housekeeping/mgmt_gpio_in[4]'. Consider moving to: gpio_control_in_1a[2]/output6/X
|
||||
|
|
@ -5508,9 +5508,9 @@ PARA-040 Warning 321678 320929
|
|||
LNK-043 Information 190193 190093
|
||||
SVR-2 Information 2 2
|
||||
Total 5 types of messages are suppressed
|
||||
Maximum memory usage for this session: 2811.06 MB
|
||||
CPU usage for this session: 213 seconds
|
||||
Elapsed time for this session: 73 seconds
|
||||
Maximum memory usage for this session: 2825.96 MB
|
||||
CPU usage for this session: 211 seconds
|
||||
Elapsed time for this session: 72 seconds
|
||||
Diagnostics summary: 69 errors, 147 warnings, 124 informationals
|
||||
|
||||
Thank you for using pt_shell!
|
||||
|
|
|
|||
|
|
@ -61,7 +61,7 @@ if {\
|
|||
# -filter is supported by PT but not in the read_sdc
|
||||
# add max_tran constraint as the default max_tran of the ss hd SCL is 10 so the violations are not caught in ss corners
|
||||
# apply the constraint to hd cells at the ss corner on caravel/caravan
|
||||
if {$::env(PROC_CORNER) == "s" & $::env(DESIGN) == "caravel" | $::env(DESIGN) == "caravan" } {
|
||||
if { $::env(DESIGN) == "caravel" | $::env(DESIGN) == "caravan" & $::env(PROC_CORNER) == "s" } {
|
||||
set max_tran 1.5
|
||||
puts "\[INFO\]: Setting maximum transition of HD cells in slow process corner to: $max_tran"
|
||||
puts "For HD cells in the hierarchy of $::env(DESIGN)"
|
||||
|
|
@ -5468,27 +5468,27 @@ Loading verilog file '/home/passant/caravel/verilog/gl/gpio_logic_high.v'
|
|||
Loading verilog file '/home/passant/caravel/verilog/gl/xres_buf.v'
|
||||
Loading verilog file '/home/passant/caravel/verilog/gl/constant_block.v'
|
||||
Loading verilog file '/home/passant/caravel/verilog/gl/mgmt_protect_hv.v'
|
||||
Loading db file '/tmp/_pt1reXkMBu/1.db'
|
||||
Loading db file '/tmp/_pt1rvSiYMa/1.db'
|
||||
Loading db file '/home/passant/caravel/scripts/pt_libs/scs130hvl_tt_3.3v_25C.lib'
|
||||
Loading db file '/tmp/_pt1rGRayrq/1.db'
|
||||
Loading db file '/tmp/_pt1rKQPZe5/1.db'
|
||||
Loading db file '/home/passant/caravel/scripts/pt_libs/scs130hvl_tt_3.3v_lowhv_3.3v_lv_1.8v_25C.lib'
|
||||
Loading db file '/tmp/_pt1rekkcTB/1.db'
|
||||
Loading db file '/tmp/_pt1rjxO5tf/1.db'
|
||||
Loading db file '/home/passant/OpenLane/pdks/sky130A/libs.ref/sky130_fd_io/lib/sky130_fd_io__top_xres4v2_tt_tt_025C_1v80_3v30.lib'
|
||||
Loading db file '/tmp/_pt1r84AG1S/1.db'
|
||||
Loading db file '/tmp/_pt1rGdnLsv/1.db'
|
||||
Loading db file '/home/passant/OpenLane/pdks/sky130A/libs.ref/sky130_fd_io/lib/sky130_ef_io__gpiov2_pad_tt_tt_025C_1v80_3v30.lib'
|
||||
Loading db file '/tmp/_pt1rUkAj7d/1.db'
|
||||
Loading db file '/tmp/_pt1rFkwdqP/1.db'
|
||||
Loading db file '/home/passant/OpenLane/pdks/sky130A/libs.ref/sky130_fd_io/lib/sky130_ef_io__vccd_lvc_clamped_pad_tt_025C_1v80_3v30_3v30.lib'
|
||||
Loading db file '/tmp/_pt1riSp5GD/1.db'
|
||||
Loading db file '/tmp/_pt1rwjYREd/1.db'
|
||||
Loading db file '/home/passant/OpenLane/pdks/sky130A/libs.ref/sky130_fd_io/lib/sky130_ef_io__vdda_hvc_clamped_pad_tt_025C_1v80_3v30_3v30.lib'
|
||||
Loading db file '/tmp/_pt1re9x6m7/1.db'
|
||||
Loading db file '/tmp/_pt1rbwBbVF/1.db'
|
||||
Loading db file '/home/passant/OpenLane/pdks/sky130A/libs.ref/sky130_fd_io/lib/sky130_ef_io__vssa_hvc_clamped_pad_tt_025C_1v80_3v30_3v30.lib'
|
||||
Loading db file '/tmp/_pt1rwYHENE/1.db'
|
||||
Loading db file '/tmp/_pt1rudor5b/1.db'
|
||||
Loading db file '/home/passant/OpenLane/pdks/sky130A/libs.ref/sky130_fd_io/lib/sky130_ef_io__vssd_lvc_clamped3_pad_tt_025C_1v80_3v30.lib'
|
||||
Loading db file '/tmp/_pt1rILmWZf/1.db'
|
||||
Loading db file '/tmp/_pt1rhDCk7L/1.db'
|
||||
Loading db file '/home/passant/OpenLane/pdks/sky130A/libs.ref/sky130_fd_io/lib/sky130_ef_io__vccd_lvc_clamped3_pad_tt_025C_1v80_3v30_3v30.lib'
|
||||
Loading db file '/tmp/_pt1ryZBJXU/1.db'
|
||||
Loading db file '/tmp/_pt1rSU1T5p/1.db'
|
||||
Loading db file '/home/passant/OpenLane/pdks/sky130A/libs.ref/sky130_fd_io/lib/sky130_ef_io__vssd_lvc_clamped_pad_tt_025C_1v80_3v30.lib'
|
||||
Loading db file '/tmp/_pt1rck5GGD/1.db'
|
||||
Loading db file '/tmp/_pt1rBnT1V7/1.db'
|
||||
Linking design caravan...
|
||||
Warning: Unable to resolve reference to 'sky130_fd_sc_hd__fill_1' in 'caravan'. (LNK-005)
|
||||
Warning: Unable to resolve reference to 'sky130_fd_sc_hd__tapvpwrvgnd_1' in 'caravan'. (LNK-005)
|
||||
|
|
@ -5680,8 +5680,6 @@ Warning: Creating 'clock' on a hierarchical pin 'housekeeping/serial_load'. (UIT
|
|||
[INFO]: Input transition range: 1 : 4
|
||||
[INFO]: Setting derate factor to: 3.75 %
|
||||
1
|
||||
[INFO]: Setting maximum transition of HD cells in slow process corner to: 1.5
|
||||
For HD cells in the hierarchy of caravan:
|
||||
Information: Checked out license 'PrimeTime-SI' (PT-019)
|
||||
Information: Log for 'read_parasitics command' will be generated in 'parasitics_command.log'. (PARA-107)
|
||||
Error: All instance paths in the -path option should correspond to valid and same sub-design. (PARA-097)
|
||||
|
|
@ -5793,21 +5791,21 @@ Warning: Some timing arcs have been disabled for breaking timing loops or becaus
|
|||
Warning: Conflicted logic driving pin padframe/flash_io1_pad/DM[0], setting resolved logic value 0 on pin padframe/flash_io1_pad/DM[0]. (PTE-042)
|
||||
Warning: Conflicted logic driving pin padframe/flash_io1_pad/DM[1], setting resolved logic value 1 on pin padframe/flash_io1_pad/DM[1]. (PTE-042)
|
||||
Warning: Conflicted logic driving pin padframe/flash_io1_pad/DM[2], setting resolved logic value 1 on pin padframe/flash_io1_pad/DM[2]. (PTE-042)
|
||||
Warning: No clock-gating check is inferred for clock hkspi_clk at pins housekeeping/_3927_/A0 and housekeeping/_3927_/A1 of cell housekeeping/_3927_. (PTE-060)
|
||||
Warning: No clock-gating check is inferred for clock hkspi_clk at pins housekeeping/_3927_/S and housekeeping/_3927_/A1 of cell housekeeping/_3927_. (PTE-060)
|
||||
Warning: No clock-gating check is inferred for clock hkspi_clk at pins housekeeping/_3945_/A0 and housekeeping/_3945_/A1 of cell housekeeping/_3945_. (PTE-060)
|
||||
Warning: No clock-gating check is inferred for clock hkspi_clk at pins housekeeping/_3945_/S and housekeeping/_3945_/A1 of cell housekeeping/_3945_. (PTE-060)
|
||||
Warning: No clock-gating check is inferred for clock hkspi_clk at pins housekeeping/_3942_/A1 and housekeeping/_3942_/B2 of cell housekeeping/_3942_. (PTE-060)
|
||||
Warning: No clock-gating check is inferred for clock hkspi_clk at pins housekeeping/_3942_/A2 and housekeeping/_3942_/B2 of cell housekeeping/_3942_. (PTE-060)
|
||||
Warning: No clock-gating check is inferred for clock hkspi_clk at pins housekeeping/_3942_/B1 and housekeeping/_3942_/B2 of cell housekeeping/_3942_. (PTE-060)
|
||||
Warning: No clock-gating check is inferred for clock hkspi_clk at pins gpio_control_in_1[1]/_065_/A2 and gpio_control_in_1[1]/_065_/A1 of cell gpio_control_in_1[1]/_065_. (PTE-060)
|
||||
Warning: No clock-gating check is inferred for clock hkspi_clk at pins gpio_control_in_1[1]/_065_/B1 and gpio_control_in_1[1]/_065_/A1 of cell gpio_control_in_1[1]/_065_. (PTE-060)
|
||||
Warning: No clock-gating check is inferred for clock clk at pins clock_ctrl/_205_/A1 and clock_ctrl/_205_/A0 of cell clock_ctrl/_205_. (PTE-060)
|
||||
Warning: No clock-gating check is inferred for clock clk at pins clock_ctrl/_205_/S and clock_ctrl/_205_/A0 of cell clock_ctrl/_205_. (PTE-060)
|
||||
Warning: No clock-gating check is inferred for clock hkspi_clk at pins housekeeping/_3945_/A0 and housekeeping/_3945_/A1 of cell housekeeping/_3945_. (PTE-060)
|
||||
Warning: No clock-gating check is inferred for clock hkspi_clk at pins housekeeping/_3945_/S and housekeeping/_3945_/A1 of cell housekeeping/_3945_. (PTE-060)
|
||||
Warning: No clock-gating check is inferred for clock hkspi_clk at pins gpio_control_in_1[1]/_066_/A1 and gpio_control_in_1[1]/_066_/A2 of cell gpio_control_in_1[1]/_066_. (PTE-060)
|
||||
Warning: No clock-gating check is inferred for clock hkspi_clk at pins gpio_control_in_1[1]/_066_/B1 and gpio_control_in_1[1]/_066_/A2 of cell gpio_control_in_1[1]/_066_. (PTE-060)
|
||||
Warning: No clock-gating check is inferred for clock hkspi_clk at pins housekeeping/_3927_/A0 and housekeeping/_3927_/A1 of cell housekeeping/_3927_. (PTE-060)
|
||||
Warning: No clock-gating check is inferred for clock hkspi_clk at pins housekeeping/_3927_/S and housekeeping/_3927_/A1 of cell housekeeping/_3927_. (PTE-060)
|
||||
Warning: No clock-gating check is inferred for clock clk at pins clock_ctrl/_206_/A1 and clock_ctrl/_206_/A0 of cell clock_ctrl/_206_. (PTE-060)
|
||||
Warning: No clock-gating check is inferred for clock clk at pins clock_ctrl/_206_/S and clock_ctrl/_206_/A0 of cell clock_ctrl/_206_. (PTE-060)
|
||||
Warning: No clock-gating check is inferred for clock hkspi_clk at pins gpio_control_in_1[1]/_066_/A1 and gpio_control_in_1[1]/_066_/A2 of cell gpio_control_in_1[1]/_066_. (PTE-060)
|
||||
Warning: No clock-gating check is inferred for clock hkspi_clk at pins gpio_control_in_1[1]/_066_/B1 and gpio_control_in_1[1]/_066_/A2 of cell gpio_control_in_1[1]/_066_. (PTE-060)
|
||||
Warning: No clock-gating check is inferred for clock clk at pins clock_ctrl/_205_/A1 and clock_ctrl/_205_/A0 of cell clock_ctrl/_205_. (PTE-060)
|
||||
Warning: No clock-gating check is inferred for clock clk at pins clock_ctrl/_205_/S and clock_ctrl/_205_/A0 of cell clock_ctrl/_205_. (PTE-060)
|
||||
Information: Inferring 1 clock-gating checks. (PTE-017)
|
||||
Warning: The drive-resistance for the timing arc (sky130_fd_sc_hd__tt_1.80v_25C/sky130_fd_sc_hd__buf_12) soc/wire1964/A-->X (min rising & falling positive_unate) is much less than the network impedance to ground; PrimeTime has adjusted the drive-resistance to improve accuracy. (RC-009)
|
||||
Warning: The drive-resistance for the timing arc (sky130_fd_sc_hd__tt_1.80v_25C/sky130_fd_sc_hd__buf_12) soc/wire1964/A-->X (max rising & falling positive_unate) is much less than the network impedance to ground; PrimeTime has adjusted the drive-resistance to improve accuracy. (RC-009)
|
||||
|
|
@ -5876,7 +5874,7 @@ Information: Number of nets evaluated in the previous iteration: 59894. (XTALK-1
|
|||
Report : write_sdf /home/passant/caravel/signoff/caravan/primetime-signoff/sdf/nom/caravan.tt.sdf
|
||||
Design : caravan
|
||||
Version: T-2022.03-SP3
|
||||
Date : Sun Oct 30 07:16:23 2022
|
||||
Date : Mon Oct 31 14:16:32 2022
|
||||
****************************************
|
||||
|
||||
Warning: Clock 'hkspi_clk'has source on hierachical pin 'housekeeping/mgmt_gpio_in[4]'. Consider moving to: gpio_control_in_1a[2]/output6/X
|
||||
|
|
@ -5907,9 +5905,8 @@ Information: Elapsed time for model extraction: 4 seconds (MEXT-096)
|
|||
Wrote the LIB file /home/passant/caravel/signoff/caravan/primetime-signoff/lib/nom/caravan.tt.lib
|
||||
Wrote model to '/home/passant/caravel/signoff/caravan/primetime-signoff/lib/nom/caravan.tt_lib.db'
|
||||
Wrote test design to '/home/passant/caravel/signoff/caravan/primetime-signoff/lib/nom/caravan.tt_test.db'
|
||||
Information: Elapsed time for lib file writing: 1 seconds (MEXT-096)
|
||||
Information: Elapsed time for lib file writing: 0 seconds (MEXT-096)
|
||||
Information: Defining new variable 'verilog'. (CMD-041)
|
||||
Information: Defining new variable 'max_tran'. (CMD-041)
|
||||
Suppressed Messages Summary:
|
||||
Id Severity Occurrences Suppressed
|
||||
-------------------------------------------------------------------------------
|
||||
|
|
@ -5919,10 +5916,10 @@ PARA-040 Warning 321678 320929
|
|||
LNK-043 Information 190190 190090
|
||||
SVR-2 Information 2 2
|
||||
Total 5 types of messages are suppressed
|
||||
Maximum memory usage for this session: 2802.90 MB
|
||||
CPU usage for this session: 213 seconds
|
||||
Maximum memory usage for this session: 2810.65 MB
|
||||
CPU usage for this session: 209 seconds
|
||||
Elapsed time for this session: 73 seconds
|
||||
Diagnostics summary: 69 errors, 221 warnings, 124 informationals
|
||||
Diagnostics summary: 69 errors, 221 warnings, 123 informationals
|
||||
|
||||
Thank you for using pt_shell!
|
||||
STA run Passed!
|
||||
|
|
|
|||
Loading…
Reference in New Issue