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940 Commits

Author SHA1 Message Date
kareem 3a81dde555 add sky130_fd_sc_hd__macro_sparecell inside gpio_control_block rtl 2022-10-10 05:24:25 -07:00
kareefardi 623be602c2 Apply automatic changes to Manifest and README.rst 2022-10-10 12:22:26 +00:00
kareem 71e309a923 some rtl changes 
- remove unused port in chip_io
- move the rest of chip_io power ports to the USE_POWER_PINS guard
- add caravel_power_routing cell guarded by TOP_ROUTING ifdef
 2022-10-10 05:13:48 -07:00
Mohamed Shalan cbcef378ad
Merge pull request #163 from mo-hosni/caravel_redesign 
Caravel redesign
 2022-10-10 14:13:06 +02:00
Mohamed Hosni 40098f693e
Merge branch 'efabless:caravel_redesign' into caravel_redesign 2022-10-10 05:08:33 -07:00
kareefardi ace9274138 Apply automatic changes to Manifest and README.rst 2022-10-10 12:07:13 +00:00
M0stafaRady 0006ae4f25 Apply automatic changes to Manifest and README.rst 2022-10-10 12:06:07 +00:00
kareem 11620eb224 Merge branch 'caravel_redesign' of github.com:efabless/caravel into caravel_redesign 2022-10-10 05:05:48 -07:00
M0stafaRady 0f0a495906 merge with caravel_redesign 2022-10-10 05:04:44 -07:00
kareem 285ef6b642 reharden!: caravel 
~ update the following views:
def
mag
verilog
spef(all corners)
+ add the ability to override the interactive script filename
+ add the ability to run openlane regression using regression.config
file
~ change GRT ADJUSTMENT values
~ change pointers to some files for workarounds

!important the interactive script still needs updates
!important this was done using old openlane v0.22 and its matching
pdk
!important known workarounds:
- a custom techlef is used where large metal spacing rules are the
only ones present to avoid violations by the router
- some odd behaviour happening when a macro has a lef view
with a non zero origin. so the power routing cell is (temporarily)
modified to have a zero origin and its placement has been shifted
which doesn't match the power routing mag.
- the old openlane doesn't generate multi spef corners. they
are generated using timing-scripts repo
 2022-10-10 04:51:05 -07:00
M0stafaRady 688429eeda move caravel.py, cpu.py ... to interfaces directory 2022-10-10 04:50:45 -07:00
M0stafaRady dd6fb6cfc4 Merge branch 'cocotb' of github.com:efabless/caravel into cocotb 2022-10-10 04:35:35 -07:00
M0stafaRady 45a885caaa update verify_cocotb script to be dependent on CARAVEL_ROOT and MCW_ROOT 2022-10-10 04:34:26 -07:00
Marwan Abbas a8934d66cc fixes for logging and sta running 2022-10-10 13:25:09 +02:00
Mohamed Shalan f5b8b0ab7c
Merge pull request #162 from efabless/chip_io_rework_update 
Update of all views of chip_io and chip_io_alt
 2022-10-10 12:18:42 +02:00
Mohamed Hosni fa441babea
Merge branch 'efabless:caravel_redesign' into caravel_redesign 2022-10-10 01:24:24 -07:00
mo-hosni 7a7690ba10 Update housekeeping 2022-10-10 01:21:51 -07:00
mo-hosni 7e5891dd9f Update mgmt_protect 2022-10-10 01:19:40 -07:00
Tim Edwards 2459b3583e Updated all views of chip_io and chip_io_alt based on the abstract 
view of constant_block which was recently merged into the repository.
The constant_block instance positions and connections were modified
slightly to avoid routing over obstruction areas.
 2022-10-09 14:20:43 -04:00
Marwan Abbas a3dd90fc61 build script fixes 2022-10-09 20:11:42 +02:00
Marwan Abbas 943a503441 run sta in parallel with drc, lvs and verification 2022-10-09 20:10:28 +02:00
Marwan Abbas ccb9a90977 added klayout drc python script 2022-10-09 19:55:27 +02:00
Marwan Abbas 82fcb3a54d remove unnecessary prints 2022-10-09 19:43:17 +02:00
Marwan Abbas ecc06078b9 added signoff automation script + supporting scripts 2022-10-09 19:36:50 +02:00
Passant 855ea54add add reading multicorner spef generated from OL 2022-10-09 10:26:01 -07:00
M0stafaRady f0037c35fd Apply automatic changes to Manifest and README.rst 2022-10-09 14:54:31 +00:00
M0stafaRady 00364eb092 Add gpio_all_o_user test 2022-10-09 07:53:25 -07:00
Passant 127057eb4b Merge branch 'caravel_redesign' of github.com:efabless/caravel into caravel_redesign 2022-10-09 07:40:56 -07:00
Passant ef688785f3 add script to run STA [in review] 2022-10-09 07:40:32 -07:00
Mohamed Shalan 7538c8c776
Merge pull request #161 from efabless/chip_io_rework 2022-10-09 16:31:28 +02:00
M0stafaRady d6f002cd70 Merge branch 'cocotb' of github.com:efabless/caravel into cocotb 2022-10-09 06:07:28 -07:00
M0stafaRady 1690c8e068 enhance gpio_all_o test 2022-10-09 06:07:19 -07:00
M0stafaRady 08229d6a9b Add gpio_all_bidir test but it still not working yet 2022-10-09 05:08:12 -07:00
Passant a5d73caf34 add script to run PrimeTime STA [in review] 2022-10-09 03:23:01 -07:00
Passant 36b1f0d62f add signoff `sdc` for top level caravel and 
submodules: housekeeping and `gpio_control_block`
 2022-10-09 03:12:36 -07:00
Mohamed Shalan e9d45569d6
Merge pull request #158 from mo-hosni/caravel_redesign 2022-10-09 11:17:38 +02:00
Tim Edwards eceb71ee04 Added GDS, DEF, and LEF views of both chip_io and chip_io_alt. 2022-10-08 22:24:38 -04:00
Tim Edwards bd4f053ec1 Updated I/O layouts with constant_block instances from M. Hosni's 
fork of caravel (layout .mag file not copied into this commit).
The layouts of both chip_io and chip_io_alt are believed to be
complete, but need verification (with LVS).
 2022-10-08 16:48:59 -04:00
mo-hosni da9e607760 added constant_block gds 2022-10-08 12:13:09 -07:00
mo-hosni dde6e034e0 added constant_block view 2022-10-08 12:05:53 -07:00
Tim Edwards fd29bb3442 Generated new chip_io_alt layout to match the chip_io changes in 
the previous commit.  Fixed a few minor errors in the chip_io
layout.  Waiting on layout of constant_block to finish.
 2022-10-08 14:05:46 -04:00
RTimothyEdwards c0d6011ee8 Apply automatic changes to Manifest and README.rst 2022-10-08 16:07:53 +00:00
Tim Edwards d1a3922dbb Initial commit for rework of chip_io and chip_io_alt layouts; 
includes RTL change inside the padframe definition to remove one
previously unnoticed hard-wired connection between VDDIO and a
3.3V domain digital input pin.
 2022-10-08 12:05:10 -04:00
M0stafaRady 7b2994e70e Apply automatic changes to Manifest and README.rst 2022-10-08 13:26:20 +00:00
M0stafaRady e94a8e0477 add test la test 2022-10-08 06:25:26 -07:00
M0stafaRady d90001eac2 update caravel.py to disable bin 3 also 2022-10-08 01:56:41 -07:00
mo-hosni b88648bbae compress gds 2022-10-07 17:03:21 -07:00
mo-hosni d6ca7f9091 rehardened housekeeping after rtl update, and fixed all hold and transition violations. 2022-10-07 16:59:01 -07:00
Mohamed Hosni 5c38e38767
Merge branch 'efabless:caravel_redesign' into caravel_redesign 2022-10-07 16:52:16 -07:00
R. Timothy Edwards 7b271a7808
Effectively reverted the change to add spare logic blocks near each (#157) 
* Effectively reverted the change to add spare logic blocks near each
of the GPIO control blocks by changing the definition of
NUM_SPARE_BLOCKS to 4 (the original number of spare logic blocks)
for both caravel and caravan top level RTL verilog modules.

* Apply automatic changes to Manifest and README.rst

Co-authored-by: RTimothyEdwards <RTimothyEdwards@users.noreply.github.com>
 2022-10-07 09:28:13 -07:00