and open source logos. Modified the gpio_defaults_block layout
so that open holes are not created in the metal1 when the vias
are moved by the defaults block configuration script.
which is now done through setting an environment variable to point to the
location of the management SoC wrapper. Added the missing user project
wrappers to the GL directory (copied from the original caravel repository),
and also the GL version of chip_io_alt. Modified the caravan_netlists and
caravel_netlists files to import the correct list of gate level netlists,
which has been reduced by moving "include" statements for components of the
management SoC into the management SoC repository (e.g., caravel_pico).
the change in the implementation of the serial loader, which split the load
signal out as a separate bit, and therefore had a separate bit-bang entry).
the clocking subcircuit from inside the pad area near the "clock"
pin to under the DLL. This prevents the DLL from having its
outputs travel all the way across the chip to reach the clocking
cell and then have the multiplexed clock travel all the way back,
especially as the DLL outputs are high-speed signals (up to 150
MHz).
verilog gate-level netlists to match the correct GPIO default
value assignments, and modify the top level gate-level caravel.v
and caravan.v netlists to match.
characters in the user_id_textblock layout, which was backwards,
and (2) add a path reference to "hexdigits" for each new character
layout encountered in the file, so that the text block layouts
are found even if "addpath hexdigits" has not been specified.
There were some other corrections to handling gzipped files that
probably does not apply in practice, where "make uncompress" has
been run prior to the set_user_id.py script.
update. Also changed the defaults block types in the layout so that
they match the gate-level netlist. This does not change the behavior
after assembly but lets LVS run correctly on the layout prior to final
assembly.
to housekeeping and the management core wrapper to separate the
wb_cyc_i signal and connect to new signal hk_cyc_o on the
management core. Also: Fixed a dangling input (user_clock) on
the housekeeping (minor error caused by the earlier refactoring
and unnoticed because there is no testbench covering that
function).
blocks; that is, there are special versions of the block for the
first 6 GPIO pins. That should allow the GL netlists to simulate,
although the end goal is to have the gen_gpio_defaults.py script
modify the GL netlists to exactly match the configuration, as is
done for the .mag layouts.
add a separate signal for the houskeeping wb_cyc_i wishbone signal,
instead of combining it with the user project's wb_cyc_i. This
change makes it compatible with the LiteX implementation of the
wishbone bus.
view pointing to the contents of ../gds/ so that when the assembled
chip's GDS is generated with "cif *hier write disable", the POR
will continue to have the GDS with the proper hierarchical processing.
Tim Edwards
manarabdelaty
jeffdi