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31 Commits

Author SHA1 Message Date
David Lindley c0e5821b14
New TRM document 
New Technical Reference Manual (TRM) documenting the  Caravel SoC Register and Memory maps.
 2024-04-15 08:35:27 -07:00
Jeff DiCorpo 2098608638
add Caravel datasheet 2024-01-08 22:50:41 -08:00
Marwan Abbas 5c05a01d63
Update requirements.txt 2023-11-12 15:03:35 +02:00
Marwan Abbas 8ff630aacf
Update ECO.rst 2022-11-11 19:34:12 +02:00
Marwan Abbas 05ce343e9d Added documentation for ECOs done on caravel 2022-10-28 16:45:12 +02:00
R. Timothy Edwards 39ac197284
Corrected the illustration of die pads; this corrects caravel (#132) 
github issue #104 from Mitch Bailey, but also adds missing
management functions that are defined in the housekeeping block
for specific pins, and renames the JTAG pin to Debug (as JTAG
has never been implemented).

Co-authored-by: Jeff DiCorpo <42048757+jeffdi@users.noreply.github.com>
 2022-10-20 14:43:42 -07:00
PriyankaDilip ec9fe7939f
Error in User Area Base Address (#97) 2022-09-29 07:14:41 -07:00
R. Timothy Edwards c363d52ccc
Corrected the documented solder bump dimension in the diagram (#133) 
die_pads.svg from 250um to 350um diameter.
 2022-09-29 07:10:53 -07:00
matt venn 44a83f90eb
add links to litex core (#96) 
and make it clear docs are split into 2
 2022-05-08 22:52:47 -07:00
Anton Blanchard f2cf19d6f2
Fix GPIO digital mode 010 description (#21) 
From looking at the firmware defines, it looks like 010 should be
pull-down, not pull-up.
 2022-04-07 07:46:20 -07:00
R. Timothy Edwards a61fc8b15d
Update maximum-ratings.rst 
Added min/max ratings for GPIO voltage and frequency
 2022-03-08 08:38:11 -05:00
Jeff DiCorpo e2f00e2770
Merge pull request #14 from Manarabdelaty/doc 
Documentation Updates
 2022-01-18 23:13:26 -08:00
manarabdelaty c96a65d023 Update doc 2022-01-14 10:33:15 -05:00
manarabdelaty 7083c96e34 Add documentation 2022-01-14 10:05:34 -05:00
Marwan Abbas b6e15baec9 added rst dir and converted all docs/other/*.txt to .rst 2021-12-27 19:17:32 +02:00
Marwan Abbas 6648513a0e
Update clamp_list.rst 2021-12-27 19:09:18 +02:00
Marwan Abbas ccce8a0f21
Create power_control.rst 2021-12-27 17:29:46 +02:00
Marwan Abbas 9470db9021
Create management_protect.rst 2021-12-27 17:23:17 +02:00
Marwan Abbas 0b17ee1d77
Create gpio.rst 2021-12-27 17:10:59 +02:00
Marwan Abbas bd2b1becc5
Create caravel_vs_caravan.rst 2021-12-26 18:20:04 +02:00
Marwan Abbas a50de44989
Merge branch 'efabless:main' into main 2021-12-26 17:23:12 +02:00
Tim Edwards 28931e7968 Added more documentation, fully documenting the GPIO, and various 
aspects of the memory mapped controls for the management protection,
and the various differences between the Caravel and Caravan chips.
 2021-12-23 11:54:36 -05:00
Marwan Abbas 0792dc6930
Create memory_map.rst 2021-12-23 14:41:53 +02:00
Marwan Abbas 56110e66e8
Create gpio_configuration.rst 2021-12-23 14:12:48 +02:00
Marwan Abbas 027dfe8d23
Create clamp_list.rst 2021-12-23 13:53:12 +02:00
Marwan Abbas 070e178c31
Update digital_locked_loop.rst 2021-12-23 13:38:01 +02:00
Marwan Abbas 7d3a8de7b9
Create digital_locked_loop.rst 2021-12-23 12:25:41 +02:00
Tim Edwards 31e3d9c106 Started a set of text documents to describe all of the register sets 
and describe the various functions of Caravel (especially housekeeping).
This should eventually be formatted to match the rest of the
documentation.
 2021-12-21 20:00:29 -05:00
jeffdi 1c9ca7e693 correct path for image in docs 2021-12-19 09:47:30 -08:00
jeffdi ee7eded766 add documentation 2021-12-17 11:55:08 -08:00
jeffdi e5cf492e0a add documentation 2021-12-16 17:51:16 -08:00