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599 Commits 16 Branches 1 Tag 1.8 GiB
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75 Commits

Author SHA1 Message Date
Tarachand Pagarani 3f5409eee2 add 4 global clocks 2021-01-14 02:28:07 -08:00
Lalit Sharma 51f11ee630 Replacing deprecated tile_port syntax 2021-01-12 21:33:53 -08:00
Tarachand Pagarani f04e72b5b3 create a copy of cout to connect to regular routing 2020-12-30 06:02:51 -08:00
Tarachand Pagarani 473e1d68a6 fix the carry in dangling 2020-12-29 19:04:56 -08:00
Tarachand Pagarani 61facff870 fix the carry in dangling and carry out accessible to regular routing 2020-12-29 18:54:48 -08:00
Tarachand Pagarani cbe50535ca further changes in architecture to make io interfaces routable 2020-12-28 08:35:17 -08:00
Tarachand Pagarani 474ed9b2ff Merge remote-tracking branch 'origin/master' into ql_ap3_arch_eval 2020-12-26 23:57:23 -08:00
Tarachand Pagarani 353207693a 1. added 32x32 fabric key\n 2. disable shift register packing due to routability failure\n 3. Disable IIR design due to routabiity failure in shift register mode\n 4. revert changes to QLSOFA architecture 2020-12-26 23:29:13 -08:00
Tarachand Pagarani 1aa0ef68e4 incoporated changes based on feedback from xifan 2020-12-24 23:05:47 -08:00
tangxifan 6a6b89e7b8 [Arch] Critical patch on dangling nets in logic elements 2020-12-21 22:23:41 -07:00
Tarachand Pagarani 01fabc65cc added a new architecture with LUT4, Soft adder and cross local routing with 24 clb inputs and feedback 2020-12-21 07:13:38 -08:00
Lalit Sharma c84c04c4b8 Increasing IO capacity to 32 2020-12-17 03:04:50 -08:00
Tarachand Pagarani 8502502b43 add 32x32 layout 2020-12-17 01:28:35 -08:00
tangxifan e7fd8e7d92 [Arch] Fine-tune architecture file to be consistent in port naming as post-PnR netlist 2020-12-09 12:12:40 -07:00
tangxifan 6039ae92ca [Arch] Bug fix for buffering two-level routing multiplexers using custom cells 2020-12-05 19:37:34 -07:00
tangxifan 06731e092e [Arch] Patch reset port name to be consistent with post-PnR netlist 2020-12-02 13:46:40 -07:00
Laboratory for Nano Integrated Systems (LNIS) 07d1962051
Merge pull request #51 from lnis-uofu/xt_dev 
Add new architecture files which use custom cells based on Skywater HD library
 2020-12-01 22:16:49 -07:00
tangxifan b5abfdd994 [Arch] enable local encoders 2020-12-01 20:56:53 -07:00
tangxifan 3b6f3b0691 [Arch] Bug fix in new arch 2020-12-01 20:49:02 -07:00
tangxifan 454ea09dc4 [Arch] Add architecture using custom cells 2020-12-01 20:19:22 -07:00
Laboratory for Nano Integrated Systems (LNIS) f4397e1656
Merge pull request #47 from LNIS-Projects/xt_dev 
Bug fix in the arch port naming
 2020-11-30 18:23:38 -07:00
tangxifan be9399a016 [Arch] Bug fix in the arch port naming: prog_reset is a reserved word in OpenFPGA 2020-11-30 17:58:56 -07:00
Tarachand Pagarani 9f7fb8a34d modify carry chain to change output mux 2020-11-30 07:08:09 -08:00
tangxifan c7ea3f3936 [Arch] Bug fix in the arch with reset and soft adder 2020-11-27 19:54:31 -07:00
tangxifan 14c21378b8 [Arch] Add new architecture using reset and softadder 2020-11-27 18:12:06 -07:00
tangxifan efab96d2dd [Arch] Bug fix in softadder architecture 2020-11-27 16:36:31 -07:00
tangxifan 295df663bb [Arch] Add arch variant with soft adders 2020-11-27 15:57:05 -07:00
tangxifan f27424c803 [Arch] Bug fix in the architecture using reset 2020-11-27 15:04:19 -07:00
tangxifan c424c3d9a6 [Arch] Add a new variant with reset signals to FFs 2020-11-27 14:41:53 -07:00
tangxifan 864ed26c9a [Arch] Merge latest arch from QuickLogic team on AP3 device using VPR routing architecture 2020-11-27 10:11:40 -07:00
tangxifan 0fa3604b6c [Arch] Update arch to enable more routability in shift register mode 2020-11-25 17:04:08 -07:00
tangxifan 6aefa8077e [Arch] Critical patch on LE architecture which enables correct shift register connections 2020-11-25 16:40:54 -07:00
tangxifan a92b9ce482 [Arch] Test Quicklogic test architecture 2020-11-25 15:58:50 -07:00
tangxifan 3ae41e2207 [Arch] Double checked I/O default direction set up in OpenFPGA architecture. Add comments for this point 2020-11-18 11:56:22 -07:00
tangxifan 1bfc793600 [Arch] Bug fix due to the use of embedded I/O cell 2020-11-17 19:55:04 -07:00
tangxifan 6a27eca809 [Arch] Update arch to use digital I/O circuitry 2020-11-17 19:34:58 -07:00
tangxifan 55db5d5aaf [Arch] Revert to the classical pin location in vpr arch 2020-11-17 15:09:31 -07:00
tangxifan 22d0aaafeb [Arch] Move global pins to the first of pin list in vpr architecture to ease backend scripts 2020-11-17 11:47:47 -07:00
tangxifan 290b1f47a0 [Arch] Change I/O density to interface wishbone 2020-11-13 17:44:53 -07:00
tangxifan be33082faf [Arch] Remove out-of-data architectures 2020-11-13 09:50:45 -07:00
tangxifan bbf871d22a [Arch] Limit shift register chain only to columns of clbs 2020-11-13 09:39:59 -07:00
tangxifan 5d3b08ada4 [Arch] Rename ports to be consistent with backend scripts and remove shift-register chain across fabric 2020-11-13 09:24:57 -07:00
tangxifan 6a4b3e7219 [Doc] Update README about fabric key and apply minor format 2020-11-13 09:20:30 -07:00
tangxifan 7dafb7e3b2 [Arch] Use global clock from tile port in caravel architecture 2020-11-11 19:43:24 -07:00
tangxifan 3792400da8 [Arch] Add fabric key for 12x12 fabric 2020-11-11 15:57:10 -07:00
tangxifan 16af5e6ad8 [Arch] Minor change to keep a regular arch in fle->lut connection 2020-11-09 15:52:46 -07:00
tangxifan 630c4060a8 [Arch] Detect some bugs (will not cause verification failed) in vpr arch 2020-11-09 15:12:00 -07:00
tangxifan 11ee81f8c4 [Arch] Bug fix in the caravel arch 2020-11-08 14:25:38 -07:00
tangxifan 795b958239 [Arch] Add fabric key for 2x2 fabric 2020-11-08 11:35:59 -07:00
tangxifan 8d84d83eab [Arch] Use single-output DFF to further compress area 2020-11-06 11:47:31 -07:00