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502 Commits 16 Branches 1 Tag 1.8 GiB
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502 Commits

Author SHA1 Message Date
tangxifan 0e2ee8a0cc [Script] Add benchmarks to OpenFPGA task run 2020-11-17 14:01:48 -07:00
tangxifan 75db7b255b [Benchmark] Add micro benchmarks 2020-11-17 13:55:47 -07:00
tangxifan 39aa11c42c [Script] Update OpenFPGA task run configuration for pre-pnr files 2020-11-17 13:46:25 -07:00
tangxifan 804d96bf50 [Testbench] Rename post-pnr testbenches to dedicated directories 2020-11-17 13:45:55 -07:00
tangxifan efda8e0f73 [Script] Update task run configuration in output directory 2020-11-17 13:21:26 -07:00
Laboratory for Nano Integrated Systems (LNIS) ffc072f36e
Merge pull request #22 from LNIS-Projects/xt_dev 
Misc Updates: Architecture, Post-PnR Testbench and Documentation
 2020-11-17 13:13:26 -07:00
tangxifan 0d62af2980 [Doc] Add missing files about clb architecture 2020-11-17 12:04:38 -07:00
tangxifan 22d0aaafeb [Arch] Move global pins to the first of pin list in vpr architecture to ease backend scripts 2020-11-17 11:47:47 -07:00
tangxifan 52076b8714 [Doc] Add detailed architecture schematic 2020-11-17 11:44:57 -07:00
tangxifan a1bb7a3ddc [Testbench] Update testbench for post-pnr 2020-11-17 11:42:35 -07:00
tangxifan 679cb3fea2 [Doc] Minor fix on broken link 2020-11-13 18:47:51 -07:00
Laboratory for Nano Integrated Systems (LNIS) 9932484944
Merge pull request #21 from LNIS-Projects/xt_dev 
Remove Obsolete Architectures and Update Documentation
 2020-11-13 18:45:06 -07:00
tangxifan a2353355ec [Doc] Update figures for I/O resources 2020-11-13 18:36:11 -07:00
tangxifan 625ad5e9c6 [HDL] Alpha version of behavioral-level Verilog for SoC wrapper 2020-11-13 18:34:40 -07:00
tangxifan 46171472a7 [Script] Rename output directory for netlsit generation 2020-11-13 17:47:38 -07:00
tangxifan 290b1f47a0 [Arch] Change I/O density to interface wishbone 2020-11-13 17:44:53 -07:00
tangxifan 8bae6bb893 [Doc] Update documentation about I/O resources 2020-11-13 17:24:43 -07:00
tangxifan 80655c5869 [HDL] Digital I/O of embedded FPGA is now lib independent 2020-11-13 10:00:30 -07:00
tangxifan be33082faf [Arch] Remove out-of-data architectures 2020-11-13 09:50:45 -07:00
tangxifan 6344bb420d [Script] Remove out-of-data task run 2020-11-13 09:47:32 -07:00
tangxifan bbf871d22a [Arch] Limit shift register chain only to columns of clbs 2020-11-13 09:39:59 -07:00
tangxifan 5d3b08ada4 [Arch] Rename ports to be consistent with backend scripts and remove shift-register chain across fabric 2020-11-13 09:24:57 -07:00
tangxifan 47dad08db5 [Doc] Fix typo in frontpage readme 2020-11-13 09:21:22 -07:00
tangxifan 6a4b3e7219 [Doc] Update README about fabric key and apply minor format 2020-11-13 09:20:30 -07:00
Laboratory for Nano Integrated Systems (LNIS) cddec1441c
Merge pull request #20 from LNIS-Projects/xt_dev 
[Doc] Add missing figures
 2020-11-12 22:08:28 -07:00
tangxifan a018bd077a [Doc] Add missing figures 2020-11-12 22:05:44 -07:00
Laboratory for Nano Integrated Systems (LNIS) 368af5a182
Merge pull request #19 from LNIS-Projects/xt_dev 
Add Online Documentation about Chip Designs
 2020-11-12 22:03:50 -07:00
tangxifan 67763c3464 [Doc] Update to latest architecture definition and device information 2020-11-12 21:59:14 -07:00
tangxifan 3108ba6283 [Doc] Update contact information 2020-11-12 19:51:23 -07:00
tangxifan ca045745aa [Doc] Update doc title 2020-11-12 19:49:57 -07:00
tangxifan eeb96fd277 [Doc] Add sphinx package to support doc writing 2020-11-12 19:47:50 -07:00
tangxifan 81ca234977 [Doc] Bug fix in readthedoc setting 2020-11-12 19:41:00 -07:00
tangxifan 407d91660a [Doc] rename readthedoc setting file 2020-11-12 19:34:04 -07:00
tangxifan 4184567326 [Doc] Update readthedoc setting file 2020-11-12 19:23:02 -07:00
tangxifan c3fbe146f8 [Doc] Add default settings for readthedoc 2020-11-12 19:21:53 -07:00
tangxifan bb531bc8ba [Git] Add ignore files to doc compiled results 2020-11-12 19:13:20 -07:00
tangxifan 4897437c0d [Doc] Add online documentation 2020-11-12 19:07:10 -07:00
tangxifan 5f02463098 [HDL] Update wrapper for caravel SoC interface 2020-11-12 19:06:49 -07:00
tangxifan 7dafb7e3b2 [Arch] Use global clock from tile port in caravel architecture 2020-11-11 19:43:24 -07:00
tangxifan 35a64a195c [Testbench] Add post PnR testbench for 12x12 fabric 2020-11-11 17:16:21 -07:00
tangxifan 3792400da8 [Arch] Add fabric key for 12x12 fabric 2020-11-11 15:57:10 -07:00
tangxifan d3ae847f43 [Script] Add openfpga task for 12x12 fabric fit caravel SoC 2020-11-11 15:20:01 -07:00
tangxifan c0d3e7c91f
Merge pull request #18 from LNIS-Projects/ganesh_dev 
Updated 12x12 design, skipped updating module GDSs
 2020-11-11 14:15:42 -07:00
Ganesh Gore 82767cd1b2 Updated 12x12 design skipped module GDSs 2020-11-10 15:37:00 -07:00
Laboratory for Nano Integrated Systems (LNIS) 2407cb1fba
Merge pull request #17 from LNIS-Projects/xt_dev 
[Testbench] Fix bugs for the testbenches for the post-PnR netlists
 2020-11-09 19:46:56 -07:00
tangxifan e5e38dff80 [Testbench] Fix bugs for the testbenches for the post-PnR netlists 2020-11-09 19:38:37 -07:00
tangxifan e6768ba171
Merge pull request #16 from LNIS-Projects/ganesh_dev 
Change configuration flipflop + Fixed configuration chain
 2020-11-09 19:33:21 -07:00
Ganesh Gore 7dd7e33cb6 Change configuration flipflop + Fixed configuration chain 2020-11-09 19:17:15 -07:00
tangxifan ab85bafa11
Merge pull request #15 from LNIS-Projects/xt_dev 
Bug fixes for post-pnr netlists and arch
 2020-11-09 15:55:08 -07:00
tangxifan 16af5e6ad8 [Arch] Minor change to keep a regular arch in fle->lut connection 2020-11-09 15:52:46 -07:00