[Doc] Add online documentation

DOC/Makefile

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+# Minimal makefile for Sphinx documentation
+#
+
+# You can set these variables from the command line.
+SPHINXOPTS    =
+SPHINXBUILD   = sphinx-build
+SOURCEDIR     = source
+BUILDDIR      = build
+
+PAPER =
+PAPEROPT_a4 = -D latex_paper_size=a4
+PAPEROPT_letter = -D latex_paper_size=letter
+ALL_SPHINXOPTS = -d $(BUILDDIR)/doctrees $(PAPEROPT_$(PAPER)) $(SPHINXOPTS) $(SOURCEDIR)
+
+# Put it first so that "make" without argument is like "make help".
+help:
+	@$(SPHINXBUILD) -M help "$(SOURCEDIR)" "$(BUILDDIR)" $(SPHINXOPTS) $(O)
+
+livehtml:
+	sphinx-autobuild -b html $(ALL_SPHINXOPTS) $(BUILDDIR)/html
+
+clean:
+	rm -rf $(BUILDDIR)/*
+
+.PHONY: help clean Makefile
+
+# Catch-all target: route all unknown targets to Sphinx using the new
+# "make mode" option.  $(O) is meant as a shortcut for $(SPHINXOPTS).
+%: Makefile
+	@$(SPHINXBUILD) -M $@ "$(SOURCEDIR)" "$(BUILDDIR)" $(SPHINXOPTS) $(O)
+#html:
+#	$(SPHINXBUILD) -b html $@ "$(SOURCEDIR)" "$(BUILDDIR)/html" $(SPHINXOPTS)
+

DOC/make.bat

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+@ECHO OFF
+
+pushd %~dp0
+
+REM Command file for Sphinx documentation
+
+if "%SPHINXBUILD%" == "" (
+	set SPHINXBUILD=sphinx-build
+)
+set SOURCEDIR=source
+set BUILDDIR=build
+
+if "%1" == "" goto help
+
+%SPHINXBUILD% >NUL 2>NUL
+if errorlevel 9009 (
+	echo.
+	echo.The 'sphinx-build' command was not found. Make sure you have Sphinx
+	echo.installed, then set the SPHINXBUILD environment variable to point
+	echo.to the full path of the 'sphinx-build' executable. Alternatively you
+	echo.may add the Sphinx directory to PATH.
+	echo.
+	echo.If you don't have Sphinx installed, grab it from
+	echo.http://sphinx-doc.org/
+	exit /b 1
+)
+
+%SPHINXBUILD% -M %1 %SOURCEDIR% %BUILDDIR% %SPHINXOPTS%
+goto end
+
+:help
+%SPHINXBUILD% -M help %SOURCEDIR% %BUILDDIR% %SPHINXOPTS%
+
+:end
+popd

DOC/requirements.txt

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+#Python requirements file for building documentation
+# used by Read The Docs to install python required 
+# modules with pip.
+
+# Support Markdown
+#recommonmark
+
+#Handle references in bibtex format
+sphinxcontrib-bibtex
+
+#Work-around bug "AttributeError: 'Values' object has no attribute 'character_level_inline_markup'" with docutils 0.13.1
+#See:
+#  * https://github.com/sphinx-doc/sphinx/issues/3951
+#  * https://sourceforge.net/p/docutils/bugs/304/
+#docutils>=0.14

DOC/source/acknowledgment.rst

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+Acknowledgment
+--------------
+
+.. figure:: ./figures/uofu_logo.png
+      :scale: 50%
+
+.. figure:: ./figures/lnis_logo.png
+      :scale: 50%
+
+Supported by DARPA PoSH program
+
+.. figure:: ./figures/darpa_logo.png
+      :scale: 50%

DOC/source/arch/clb.rst

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+Configurable Logic Block User Guide
+-----------------------------------
+
+FROG's Configurable Logic Block (CLB) consists of 10 logic elements as shown in :numref:`fig_le_arch` and a 50% depopulated crossbar which tightly interconnects the logic elements.
+
+.. _fig_le_arch:
+
+.. figure:: ./figures/le_arch.png
+  :scale: 100%
+  :alt: Logic element schematic
+
+  Logic Element
+
+.. _fig_clb_arch:
+
+.. figure:: ./figures/clb_arch.png
+  :scale: 60%
+  :alt: Configurable Logic Block schematic
+
+  Configurable logic block and its chain connections across FPGA
+
+

DOC/source/arch/index.rst

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+.. _arch:
+   Architecture 
+ 
+.. toctree::
+   :maxdepth: 2
+
+   clb

DOC/source/conf.py

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+# -*- coding: utf-8 -*-
+#
+# Configuration file for the Sphinx documentation builder.
+#
+# This file does only contain a selection of the most common options. For a
+# full list see the documentation:
+# http://www.sphinx-doc.org/en/master/config
+
+# -- Path setup --------------------------------------------------------------
+
+# If extensions (or modules to document with autodoc) are in another directory,
+# add these directories to sys.path here. If the directory is relative to the
+# documentation root, use os.path.abspath to make it absolute, like shown here.
+#
+import sys
+import os
+import shlex
+# sys.path.insert(0, os.path.abspath('.'))
+
+import sphinx_rtd_theme
+
+# Uncomment for local build
+#html_theme = "sphinx_rtd_theme"
+#html_theme_path = [sphinx_rtd_theme.get_html_theme_path()]
+
+# Import sphinxcontrib.bibtex
+have_sphinxcontrib_bibtex = True
+try:
+    import sphinxcontrib.bibtex
+except ImportError:
+    have_sphinxcontrib_bibtex = False
+
+# -- Project information -----------------------------------------------------
+
+project = u'OpenFPGA'
+copyright = u'2018, Xifan Tang'
+author = u'Xifan Tang'
+
+# The short X.Y version
+version = u''
+# The full version, including alpha/beta/rc tags
+release = u'1.0'
+
+
+# -- General configuration ---------------------------------------------------
+
+# If your documentation needs a minimal Sphinx version, state it here.
+#
+# needs_sphinx = '1.0'
+
+# Add any Sphinx extension module names here, as strings. They can be
+# extensions coming with Sphinx (named 'sphinx.ext.*') or your custom
+# ones.
+extensions = [
+    'sphinx.ext.todo',
+    'sphinx.ext.mathjax',
+    'sphinx.ext.graphviz',
+    'sphinxcontrib.bibtex',
+    'sphinx.ext.autosectionlabel',
+]
+
+# Add any paths that contain templates here, relative to this directory.
+#templates_path = ['ytemplates']
+templates_path = [sphinx_rtd_theme.get_html_theme_path()]
+
+# The suffix(es) of source filenames.
+# You can specify multiple suffix as a list of string:
+#
+# source_suffix = ['.rst', '.md']
+source_suffix = '.rst'
+
+# The master toctree document.
+master_doc = 'index'
+
+# The language for content autogenerated by Sphinx. Refer to documentation
+# for a list of supported languages.
+#
+# This is also used if you do content translation via gettext catalogs.
+# Usually you set "language" from the command line for these cases.
+language = None
+
+# List of patterns, relative to source directory, that match files and
+# directories to ignore when looking for source files.
+# This pattern also affects html_static_path and html_extra_path.
+exclude_patterns = []
+
+# The name of the Pygments (syntax highlighting) style to use.
+pygments_style = 'sphinx'
+
+# If true, `todo` and `todoList` produce output, else they produce nothing.
+todo_include_todos = True
+
+# Number figures for referencing
+numfig = True
+
+
+# -- Options for HTML output -------------------------------------------------
+
+# The theme to use for HTML and HTML Help pages.  See the documentation for
+# a list of builtin themes.
+#
+#html_theme = 'alabaster'
+html_theme = 'sphinx_rtd_theme'
+
+# Theme options are theme-specific and customize the look and feel of a theme
+# further.  For a list of options available for each theme, see the
+# documentation.
+#
+# Comment when using local build
+# Uncomment when using readthedocs build
+#html_theme_options = {sphinx_rtd_theme}
+
+# Add any paths that contain custom static files (such as style sheets) here,
+# relative to this directory. They are copied after the builtin static files,
+# so a file named "default.css" will overwrite the builtin "default.css".
+#html_static_path = ['ystatic']
+
+# Custom sidebar templates, must be a dictionary that maps document names
+# to template names.
+#
+# The default sidebars (for documents that don't match any pattern) are
+# defined by theme itself.  Builtin themes are using these templates by
+# default: ``['localtoc.html', 'relations.html', 'sourcelink.html',
+# 'searchbox.html']``.
+#
+# html_sidebars = {}
+
+
+# -- Options for HTMLHelp output ---------------------------------------------
+
+# Output file base name for HTML help builder.
+htmlhelp_basename = 'OpenFPGAdoc'
+
+
+# -- Options for LaTeX output ------------------------------------------------
+
+latex_elements = {
+    # The paper size ('letterpaper' or 'a4paper').
+    #
+    # 'papersize': 'letterpaper',
+
+    # The font size ('10pt', '11pt' or '12pt').
+    #
+    # 'pointsize': '10pt',
+
+    # Additional stuff for the LaTeX preamble.
+    #
+    # 'preamble': '',
+
+    # Latex figure (float) alignment
+    #
+    # 'figure_align': 'htbp',
+}
+
+# Grouping the document tree into LaTeX files. List of tuples
+# (source start file, target name, title,
+#  author, documentclass [howto, manual, or own class]).
+latex_documents = [
+    (master_doc, 'OpenFPGA.tex', u'OpenFPGA Documentation',
+     u'Xifan Tang', 'manual'),
+]
+
+
+# -- Options for manual page output ------------------------------------------
+
+# One entry per manual page. List of tuples
+# (source start file, name, description, authors, manual section).
+man_pages = [
+    (master_doc, 'openfpga', u'OpenFPGA Documentation',
+     [author], 1)
+]
+
+
+# -- Options for Texinfo output ----------------------------------------------
+
+# Grouping the document tree into Texinfo files. List of tuples
+# (source start file, target name, title, author,
+#  dir menu entry, description, category)
+texinfo_documents = [
+    (master_doc, 'OpenFPGA', u'OpenFPGA Documentation',
+     author, 'OpenFPGA', 'One line description of project.',
+     'Miscellaneous'),
+]
+
+
+# -- Options for Epub output -------------------------------------------------
+
+# Bibliographic Dublin Core info.
+epub_title = project
+
+# The unique identifier of the text. This can be a ISBN number
+# or the project homepage.
+#
+# epub_identifier = ''
+
+# A unique identification for the text.
+#
+# epub_uid = ''
+
+# A list of files that should not be packed into the epub file.
+epub_exclude_files = ['search.html']

DOC/source/contact.rst

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+.. _contact:
+
+Contacts
+~~~~~~~~
+
+General Questions
+
+Prof. Pierre-Emmanuel Gaillardon 
+
+pierre-emmanuel.gaillardon@utah.edu
+
+Technical Questions about OpenFPGA
+
+Dr. Xifan Tang
+
+xifan.tang@utah.edu
+
+Technical Questions about Backend
+
+Ganesh Gore
+
+ganesh.gore@utah.edu
+
+Edouard Giacomin
+
+edouard.giacomin@utah.edu
+
+Technical Questions about Verification and Signoff
+
+Aurelien Alacchi
+
+aurelien.alacchi@utah.edu

DOC/source/dc_ac_character.rst

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+DC and AC Characteristics
+-------------------------
+
+FROG contains 196 I/O pins, whose details are summarized in the following tables.
+
+I/O usage and port information
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+
+.. table:: I/O usage and sizes
+
+  +-----------+------------------------------------------------------------------------+-------------+
+  | I/O Type  | Description                                                            | No. of Pins |
+  +===========+========================================================================+=============+
+  | Data I/O  | Datapath I/Os of FPGA fabric                                           | 80          |
+  +-----------+------------------------------------------------------------------------+-------------+
+  | VDD_core  | VDD supply for FPGA core                                               | 28          |
+  +-----------+------------------------------------------------------------------------+-------------+
+  | VSS_core  | VSS supply for FPGA core                                               | 28          |
+  +-----------+------------------------------------------------------------------------+-------------+
+  | VDD_io    | VDD supply for FPGA I/Os                                               | 16          |
+  +-----------+------------------------------------------------------------------------+-------------+
+  | VSS_io    | VSS supply for FPGA I/Os                                               | 16          |
+  +-----------+------------------------------------------------------------------------+-------------+
+  | Clk       | Operating clock of FPGA core                                           | 1           |
+  +-----------+------------------------------------------------------------------------+-------------+
+  | Reset     | Reset flip-flop contents to logic '0'                                  | 1           |
+  +-----------+------------------------------------------------------------------------+-------------+
+  | ProgClk   | Clock used by configuration protocol to program FPGA fabric            | 1           |
+  +-----------+------------------------------------------------------------------------+-------------+
+  | ProgReset | Reset configurable memories to logic '0'                               | 1           |
+  +-----------+------------------------------------------------------------------------+-------------+
+  | CCin      | Input of configuation protocol to load bitstream                       | 1           |
+  +-----------+------------------------------------------------------------------------+-------------+
+  | CCout     | Output of configuration protocol to read back bitstream                | 1           |
+  +-----------+------------------------------------------------------------------------+-------------+
+  | TestEn    | Activate the test mode of FPGA fabric                                  | 1           |
+  +-----------+------------------------------------------------------------------------+-------------+
+  | SCin      | Input of built-in scan-chain to load data to flip-flops of FPGA fabric | 1           |
+  +-----------+------------------------------------------------------------------------+-------------+
+  | SCout     | Output of built-in scan-chain to read back flip-flops from FPGA fabric | 1           |
+  +-----------+------------------------------------------------------------------------+-------------+
+  | Spypad    | Spypads for debugging. See details in spypad section                   | 14          |
+  +-----------+------------------------------------------------------------------------+-------------+
+  | Total     |                                                                        | 191         |
+  +-----------+------------------------------------------------------------------------+-------------+
+
+Recommended Operating Conditions
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+
+.. table:: Recommended Operating Conditions
+
+  +----------+------------------------------+------+------+-------+
+  | Symbol   | Description                  | Min  | Max  | Units |
+  +==========+==============================+======+======+=======+
+  | VDD_io   | Supply voltage for I/Os      | 1.26 | 2.34 | V     |
+  +----------+------------------------------+------+------+-------+
+  | VDD_core | Supply voltage for FPGA core | 0.56 | 1.04 | V     |
+  +----------+------------------------------+------+------+-------+
+  | V_in     | Input voltage for other I/Os | 0.56 | 1.04 | V     |
+  +----------+------------------------------+------+------+-------+
+  | I_in     | Maximum current through pins | N/A  | 4    | mA    |
+  +----------+------------------------------+------+------+-------+
+  | f_max    | Maximum frequency of I/Os    | N/A  | 70   | MHz   |
+  +----------+------------------------------+------+------+-------+
+  
+Typical AC Characteristics
+^^^^^^^^^^^^^^^^^^^^^^^^^^
+
+.. table:: Typical AC characteristics for FPGA I/Os
+
+  +-----------------+-------------------------------------------+------+------+-------+
+  | Symbol          | Description                               | Min  | Max  | Units |
+  +=================+===========================================+======+======+=======+
+  | V_in Overshoot  | Maximum allowed overshoot voltage for Vin | 2.34 | 2.34 | V     |
+  +-----------------+-------------------------------------------+------+------+-------+
+  | V_in Undershoot | Minimum allowed overshoot voltage for Vin | 1.26 | 1.26 | V     |
+  +-----------------+-------------------------------------------+------+------+-------+
+  | I_VDD_core      | Quiescent VDD_core supply current         | 5000 | 5000 | mA    |
+  +-----------------+-------------------------------------------+------+------+-------+
+  | I_VDD_io        | Quiescent VDD_io supply current           | TBD  | TBD  | mA    |
+  +-----------------+-------------------------------------------+------+------+-------+
+

DOC/source/index.rst

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+.. OpenFPGA documentation master file, created by
+   sphinx-quickstart on Thu Sep 13 12:15:14 2018.
+   You can adapt this file completely to your liking, but it should at least
+   contain the root `toctree` directive.
+
+Welcome to FROG's documentation!
+====================================
+
+.. toctree::
+   :caption: Device
+
+   technical_highlights
+
+   dc_ac_character
+
+.. toctree::
+   :maxdepth: 2
+   :caption: Architecture
+
+   arch/index
+
+.. toctree::
+   :maxdepth: 2
+   :caption: Appendix
+
+   contact
+
+   acknowledgment
+
+For more information on the OpenFPGA see openfpga_doc_ or openfpga_github_
+
+For more information on the original FPGA architecture description language see xml_vtr_
+
+Indices and tables
+==================
+
+* :ref:`genindex`
+* :ref:`modindex`
+* :ref:`search`
+
+.. _openfpga_doc: https://docs.verilogtorouting.org/en/latest/
+.. _openfpga_github: https://github.com/verilog-to-routing/vtr-verilog-to-routing
+.. _xml_vtr: https://docs.verilogtorouting.org/en/latest/arch/reference/

DOC/source/technical_highlights.rst

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+Highlights
+----------
+
+FROG is the FiRst Open-source fpGa, which is designed through a no-human-in-the-loop automate flow. Built on a state-of-the-art 14nm FinFET technology, FROG aims to empower embedded applications with its low-cost design approach but high-performance architecture.
+
+- Multi-mode 6-input Look-Up Table (LUT) technology, which operate as dual-output 5-input LUTs, as well as four-output 4-input LUTs.
+
+- Native support on up-to 600-bit shift registers as well as ripple-carry adders
+
+- 512Kb dual-port block RAM populated in 16 independent on-chip memory banks
+
+- Operating temperature ranging from -40 :math:`^\circ C` to 85 :math:`^\circ C`
+
+- Packaged by wire-bonded BGA
+
+
+.. table:: Logic capacity of FROG
+
+  +--------------------------+------------+
+  | Resource Type            | Capacity   |
+  +==========================+============+
+  | Look-Up Tables [1]_      |   9.92k    |
+  +--------------------------+------------+
+  | Arithmetic Units [2]_    |   19.84k   |
+  +--------------------------+------------+
+  | Flip-flops               |   19.84k   |
+  +--------------------------+------------+
+  | Block RAM [3]_           |   512kb    |
+  +--------------------------+------------+
+  | Max. Configuration Speed |     TBD    |
+  +--------------------------+------------+
+  | Max. Operating Speed     |   150MHz   |
+  +--------------------------+------------+
+  | User I/O Pins            |   124      |
+  +--------------------------+------------+
+  | Max. I/O Speed           |   70MHz    |
+  +--------------------------+------------+
+  | I/O Voltage              |   1.8V     |
+  +--------------------------+------------+
+  | Core Voltage             |   0.8V     |
+  +--------------------------+------------+
+
+.. [1] counted by 6-input fracturable LUTs
+
+.. [2] Counted by 1-bit full adders 
+
+.. [3] Include sixteen 32kb memory blocks
+
+