Merge pull request #22 from LNIS-Projects/xt_dev

Misc Updates: Architecture, Post-PnR Testbench and Documentation

ARCH/vpr_arch/k4_frac_N8_tileable_register_scan_chain_nonLR_caravel_io_skywater130nm.xml

@@ -144,10 +144,10 @@
       </fc>
       <!--pinlocations pattern="spread"/-->
       <pinlocations pattern="custom">
-        <loc side="left">clb.clk</loc>
-        <loc side="top">clb.reg_in clb.sc_in clb.O[7:0] clb.I0 clb.I0i clb.I1 clb.I1i clb.I2 clb.I2i clb.I3 clb.I3i</loc>
+        <loc side="left"></loc>
+        <loc side="top">clb.clk clb.reg_in clb.sc_in clb.reg_out clb.sc_out clb.O[7:0] clb.I0 clb.I0i clb.I1 clb.I1i clb.I2 clb.I2i clb.I3 clb.I3i</loc>
         <loc side="right">clb.O[15:8] clb.I4 clb.I4i clb.I5 clb.I5i clb.I6 clb.I6i clb.I7 clb.I7i</loc>
-        <loc side="bottom">clb.reg_out clb.sc_out</loc>
+        <loc side="bottom"></loc>
       </pinlocations>
     </tile>
   </tiles>

DOC/source/arch/clb.rst

@@ -1,24 +0,0 @@
-.. _clb:
-
-Configurable Logic Block
-------------------------
-
-Each Configurable Logic Block (CLB) consists of 8 logic elements as shown in :numref:`fig_fle_arch`.
-
-.. _fig_fle_arch:
-
-.. figure:: ./figures/fle_arch.png
-  :scale: 40%
-  :alt: Logic element schematic
-
-  Schematic of a logic element
-
-.. _fig_clb_arch:
-
-.. figure:: ./figures/clb_arch.png
-  :scale: 60%
-  :alt: Configurable Logic Block schematic
-
-  Configurable logic block and its chain connections across FPGA
-
-

DOC/source/arch/clb_arch.rst

@@ -0,0 +1,56 @@
+.. _clb_arch:
+
+Configurable Logic Block
+------------------------
+
+.. _clb_arch_generality:
+
+Generality
+~~~~~~~~~~
+
+Each Logic Block (CLB) consists of 8 Logic Elements (LEs) as shown in :numref:`fig_clb_arch`.
+All the pins of the LEs are directly wired to CLB pins without a local routing architecture.
+Feedback connections between LEs are implemented by the global routing architecture outside the CLBs.
+
+.. _fig_clb_arch:
+
+.. figure:: ./figures/clb_arch.png
+  :scale: 20%
+  :alt: Configurable Logic Block schematic
+
+  Configurable logic block schematic
+
+.. _clb_arch_le:
+
+Multi-mode Logic Element
+~~~~~~~~~~~~~~~~~~~~~~~~
+
+As shown in :numref:`fig_fle_arch`, each Logic Element (LE) consists of
+
+- a fracturable 4-input Look-Up Table (LUT)
+- two D-type Flip-Flops (FF)
+
+.. _fig_fle_arch:
+
+.. figure:: ./figures/fle_arch.png
+  :scale: 30%
+  :alt: Logic element schematic
+
+  Detailed schematic of a logic element
+
+The LE can operate in different modes to map logic function efficiently
+
+- 4-input LUT and single FF
+- Dual 3-input LUTs and 2 FFs
+- 2-bit shift registers
+
+.. _clb_arch_scan_chain:
+
+Scan Chain
+~~~~~~~~~~
+
+There is a built-in scan-chain in the CLB where all the `sc_in` and `sc_out` ports of LEs are connected in a chain, as illustrated in :numref:`fig_clb_arch`.
+When `Test_en` signal is active, users can readback the contents of all the D-type flip-flops of the LEs thanks to the scan-chain. 
+When `Test_en` signal is disabled, D-type flip-flops of the LEs operate in regular mode to propagate datapath signal from LUT outputs. 
+
+.. note:: The scan-chain of CLBs are connected in a chain at the top-level. See details in :ref:`fpga_arch_scan_chain`.

DOC/source/arch/fpga_arch.rst

@@ -0,0 +1,78 @@
+.. _fpga_arch:
+
+FPGA Overview
+-------------
+
+.. _fpga_arch_generality:
+
+Generality
+~~~~~~~~~~
+
+:numref:`fig_fpga_arch` shows an overview on the architecture of the embedded FPGA fabric.
+The FPGA follows a homogeneous architecture which only contains single type of tiles in the center fabric.
+I/O tiles are placed at the boundary of the FPGA to interface with GPIOs and RISC-V processors (see details in :ref:`io_resource`). 
+
+.. _fig_fpga_arch:
+
+.. figure:: ./figures/fpga_arch.png
+  :scale: 25%
+  :alt: Tile-based FPGA architecture
+
+  Tile-based FPGA architecture
+
+
+.. _fpga_arch_tiles:
+
+Tiles
+~~~~~
+
+The FPGA architecture follows a tile-based organization, to exploit the fine-grainularity in physical design, where three types of tiles are built:
+
+.. table:: FPGA tile type and functionalities
+
+  +------+----------+---------------------------------------------+
+  | Type | Capacity | Description                                 |
+  +======+==========+=============================================+
+  | CLB  | 144      | Each CLB tile consists of                   | 
+  |      |          | - a Configurable Logic Block (CLB)          |
+  |      |          | - a X-direction Connection Block (CBx)      | 
+  |      |          | - a Y-direction Connection Block (CBy)      |
+  |      |          | - a Switch Block (SB).                      |
+  |      |          | This is the majority tile across the fabric |
+  |      |          | to implement logics and registers.          | 
+  +------+----------+---------------------------------------------+
+  | IO-A | 36       | The type-A I/O is a low-density I/O tile    |
+  |      |          | which is designed to mainly interface the   |
+  |      |          | the GPIOs of the SoC.                       |
+  |      |          | Each I/O-A tile consists of 1 digitial I/O  |
+  |      |          | cell.                                       |
+  +------+----------+---------------------------------------------+
+  | IO-B | 12       | The type-B I/O is a high-density I/O tile   |
+  |      |          | which is designed to mainly interface the   |
+  |      |          | the wishbone interface and logic analyzer   |
+  |      |          | of the SoC.                                 |
+  |      |          | Each I/O-B tile consists of 9 digitial I/O  |
+  |      |          | cells.                                      |
+  +------+----------+---------------------------------------------+
+
+.. _fpga_arch_scan_chain:
+
+Scan-chain
+~~~~~~~~~~
+
+There is a built-in scan-chain in the FPGA which connects the the `sc_in` and `sc_out` ports of CLBs in a chain (see details in :ref:`clb_arch_scan_chain`), as illustrated in :numref:`fig_fabric_scan_chain`.
+
+When `Test_en` signal is active, users can 
+
+- overwrite the contents of all the D-type flip-flops in the FPGA by feeding signals to the `SC_HEAD` port
+- readback the contents of all the D-type flip-flops in the FPGA through the `SC_TAIL` port. 
+
+.. _fig_fabric_scan_chain:
+
+.. figure:: ./figures/fabric_scan_chain.png
+  :scale: 25%
+  :alt: Built-in scan-chain across FPGA
+
+  Built-in scan-chain across FPGA
+
+

DOC/source/arch/index.rst

@@ -6,4 +6,6 @@
 
    io_resource
 
-   clb
+   fpga_arch
+
+   clb_arch

DOC/source/arch/io_resource.rst

@@ -14,7 +14,7 @@ Among the 144 I/Os,
 
 - **30 external I/Os** are accessible through the Caravel SoC's *General-Purpose I/Os* (GPIOs).
 
-- **114 internal I/Os** are accessible through the Caravel SOC's logic analyzer and wishbone interfaces, which are controlled by the RISC-V processor. See :ref:`io_resoure_debug` and :ref:`io_resource_accelerator` for details. 
+- **114 internal I/Os** are accessible through the Caravel SOC's logic analyzer and wishbone interfaces, which are controlled by the RISC-V processor. See :ref:`io_resource_debug` and :ref:`io_resource_accelerator` for details. 
 
 .. note:: The connectivity of the 114 internal I/Os can be switched through a GPIO of Caravel SoC. As a result, the FPGA can operate in different modes. 
 

TESTBENCH/k4_non_adder_caravel_io_FPGA_12x12_fdhd_cc/verilog_testbench/and2_post_pnr_include_netlists.v

@@ -52,10 +52,13 @@
 `include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/buf/sky130_fd_sc_hd__buf_8.v"
 `include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/clkdlybuf4s50/sky130_fd_sc_hd__clkdlybuf4s50_2.v"
 `include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/buf/sky130_fd_sc_hd__buf_12.v"
+`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/buf/sky130_fd_sc_hd__buf_1.v"
+`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/buf/sky130_fd_sc_hd__buf_16.v"
+`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/bufbuf/sky130_fd_sc_hd__bufbuf_16.v"
 
 // ------ Include fabric top-level netlists -----
-`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/FPGA1212_FC_HD_SKY_PNR/fpga_core/fpga_core_icv_in_design.pt.v"
-
+//`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/FPGA1212_FC_HD_SKY_PNR/fpga_core/fpga_core_icv_in_design.pt.v"
+`include "/research/ece/lnis/USERS/DARPA_ERI/Tapeout/Nov2020_Skywater/FPGA1212_FLAT_HD_SKY_PNR/fpga_core/fpga_core_icv_in_design.pt.v"
 
 `ifdef AUTOCHECKED_SIMULATION
 	`include "and2_output_verilog.v"