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Change configuration flipflop + Fixed configuration chain

This commit is contained in:
Ganesh Gore 2020-11-09 19:17:15 -07:00
parent 015c67e10f
commit 7dd7e33cb6
139 changed files with 95732 additions and 103692 deletions
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34
FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/OpenFPGAEngine.info
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@ -1,35 +1,35 @@
commit 55f7a2c187139d471143f91dc368bb1497e2eb78
Merge: 1f3e656f 93e7107d
commit 520e54d7abecebf75310bb901ce702532148d686
Merge: 4a53640c 056b7c0c
Author: Laboratory for Nano Integrated Systems (LNIS) <40280375+LNIS-Projects@users.noreply.github.com>
Date: Wed Nov 4 21:55:37 2020 -0700
Date: Fri Nov 6 13:25:29 2020 -0700
Merge pull request #116 from LNIS-Projects/dev
Merge pull request #118 from LNIS-Projects/dev
Extended I/O Support for SoC I/O interface
Remove the restrictions on requiring two outputs for configurable memory circuits
commit 93e7107d800259ad9031c6b5d4572e8a971c6403
commit 056b7c0c7997d2d12473f2fc4b7915e25ff74820
Author: tangxifan <tangxifan@gmail.com>
Date: Wed Nov 4 20:59:34 2020 -0700
Date: Fri Nov 6 12:22:22 2020 -0700
[Test] Add new test to CI
[Doc] Update documentation about CCFF circuit model examples
commit bce8233019cec3b7f778befd9457c9c637b05c6c
commit 70734abc35347dbc27113200908858c9a66e9945
Author: tangxifan <tangxifan@gmail.com>
Date: Wed Nov 4 20:58:58 2020 -0700
Date: Fri Nov 6 11:20:13 2020 -0700
[Arch] Bug fix in caravel arch
[Arch] Remove QN from stdcell arch
commit 6b48ee7f0bd6c86181cdbbb468c4cf8e7af5c4c6
commit 1a79a556467ae8d9d4d791b94462e168e15635ca
Author: tangxifan <tangxifan@gmail.com>
Date: Wed Nov 4 20:58:40 2020 -0700
Date: Fri Nov 6 11:19:19 2020 -0700
[Test] Add new test for caravel io support
[HDL] Add DFF cell with reset but only 1 output
commit c85edb4738a24c394b5eeefb08586da7bd4ead6a
commit 0a273ffab65b1f503d6e63da59c93644375dc3b1
Author: tangxifan <tangxifan@gmail.com>
Date: Wed Nov 4 20:52:47 2020 -0700
Date: Fri Nov 6 11:16:46 2020 -0700
[Arch] Bug fix for embedded io arch
[Tool] Bug fix in the tight requirements on CCFF circuit model
On branch master
Your branch is up to date with 'origin/master'.

2
FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/fabric_netlists.v
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@ -19,7 +19,7 @@
`include "/research/ece/lnis/USERS/DARPA_ERI/Tapeout/May2020/OpenFPGA_for_Chip/openfpga_flow/tasks/FPGA22_HIER_SKY_PNR/skywater/libraries/sky130_fd_sc_hd/latest/cells/or2/sky130_fd_sc_hd__or2_1.v"
`include "/research/ece/lnis/USERS/DARPA_ERI/Tapeout/May2020/OpenFPGA_for_Chip/openfpga_flow/tasks/FPGA22_HIER_SKY_PNR/skywater/libraries/sky130_fd_sc_hd/latest/cells/mux2/sky130_fd_sc_hd__mux2_1.v"
`include "/research/ece/lnis/USERS/DARPA_ERI/Tapeout/May2020/OpenFPGA_for_Chip/openfpga_flow/tasks/FPGA22_HIER_SKY_PNR/skywater/libraries/sky130_fd_sc_hd/latest/cells/sdfxtp/sky130_fd_sc_hd__sdfxtp_1.v"
`include "/research/ece/lnis/USERS/DARPA_ERI/Tapeout/May2020/OpenFPGA_for_Chip/openfpga_flow/tasks/FPGA22_HIER_SKY_PNR/skywater/libraries/sky130_fd_sc_hd/latest/cells/dfxbp/sky130_fd_sc_hd__dfxbp_1.v"
`include "/research/ece/lnis/USERS/DARPA_ERI/Tapeout/May2020/OpenFPGA_for_Chip/openfpga_flow/tasks/FPGA22_HIER_SKY_PNR/skywater/libraries/sky130_fd_sc_hd/latest/cells/dfxtp/sky130_fd_sc_hd__dfxtp_1.v"
`include "/research/ece/lnis/USERS/DARPA_ERI/Tapeout/May2020/OpenFPGA_for_Chip/openfpga_flow/tasks/FPGA22_HIER_SKY_PNR/sc_verilog/digital_io_hd.v"
//
`include "./SRC/sub_module/inv_buf_passgate.v"

32
FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/lb/logical_tile_clb_mode_clb_.v
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@ -400,7 +400,7 @@ wire [0:0] logical_tile_clb_mode_default__fle_7_fle_sc_out;
.out(clb_sc_out[0]));
direct_interc direct_interc_18_ (
.in(clb_I0[2]),
.in(clb_I0[0]),
.out(direct_interc_18_out[0]));
direct_interc direct_interc_19_ (
@ -408,7 +408,7 @@ wire [0:0] logical_tile_clb_mode_default__fle_7_fle_sc_out;
.out(direct_interc_19_out[0]));
direct_interc direct_interc_20_ (
.in(clb_I0[0]),
.in(clb_I0[2]),
.out(direct_interc_20_out[0]));
direct_interc direct_interc_21_ (
@ -428,7 +428,7 @@ wire [0:0] logical_tile_clb_mode_default__fle_7_fle_sc_out;
.out(direct_interc_24_out[0]));
direct_interc direct_interc_25_ (
.in(clb_I1[2]),
.in(clb_I1[0]),
.out(direct_interc_25_out[0]));
direct_interc direct_interc_26_ (
@ -436,7 +436,7 @@ wire [0:0] logical_tile_clb_mode_default__fle_7_fle_sc_out;
.out(direct_interc_26_out[0]));
direct_interc direct_interc_27_ (
.in(clb_I1[0]),
.in(clb_I1[2]),
.out(direct_interc_27_out[0]));
direct_interc direct_interc_28_ (
@ -456,7 +456,7 @@ wire [0:0] logical_tile_clb_mode_default__fle_7_fle_sc_out;
.out(direct_interc_31_out[0]));
direct_interc direct_interc_32_ (
.in(clb_I2[2]),
.in(clb_I2[0]),
.out(direct_interc_32_out[0]));
direct_interc direct_interc_33_ (
@ -464,7 +464,7 @@ wire [0:0] logical_tile_clb_mode_default__fle_7_fle_sc_out;
.out(direct_interc_33_out[0]));
direct_interc direct_interc_34_ (
.in(clb_I2[0]),
.in(clb_I2[2]),
.out(direct_interc_34_out[0]));
direct_interc direct_interc_35_ (
@ -484,7 +484,7 @@ wire [0:0] logical_tile_clb_mode_default__fle_7_fle_sc_out;
.out(direct_interc_38_out[0]));
direct_interc direct_interc_39_ (
.in(clb_I3[2]),
.in(clb_I3[0]),
.out(direct_interc_39_out[0]));
direct_interc direct_interc_40_ (
@ -492,7 +492,7 @@ wire [0:0] logical_tile_clb_mode_default__fle_7_fle_sc_out;
.out(direct_interc_40_out[0]));
direct_interc direct_interc_41_ (
.in(clb_I3[0]),
.in(clb_I3[2]),
.out(direct_interc_41_out[0]));
direct_interc direct_interc_42_ (
@ -512,7 +512,7 @@ wire [0:0] logical_tile_clb_mode_default__fle_7_fle_sc_out;
.out(direct_interc_45_out[0]));
direct_interc direct_interc_46_ (
.in(clb_I4[2]),
.in(clb_I4[0]),
.out(direct_interc_46_out[0]));
direct_interc direct_interc_47_ (
@ -520,7 +520,7 @@ wire [0:0] logical_tile_clb_mode_default__fle_7_fle_sc_out;
.out(direct_interc_47_out[0]));
direct_interc direct_interc_48_ (
.in(clb_I4[0]),
.in(clb_I4[2]),
.out(direct_interc_48_out[0]));
direct_interc direct_interc_49_ (
@ -540,7 +540,7 @@ wire [0:0] logical_tile_clb_mode_default__fle_7_fle_sc_out;
.out(direct_interc_52_out[0]));
direct_interc direct_interc_53_ (
.in(clb_I5[2]),
.in(clb_I5[0]),
.out(direct_interc_53_out[0]));
direct_interc direct_interc_54_ (
@ -548,7 +548,7 @@ wire [0:0] logical_tile_clb_mode_default__fle_7_fle_sc_out;
.out(direct_interc_54_out[0]));
direct_interc direct_interc_55_ (
.in(clb_I5[0]),
.in(clb_I5[2]),
.out(direct_interc_55_out[0]));
direct_interc direct_interc_56_ (
@ -568,7 +568,7 @@ wire [0:0] logical_tile_clb_mode_default__fle_7_fle_sc_out;
.out(direct_interc_59_out[0]));
direct_interc direct_interc_60_ (
.in(clb_I6[2]),
.in(clb_I6[0]),
.out(direct_interc_60_out[0]));
direct_interc direct_interc_61_ (
@ -576,7 +576,7 @@ wire [0:0] logical_tile_clb_mode_default__fle_7_fle_sc_out;
.out(direct_interc_61_out[0]));
direct_interc direct_interc_62_ (
.in(clb_I6[0]),
.in(clb_I6[2]),
.out(direct_interc_62_out[0]));
direct_interc direct_interc_63_ (
@ -596,7 +596,7 @@ wire [0:0] logical_tile_clb_mode_default__fle_7_fle_sc_out;
.out(direct_interc_66_out[0]));
direct_interc direct_interc_67_ (
.in(clb_I7[2]),
.in(clb_I7[0]),
.out(direct_interc_67_out[0]));
direct_interc direct_interc_68_ (
@ -604,7 +604,7 @@ wire [0:0] logical_tile_clb_mode_default__fle_7_fle_sc_out;
.out(direct_interc_68_out[0]));
direct_interc direct_interc_69_ (
.in(clb_I7[0]),
.in(clb_I7[2]),
.out(direct_interc_69_out[0]));
direct_interc direct_interc_70_ (

21
FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/lb/logical_tile_clb_mode_default__fle_mode_physical__fabric.v
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@ -75,13 +75,13 @@ wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default
wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_1_ff_Q;
wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail;
wire [0:1] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out;
wire [0:1] mux_fabric_out_0_undriven_sram_inv;
wire [0:1] mux_fabric_out_1_undriven_sram_inv;
wire [0:1] mux_ff_0_D_0_undriven_sram_inv;
wire [0:1] mux_tree_size2_0_sram;
wire [0:1] mux_tree_size2_0_sram_inv;
wire [0:1] mux_tree_size2_1_sram;
wire [0:1] mux_tree_size2_1_sram_inv;
wire [0:0] mux_tree_size2_2_out;
wire [0:1] mux_tree_size2_2_sram;
wire [0:1] mux_tree_size2_2_sram_inv;
wire [0:0] mux_tree_size2_mem_0_ccff_tail;
wire [0:0] mux_tree_size2_mem_1_ccff_tail;
@ -116,41 +116,38 @@ wire [0:0] mux_tree_size2_mem_1_ccff_tail;
mux_tree_size2 mux_fabric_out_0 (
.in({logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q[0], logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[0]}),
.sram(mux_tree_size2_0_sram[0:1]),
.sram_inv(mux_tree_size2_0_sram_inv[0:1]),
.sram_inv(mux_fabric_out_0_undriven_sram_inv[0:1]),
.out(fabric_out[0]));
mux_tree_size2 mux_fabric_out_1 (
.in({logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_1_ff_Q[0], logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[1]}),
.sram(mux_tree_size2_1_sram[0:1]),
.sram_inv(mux_tree_size2_1_sram_inv[0:1]),
.sram_inv(mux_fabric_out_1_undriven_sram_inv[0:1]),
.out(fabric_out[1]));
mux_tree_size2 mux_ff_0_D_0 (
.in({logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[0], fabric_regin[0]}),
.sram(mux_tree_size2_2_sram[0:1]),
.sram_inv(mux_tree_size2_2_sram_inv[0:1]),
.sram_inv(mux_ff_0_D_0_undriven_sram_inv[0:1]),
.out(mux_tree_size2_2_out[0]));
mux_tree_size2_mem mem_fabric_out_0 (
.prog_clk(prog_clk[0]),
.ccff_head(logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail[0]),
.ccff_tail(mux_tree_size2_mem_0_ccff_tail[0]),
.mem_out(mux_tree_size2_0_sram[0:1]),
.mem_outb(mux_tree_size2_0_sram_inv[0:1]));
.mem_out(mux_tree_size2_0_sram[0:1]));
mux_tree_size2_mem mem_fabric_out_1 (
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_size2_mem_0_ccff_tail[0]),
.ccff_tail(mux_tree_size2_mem_1_ccff_tail[0]),
.mem_out(mux_tree_size2_1_sram[0:1]),
.mem_outb(mux_tree_size2_1_sram_inv[0:1]));
.mem_out(mux_tree_size2_1_sram[0:1]));
mux_tree_size2_mem mem_ff_0_D_0 (
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_size2_mem_1_ccff_tail[0]),
.ccff_tail(ccff_tail[0]),
.mem_out(mux_tree_size2_2_sram[0:1]),
.mem_outb(mux_tree_size2_2_sram_inv[0:1]));
.mem_out(mux_tree_size2_2_sram[0:1]));
direct_interc direct_interc_0_ (
.in(logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_1_ff_Q[0]),

7
FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/lb/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic.v
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@ -43,8 +43,8 @@ wire [0:0] direct_interc_4_out;
wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_ccff_tail;
wire [0:1] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut3_out;
wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut4_out;
wire [0:1] mux_frac_logic_out_0_undriven_sram_inv;
wire [0:1] mux_tree_size2_0_sram;
wire [0:1] mux_tree_size2_0_sram_inv;
//
//
@ -62,15 +62,14 @@ wire [0:1] mux_tree_size2_0_sram_inv;
mux_tree_size2 mux_frac_logic_out_0 (
.in({logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut4_out[0], logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut3_out[0]}),
.sram(mux_tree_size2_0_sram[0:1]),
.sram_inv(mux_tree_size2_0_sram_inv[0:1]),
.sram_inv(mux_frac_logic_out_0_undriven_sram_inv[0:1]),
.out(frac_logic_out[0]));
mux_tree_size2_mem mem_frac_logic_out_0 (
.prog_clk(prog_clk[0]),
.ccff_head(logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_ccff_tail[0]),
.ccff_tail(ccff_tail[0]),
.mem_out(mux_tree_size2_0_sram[0:1]),
.mem_outb(mux_tree_size2_0_sram_inv[0:1]));
.mem_out(mux_tree_size2_0_sram[0:1]));
direct_interc direct_interc_0_ (
.in(logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut3_out[1]),

13
FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/lb/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4.v
View File

@ -39,10 +39,10 @@ wire [0:0] frac_lut4_lut4_out;
//
wire [0:0] frac_lut4_0__undriven_mode_inv;
wire [0:15] frac_lut4_0__undriven_sram_inv;
wire [0:0] frac_lut4_0_mode;
wire [0:0] frac_lut4_0_mode_inv;
wire [0:15] frac_lut4_0_sram;
wire [0:15] frac_lut4_0_sram_inv;
//
//
@ -52,18 +52,17 @@ wire [0:15] frac_lut4_0_sram_inv;
frac_lut4 frac_lut4_0_ (
.in(frac_lut4_in[0:3]),
.sram(frac_lut4_0_sram[0:15]),
.sram_inv(frac_lut4_0_sram_inv[0:15]),
.sram_inv(frac_lut4_0__undriven_sram_inv[0:15]),
.mode(frac_lut4_0_mode[0]),
.mode_inv(frac_lut4_0_mode_inv[0]),
.mode_inv(frac_lut4_0__undriven_mode_inv[0]),
.lut3_out(frac_lut4_lut3_out[0:1]),
.lut4_out(frac_lut4_lut4_out[0]));
frac_lut4_sky130_fd_sc_hd__dfxbp_1_mem frac_lut4_sky130_fd_sc_hd__dfxbp_1_mem (
frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem (
.prog_clk(prog_clk[0]),
.ccff_head(ccff_head[0]),
.ccff_tail(ccff_tail[0]),
.mem_out({frac_lut4_0_sram[0:15], frac_lut4_0_mode[0]}),
.mem_outb({frac_lut4_0_sram_inv[0:15], frac_lut4_0_mode_inv[0]}));
.mem_out({frac_lut4_0_sram[0:15], frac_lut4_0_mode[0]}));
endmodule
//

6
FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/lb/logical_tile_io_mode_physical__iopad.v
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@ -45,7 +45,6 @@ wire [0:0] iopad_inpad;
wire [0:0] EMBEDDED_IO_0_en;
wire [0:0] EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem_undriven_mem_outb;
//
//
@ -60,12 +59,11 @@ wire [0:0] EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem_undriven_mem_outb;
.FPGA_DIR(EMBEDDED_IO_0_en[0]),
.FPGA_IN(iopad_inpad[0]));
EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem (
EMBEDDED_IO_sky130_fd_sc_hd__dfxtp_1_mem EMBEDDED_IO_sky130_fd_sc_hd__dfxtp_1_mem (
.prog_clk(prog_clk[0]),
.ccff_head(ccff_head[0]),
.ccff_tail(ccff_tail[0]),
.mem_out(EMBEDDED_IO_0_en[0]),
.mem_outb(EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem_undriven_mem_outb[0]));
.mem_out(EMBEDDED_IO_0_en[0]));
endmodule
//

52
FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/routing/cbx_1__0_.v
View File

@ -41,18 +41,18 @@ module cbx_1__0_
output SC_OUT_TOP;
output SC_OUT_BOT;
wire [0:3] mux_top_ipin_0_undriven_sram_inv;
wire [0:3] mux_top_ipin_1_undriven_sram_inv;
wire [0:3] mux_top_ipin_2_undriven_sram_inv;
wire [0:3] mux_top_ipin_3_undriven_sram_inv;
wire [0:3] mux_top_ipin_4_undriven_sram_inv;
wire [0:3] mux_top_ipin_5_undriven_sram_inv;
wire [0:3] mux_tree_tapbuf_size10_0_sram;
wire [0:3] mux_tree_tapbuf_size10_0_sram_inv;
wire [0:3] mux_tree_tapbuf_size10_1_sram;
wire [0:3] mux_tree_tapbuf_size10_1_sram_inv;
wire [0:3] mux_tree_tapbuf_size10_2_sram;
wire [0:3] mux_tree_tapbuf_size10_2_sram_inv;
wire [0:3] mux_tree_tapbuf_size10_3_sram;
wire [0:3] mux_tree_tapbuf_size10_3_sram_inv;
wire [0:3] mux_tree_tapbuf_size10_4_sram;
wire [0:3] mux_tree_tapbuf_size10_4_sram_inv;
wire [0:3] mux_tree_tapbuf_size10_5_sram;
wire [0:3] mux_tree_tapbuf_size10_5_sram_inv;
wire [0:0] mux_tree_tapbuf_size10_mem_0_ccff_tail;
wire [0:0] mux_tree_tapbuf_size10_mem_1_ccff_tail;
wire [0:0] mux_tree_tapbuf_size10_mem_2_ccff_tail;
@ -118,7 +118,7 @@ module cbx_1__0_
(
.in({ chanx_left_in[0], chanx_right_in[0], chanx_left_in[2], chanx_right_in[2], chanx_left_in[4], chanx_right_in[4], chanx_left_in[10], chanx_right_in[10], chanx_left_in[16], chanx_right_in[16] }),
.sram(mux_tree_tapbuf_size10_0_sram[0:3]),
.sram_inv(mux_tree_tapbuf_size10_0_sram_inv[0:3]),
.sram_inv(mux_top_ipin_0_undriven_sram_inv[0:3]),
.out(bottom_grid_pin_0_[0])
);
@ -128,7 +128,7 @@ module cbx_1__0_
(
.in({ chanx_left_in[1], chanx_right_in[1], chanx_left_in[3], chanx_right_in[3], chanx_left_in[5], chanx_right_in[5], chanx_left_in[11], chanx_right_in[11], chanx_left_in[17], chanx_right_in[17] }),
.sram(mux_tree_tapbuf_size10_1_sram[0:3]),
.sram_inv(mux_tree_tapbuf_size10_1_sram_inv[0:3]),
.sram_inv(mux_top_ipin_1_undriven_sram_inv[0:3]),
.out(bottom_grid_pin_2_[0])
);
@ -138,7 +138,7 @@ module cbx_1__0_
(
.in({ chanx_left_in[0], chanx_right_in[0], chanx_left_in[2], chanx_right_in[2], chanx_left_in[6], chanx_right_in[6], chanx_left_in[12], chanx_right_in[12], chanx_left_in[18], chanx_right_in[18] }),
.sram(mux_tree_tapbuf_size10_2_sram[0:3]),
.sram_inv(mux_tree_tapbuf_size10_2_sram_inv[0:3]),
.sram_inv(mux_top_ipin_2_undriven_sram_inv[0:3]),
.out(bottom_grid_pin_4_[0])
);
@ -148,7 +148,7 @@ module cbx_1__0_
(
.in({ chanx_left_in[1], chanx_right_in[1], chanx_left_in[3], chanx_right_in[3], chanx_left_in[7], chanx_right_in[7], chanx_left_in[13], chanx_right_in[13], chanx_left_in[19], chanx_right_in[19] }),
.sram(mux_tree_tapbuf_size10_3_sram[0:3]),
.sram_inv(mux_tree_tapbuf_size10_3_sram_inv[0:3]),
.sram_inv(mux_top_ipin_3_undriven_sram_inv[0:3]),
.out(bottom_grid_pin_6_[0])
);
@ -158,7 +158,7 @@ module cbx_1__0_
(
.in({ chanx_left_in[0], chanx_right_in[0], chanx_left_in[2], chanx_right_in[2], chanx_left_in[4], chanx_right_in[4], chanx_left_in[8], chanx_right_in[8], chanx_left_in[14], chanx_right_in[14] }),
.sram(mux_tree_tapbuf_size10_4_sram[0:3]),
.sram_inv(mux_tree_tapbuf_size10_4_sram_inv[0:3]),
.sram_inv(mux_top_ipin_4_undriven_sram_inv[0:3]),
.out(bottom_grid_pin_8_[0])
);
@ -168,7 +168,7 @@ module cbx_1__0_
(
.in({ chanx_left_in[1], chanx_right_in[1], chanx_left_in[3], chanx_right_in[3], chanx_left_in[5], chanx_right_in[5], chanx_left_in[9], chanx_right_in[9], chanx_left_in[15], chanx_right_in[15] }),
.sram(mux_tree_tapbuf_size10_5_sram[0:3]),
.sram_inv(mux_tree_tapbuf_size10_5_sram_inv[0:3]),
.sram_inv(mux_top_ipin_5_undriven_sram_inv[0:3]),
.out(bottom_grid_pin_10_[0])
);
@ -179,8 +179,7 @@ module cbx_1__0_
.prog_clk(prog_clk[0]),
.ccff_head(ccff_head[0]),
.ccff_tail(mux_tree_tapbuf_size10_mem_0_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size10_0_sram[0:3]),
.mem_outb(mux_tree_tapbuf_size10_0_sram_inv[0:3])
.mem_out(mux_tree_tapbuf_size10_0_sram[0:3])
);
@ -190,8 +189,7 @@ module cbx_1__0_
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size10_mem_0_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size10_mem_1_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size10_1_sram[0:3]),
.mem_outb(mux_tree_tapbuf_size10_1_sram_inv[0:3])
.mem_out(mux_tree_tapbuf_size10_1_sram[0:3])
);
@ -201,8 +199,7 @@ module cbx_1__0_
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size10_mem_1_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size10_mem_2_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size10_2_sram[0:3]),
.mem_outb(mux_tree_tapbuf_size10_2_sram_inv[0:3])
.mem_out(mux_tree_tapbuf_size10_2_sram[0:3])
);
@ -212,8 +209,7 @@ module cbx_1__0_
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size10_mem_2_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size10_mem_3_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size10_3_sram[0:3]),
.mem_outb(mux_tree_tapbuf_size10_3_sram_inv[0:3])
.mem_out(mux_tree_tapbuf_size10_3_sram[0:3])
);
@ -223,8 +219,7 @@ module cbx_1__0_
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size10_mem_3_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size10_mem_4_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size10_4_sram[0:3]),
.mem_outb(mux_tree_tapbuf_size10_4_sram_inv[0:3])
.mem_out(mux_tree_tapbuf_size10_4_sram[0:3])
);
@ -234,8 +229,7 @@ module cbx_1__0_
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size10_mem_4_ccff_tail[0]),
.ccff_tail(ccff_tail_mid),
.mem_out(mux_tree_tapbuf_size10_5_sram[0:3]),
.mem_outb(mux_tree_tapbuf_size10_5_sram_inv[0:3])
.mem_out(mux_tree_tapbuf_size10_5_sram[0:3])
);
@ -261,7 +255,7 @@ module cbx_1__0_
.gfpga_pad_EMBEDDED_IO_SOC_OUT(gfpga_pad_EMBEDDED_IO_SOC_OUT[1]),
.gfpga_pad_EMBEDDED_IO_SOC_DIR(gfpga_pad_EMBEDDED_IO_SOC_DIR[1]),
.io_outpad(top_width_0_height_0__pin_2_[0]),
.ccff_head(ccff_tail_mid),
.ccff_head(logical_tile_io_mode_io__0_ccff_tail[0]),
.io_inpad(top_width_0_height_0__pin_3_upper[0]),
.ccff_tail(logical_tile_io_mode_io__1_ccff_tail[0])
);
@ -275,7 +269,7 @@ module cbx_1__0_
.gfpga_pad_EMBEDDED_IO_SOC_OUT(gfpga_pad_EMBEDDED_IO_SOC_OUT[2]),
.gfpga_pad_EMBEDDED_IO_SOC_DIR(gfpga_pad_EMBEDDED_IO_SOC_DIR[2]),
.io_outpad(top_width_0_height_0__pin_4_[0]),
.ccff_head(ccff_tail_mid),
.ccff_head(logical_tile_io_mode_io__1_ccff_tail[0]),
.io_inpad(top_width_0_height_0__pin_5_upper[0]),
.ccff_tail(logical_tile_io_mode_io__2_ccff_tail[0])
);
@ -289,7 +283,7 @@ module cbx_1__0_
.gfpga_pad_EMBEDDED_IO_SOC_OUT(gfpga_pad_EMBEDDED_IO_SOC_OUT[3]),
.gfpga_pad_EMBEDDED_IO_SOC_DIR(gfpga_pad_EMBEDDED_IO_SOC_DIR[3]),
.io_outpad(top_width_0_height_0__pin_6_[0]),
.ccff_head(ccff_tail_mid),
.ccff_head(logical_tile_io_mode_io__2_ccff_tail[0]),
.io_inpad(top_width_0_height_0__pin_7_upper[0]),
.ccff_tail(logical_tile_io_mode_io__3_ccff_tail[0])
);
@ -303,7 +297,7 @@ module cbx_1__0_
.gfpga_pad_EMBEDDED_IO_SOC_OUT(gfpga_pad_EMBEDDED_IO_SOC_OUT[4]),
.gfpga_pad_EMBEDDED_IO_SOC_DIR(gfpga_pad_EMBEDDED_IO_SOC_DIR[4]),
.io_outpad(top_width_0_height_0__pin_8_[0]),
.ccff_head(ccff_tail_mid),
.ccff_head(logical_tile_io_mode_io__3_ccff_tail[0]),
.io_inpad(top_width_0_height_0__pin_9_upper[0]),
.ccff_tail(logical_tile_io_mode_io__4_ccff_tail[0])
);
@ -317,7 +311,7 @@ module cbx_1__0_
.gfpga_pad_EMBEDDED_IO_SOC_OUT(gfpga_pad_EMBEDDED_IO_SOC_OUT[5]),
.gfpga_pad_EMBEDDED_IO_SOC_DIR(gfpga_pad_EMBEDDED_IO_SOC_DIR[5]),
.io_outpad(top_width_0_height_0__pin_10_[0]),
.ccff_head(ccff_tail_mid),
.ccff_head(logical_tile_io_mode_io__4_ccff_tail[0]),
.io_inpad(top_width_0_height_0__pin_11_upper[0]),
.ccff_tail(ccff_tail[0])
);

112
FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/routing/cbx_1__1_.v
View File

@ -30,22 +30,30 @@ module cbx_1__1_
output SC_OUT_TOP;
output SC_OUT_BOT;
wire [0:3] mux_top_ipin_0_undriven_sram_inv;
wire [0:3] mux_top_ipin_10_undriven_sram_inv;
wire [0:3] mux_top_ipin_11_undriven_sram_inv;
wire [0:3] mux_top_ipin_12_undriven_sram_inv;
wire [0:3] mux_top_ipin_13_undriven_sram_inv;
wire [0:3] mux_top_ipin_14_undriven_sram_inv;
wire [0:3] mux_top_ipin_15_undriven_sram_inv;
wire [0:3] mux_top_ipin_1_undriven_sram_inv;
wire [0:3] mux_top_ipin_2_undriven_sram_inv;
wire [0:3] mux_top_ipin_3_undriven_sram_inv;
wire [0:3] mux_top_ipin_4_undriven_sram_inv;
wire [0:3] mux_top_ipin_5_undriven_sram_inv;
wire [0:3] mux_top_ipin_6_undriven_sram_inv;
wire [0:3] mux_top_ipin_7_undriven_sram_inv;
wire [0:3] mux_top_ipin_8_undriven_sram_inv;
wire [0:3] mux_top_ipin_9_undriven_sram_inv;
wire [0:3] mux_tree_tapbuf_size10_0_sram;
wire [0:3] mux_tree_tapbuf_size10_0_sram_inv;
wire [0:3] mux_tree_tapbuf_size10_1_sram;
wire [0:3] mux_tree_tapbuf_size10_1_sram_inv;
wire [0:3] mux_tree_tapbuf_size10_2_sram;
wire [0:3] mux_tree_tapbuf_size10_2_sram_inv;
wire [0:3] mux_tree_tapbuf_size10_3_sram;
wire [0:3] mux_tree_tapbuf_size10_3_sram_inv;
wire [0:3] mux_tree_tapbuf_size10_4_sram;
wire [0:3] mux_tree_tapbuf_size10_4_sram_inv;
wire [0:3] mux_tree_tapbuf_size10_5_sram;
wire [0:3] mux_tree_tapbuf_size10_5_sram_inv;
wire [0:3] mux_tree_tapbuf_size10_6_sram;
wire [0:3] mux_tree_tapbuf_size10_6_sram_inv;
wire [0:3] mux_tree_tapbuf_size10_7_sram;
wire [0:3] mux_tree_tapbuf_size10_7_sram_inv;
wire [0:0] mux_tree_tapbuf_size10_mem_0_ccff_tail;
wire [0:0] mux_tree_tapbuf_size10_mem_1_ccff_tail;
wire [0:0] mux_tree_tapbuf_size10_mem_2_ccff_tail;
@ -54,21 +62,13 @@ module cbx_1__1_
wire [0:0] mux_tree_tapbuf_size10_mem_5_ccff_tail;
wire [0:0] mux_tree_tapbuf_size10_mem_6_ccff_tail;
wire [0:3] mux_tree_tapbuf_size8_0_sram;
wire [0:3] mux_tree_tapbuf_size8_0_sram_inv;
wire [0:3] mux_tree_tapbuf_size8_1_sram;
wire [0:3] mux_tree_tapbuf_size8_1_sram_inv;
wire [0:3] mux_tree_tapbuf_size8_2_sram;
wire [0:3] mux_tree_tapbuf_size8_2_sram_inv;
wire [0:3] mux_tree_tapbuf_size8_3_sram;
wire [0:3] mux_tree_tapbuf_size8_3_sram_inv;
wire [0:3] mux_tree_tapbuf_size8_4_sram;
wire [0:3] mux_tree_tapbuf_size8_4_sram_inv;
wire [0:3] mux_tree_tapbuf_size8_5_sram;
wire [0:3] mux_tree_tapbuf_size8_5_sram_inv;
wire [0:3] mux_tree_tapbuf_size8_6_sram;
wire [0:3] mux_tree_tapbuf_size8_6_sram_inv;
wire [0:3] mux_tree_tapbuf_size8_7_sram;
wire [0:3] mux_tree_tapbuf_size8_7_sram_inv;
wire [0:0] mux_tree_tapbuf_size8_mem_0_ccff_tail;
wire [0:0] mux_tree_tapbuf_size8_mem_1_ccff_tail;
wire [0:0] mux_tree_tapbuf_size8_mem_2_ccff_tail;
@ -125,7 +125,7 @@ module cbx_1__1_
(
.in({ chanx_left_in[0], chanx_right_in[0], chanx_left_in[2], chanx_right_in[2], chanx_left_in[4], chanx_right_in[4], chanx_left_in[10], chanx_right_in[10], chanx_left_in[16], chanx_right_in[16] }),
.sram(mux_tree_tapbuf_size10_0_sram[0:3]),
.sram_inv(mux_tree_tapbuf_size10_0_sram_inv[0:3]),
.sram_inv(mux_top_ipin_0_undriven_sram_inv[0:3]),
.out(bottom_grid_pin_0_[0])
);
@ -135,7 +135,7 @@ module cbx_1__1_
(
.in({ chanx_left_in[1], chanx_right_in[1], chanx_left_in[3], chanx_right_in[3], chanx_left_in[7], chanx_right_in[7], chanx_left_in[13], chanx_right_in[13], chanx_left_in[19], chanx_right_in[19] }),
.sram(mux_tree_tapbuf_size10_1_sram[0:3]),
.sram_inv(mux_tree_tapbuf_size10_1_sram_inv[0:3]),
.sram_inv(mux_top_ipin_3_undriven_sram_inv[0:3]),
.out(bottom_grid_pin_3_[0])
);
@ -145,7 +145,7 @@ module cbx_1__1_
(
.in({ chanx_left_in[0], chanx_right_in[0], chanx_left_in[2], chanx_right_in[2], chanx_left_in[4], chanx_right_in[4], chanx_left_in[8], chanx_right_in[8], chanx_left_in[14], chanx_right_in[14] }),
.sram(mux_tree_tapbuf_size10_2_sram[0:3]),
.sram_inv(mux_tree_tapbuf_size10_2_sram_inv[0:3]),
.sram_inv(mux_top_ipin_4_undriven_sram_inv[0:3]),
.out(bottom_grid_pin_4_[0])
);
@ -155,7 +155,7 @@ module cbx_1__1_
(
.in({ chanx_left_in[1], chanx_right_in[1], chanx_left_in[3], chanx_right_in[3], chanx_left_in[7], chanx_right_in[7], chanx_left_in[11], chanx_right_in[11], chanx_left_in[17], chanx_right_in[17] }),
.sram(mux_tree_tapbuf_size10_3_sram[0:3]),
.sram_inv(mux_tree_tapbuf_size10_3_sram_inv[0:3]),
.sram_inv(mux_top_ipin_7_undriven_sram_inv[0:3]),
.out(bottom_grid_pin_7_[0])
);
@ -165,7 +165,7 @@ module cbx_1__1_
(
.in({ chanx_left_in[0], chanx_right_in[0], chanx_left_in[2], chanx_right_in[2], chanx_left_in[8], chanx_right_in[8], chanx_left_in[12], chanx_right_in[12], chanx_left_in[18], chanx_right_in[18] }),
.sram(mux_tree_tapbuf_size10_4_sram[0:3]),
.sram_inv(mux_tree_tapbuf_size10_4_sram_inv[0:3]),
.sram_inv(mux_top_ipin_8_undriven_sram_inv[0:3]),
.out(bottom_grid_pin_8_[0])
);
@ -175,7 +175,7 @@ module cbx_1__1_
(
.in({ chanx_left_in[1], chanx_right_in[1], chanx_left_in[3], chanx_right_in[3], chanx_left_in[5], chanx_right_in[5], chanx_left_in[11], chanx_right_in[11], chanx_left_in[15], chanx_right_in[15] }),
.sram(mux_tree_tapbuf_size10_5_sram[0:3]),
.sram_inv(mux_tree_tapbuf_size10_5_sram_inv[0:3]),
.sram_inv(mux_top_ipin_11_undriven_sram_inv[0:3]),
.out(bottom_grid_pin_11_[0])
);
@ -185,7 +185,7 @@ module cbx_1__1_
(
.in({ chanx_left_in[0], chanx_right_in[0], chanx_left_in[2], chanx_right_in[2], chanx_left_in[6], chanx_right_in[6], chanx_left_in[12], chanx_right_in[12], chanx_left_in[16], chanx_right_in[16] }),
.sram(mux_tree_tapbuf_size10_6_sram[0:3]),
.sram_inv(mux_tree_tapbuf_size10_6_sram_inv[0:3]),
.sram_inv(mux_top_ipin_12_undriven_sram_inv[0:3]),
.out(bottom_grid_pin_12_[0])
);
@ -195,7 +195,7 @@ module cbx_1__1_
(
.in({ chanx_left_in[1], chanx_right_in[1], chanx_left_in[3], chanx_right_in[3], chanx_left_in[9], chanx_right_in[9], chanx_left_in[15], chanx_right_in[15], chanx_left_in[19], chanx_right_in[19] }),
.sram(mux_tree_tapbuf_size10_7_sram[0:3]),
.sram_inv(mux_tree_tapbuf_size10_7_sram_inv[0:3]),
.sram_inv(mux_top_ipin_15_undriven_sram_inv[0:3]),
.out(bottom_grid_pin_15_[0])
);
@ -206,8 +206,7 @@ module cbx_1__1_
.prog_clk(prog_clk[0]),
.ccff_head(ccff_head[0]),
.ccff_tail(mux_tree_tapbuf_size10_mem_0_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size10_0_sram[0:3]),
.mem_outb(mux_tree_tapbuf_size10_0_sram_inv[0:3])
.mem_out(mux_tree_tapbuf_size10_0_sram[0:3])
);
@ -217,8 +216,7 @@ module cbx_1__1_
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size8_mem_1_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size10_mem_1_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size10_1_sram[0:3]),
.mem_outb(mux_tree_tapbuf_size10_1_sram_inv[0:3])
.mem_out(mux_tree_tapbuf_size10_1_sram[0:3])
);
@ -228,8 +226,7 @@ module cbx_1__1_
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size10_mem_1_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size10_mem_2_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size10_2_sram[0:3]),
.mem_outb(mux_tree_tapbuf_size10_2_sram_inv[0:3])
.mem_out(mux_tree_tapbuf_size10_2_sram[0:3])
);
@ -239,8 +236,7 @@ module cbx_1__1_
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size8_mem_3_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size10_mem_3_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size10_3_sram[0:3]),
.mem_outb(mux_tree_tapbuf_size10_3_sram_inv[0:3])
.mem_out(mux_tree_tapbuf_size10_3_sram[0:3])
);
@ -250,8 +246,7 @@ module cbx_1__1_
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size10_mem_3_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size10_mem_4_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size10_4_sram[0:3]),
.mem_outb(mux_tree_tapbuf_size10_4_sram_inv[0:3])
.mem_out(mux_tree_tapbuf_size10_4_sram[0:3])
);
@ -261,8 +256,7 @@ module cbx_1__1_
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size8_mem_5_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size10_mem_5_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size10_5_sram[0:3]),
.mem_outb(mux_tree_tapbuf_size10_5_sram_inv[0:3])
.mem_out(mux_tree_tapbuf_size10_5_sram[0:3])
);
@ -272,8 +266,7 @@ module cbx_1__1_
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size10_mem_5_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size10_mem_6_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size10_6_sram[0:3]),
.mem_outb(mux_tree_tapbuf_size10_6_sram_inv[0:3])
.mem_out(mux_tree_tapbuf_size10_6_sram[0:3])
);
@ -283,8 +276,7 @@ module cbx_1__1_
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size8_mem_7_ccff_tail[0]),
.ccff_tail(ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size10_7_sram[0:3]),
.mem_outb(mux_tree_tapbuf_size10_7_sram_inv[0:3])
.mem_out(mux_tree_tapbuf_size10_7_sram[0:3])
);
@ -293,7 +285,7 @@ module cbx_1__1_
(
.in({ chanx_left_in[1], chanx_right_in[1], chanx_left_in[3], chanx_right_in[3], chanx_left_in[5], chanx_right_in[5], chanx_left_in[13], chanx_right_in[13] }),
.sram(mux_tree_tapbuf_size8_0_sram[0:3]),
.sram_inv(mux_tree_tapbuf_size8_0_sram_inv[0:3]),
.sram_inv(mux_top_ipin_1_undriven_sram_inv[0:3]),
.out(bottom_grid_pin_1_[0])
);
@ -303,7 +295,7 @@ module cbx_1__1_
(
.in({ chanx_left_in[0], chanx_right_in[0], chanx_left_in[2], chanx_right_in[2], chanx_left_in[6], chanx_right_in[6], chanx_left_in[14], chanx_right_in[14] }),
.sram(mux_tree_tapbuf_size8_1_sram[0:3]),
.sram_inv(mux_tree_tapbuf_size8_1_sram_inv[0:3]),
.sram_inv(mux_top_ipin_2_undriven_sram_inv[0:3]),
.out(bottom_grid_pin_2_[0])
);
@ -313,7 +305,7 @@ module cbx_1__1_
(
.in({ chanx_left_in[1], chanx_right_in[1], chanx_left_in[3], chanx_right_in[3], chanx_left_in[9], chanx_right_in[9], chanx_left_in[17], chanx_right_in[17] }),
.sram(mux_tree_tapbuf_size8_2_sram[0:3]),
.sram_inv(mux_tree_tapbuf_size8_2_sram_inv[0:3]),
.sram_inv(mux_top_ipin_5_undriven_sram_inv[0:3]),
.out(bottom_grid_pin_5_[0])
);
@ -323,7 +315,7 @@ module cbx_1__1_
(
.in({ chanx_left_in[0], chanx_right_in[0], chanx_left_in[2], chanx_right_in[2], chanx_left_in[10], chanx_right_in[10], chanx_left_in[18], chanx_right_in[18] }),
.sram(mux_tree_tapbuf_size8_3_sram[0:3]),
.sram_inv(mux_tree_tapbuf_size8_3_sram_inv[0:3]),
.sram_inv(mux_top_ipin_6_undriven_sram_inv[0:3]),
.out(bottom_grid_pin_6_[0])
);
@ -333,7 +325,7 @@ module cbx_1__1_
(
.in({ chanx_left_in[1], chanx_right_in[1], chanx_left_in[3], chanx_right_in[3], chanx_left_in[5], chanx_right_in[5], chanx_left_in[13], chanx_right_in[13] }),
.sram(mux_tree_tapbuf_size8_4_sram[0:3]),
.sram_inv(mux_tree_tapbuf_size8_4_sram_inv[0:3]),
.sram_inv(mux_top_ipin_9_undriven_sram_inv[0:3]),
.out(bottom_grid_pin_9_[0])
);
@ -343,7 +335,7 @@ module cbx_1__1_
(
.in({ chanx_left_in[0], chanx_right_in[0], chanx_left_in[2], chanx_right_in[2], chanx_left_in[6], chanx_right_in[6], chanx_left_in[14], chanx_right_in[14] }),
.sram(mux_tree_tapbuf_size8_5_sram[0:3]),
.sram_inv(mux_tree_tapbuf_size8_5_sram_inv[0:3]),
.sram_inv(mux_top_ipin_10_undriven_sram_inv[0:3]),
.out(bottom_grid_pin_10_[0])
);
@ -353,7 +345,7 @@ module cbx_1__1_
(
.in({ chanx_left_in[1], chanx_right_in[1], chanx_left_in[3], chanx_right_in[3], chanx_left_in[9], chanx_right_in[9], chanx_left_in[17], chanx_right_in[17] }),
.sram(mux_tree_tapbuf_size8_6_sram[0:3]),
.sram_inv(mux_tree_tapbuf_size8_6_sram_inv[0:3]),
.sram_inv(mux_top_ipin_13_undriven_sram_inv[0:3]),
.out(bottom_grid_pin_13_[0])
);
@ -363,7 +355,7 @@ module cbx_1__1_
(
.in({ chanx_left_in[0], chanx_right_in[0], chanx_left_in[2], chanx_right_in[2], chanx_left_in[10], chanx_right_in[10], chanx_left_in[18], chanx_right_in[18] }),
.sram(mux_tree_tapbuf_size8_7_sram[0:3]),
.sram_inv(mux_tree_tapbuf_size8_7_sram_inv[0:3]),
.sram_inv(mux_top_ipin_14_undriven_sram_inv[0:3]),
.out(bottom_grid_pin_14_[0])
);
@ -374,8 +366,7 @@ module cbx_1__1_
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size10_mem_0_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size8_mem_0_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size8_0_sram[0:3]),
.mem_outb(mux_tree_tapbuf_size8_0_sram_inv[0:3])
.mem_out(mux_tree_tapbuf_size8_0_sram[0:3])
);
@ -385,8 +376,7 @@ module cbx_1__1_
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size8_mem_0_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size8_mem_1_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size8_1_sram[0:3]),
.mem_outb(mux_tree_tapbuf_size8_1_sram_inv[0:3])
.mem_out(mux_tree_tapbuf_size8_1_sram[0:3])
);
@ -396,8 +386,7 @@ module cbx_1__1_
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size10_mem_2_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size8_mem_2_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size8_2_sram[0:3]),
.mem_outb(mux_tree_tapbuf_size8_2_sram_inv[0:3])
.mem_out(mux_tree_tapbuf_size8_2_sram[0:3])
);
@ -407,8 +396,7 @@ module cbx_1__1_
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size8_mem_2_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size8_mem_3_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size8_3_sram[0:3]),
.mem_outb(mux_tree_tapbuf_size8_3_sram_inv[0:3])
.mem_out(mux_tree_tapbuf_size8_3_sram[0:3])
);
@ -418,8 +406,7 @@ module cbx_1__1_
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size10_mem_4_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size8_mem_4_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size8_4_sram[0:3]),
.mem_outb(mux_tree_tapbuf_size8_4_sram_inv[0:3])
.mem_out(mux_tree_tapbuf_size8_4_sram[0:3])
);
@ -429,8 +416,7 @@ module cbx_1__1_
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size8_mem_4_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size8_mem_5_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size8_5_sram[0:3]),
.mem_outb(mux_tree_tapbuf_size8_5_sram_inv[0:3])
.mem_out(mux_tree_tapbuf_size8_5_sram[0:3])
);
@ -440,8 +426,7 @@ module cbx_1__1_
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size10_mem_6_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size8_mem_6_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size8_6_sram[0:3]),
.mem_outb(mux_tree_tapbuf_size8_6_sram_inv[0:3])
.mem_out(mux_tree_tapbuf_size8_6_sram[0:3])
);
@ -451,8 +436,7 @@ module cbx_1__1_
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size8_mem_6_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size8_mem_7_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size8_7_sram[0:3]),
.mem_outb(mux_tree_tapbuf_size8_7_sram_inv[0:3])
.mem_out(mux_tree_tapbuf_size8_7_sram[0:3])
);

119
FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/routing/cbx_1__2_.v
View File

@ -37,24 +37,32 @@ module cbx_1__2_
output SC_OUT_TOP;
output SC_OUT_BOT;
wire [0:3] mux_bottom_ipin_0_undriven_sram_inv;
wire [0:3] mux_top_ipin_0_undriven_sram_inv;
wire [0:3] mux_top_ipin_10_undriven_sram_inv;
wire [0:3] mux_top_ipin_11_undriven_sram_inv;
wire [0:3] mux_top_ipin_12_undriven_sram_inv;
wire [0:3] mux_top_ipin_13_undriven_sram_inv;
wire [0:3] mux_top_ipin_14_undriven_sram_inv;
wire [0:3] mux_top_ipin_15_undriven_sram_inv;
wire [0:3] mux_top_ipin_1_undriven_sram_inv;
wire [0:3] mux_top_ipin_2_undriven_sram_inv;
wire [0:3] mux_top_ipin_3_undriven_sram_inv;
wire [0:3] mux_top_ipin_4_undriven_sram_inv;
wire [0:3] mux_top_ipin_5_undriven_sram_inv;
wire [0:3] mux_top_ipin_6_undriven_sram_inv;
wire [0:3] mux_top_ipin_7_undriven_sram_inv;
wire [0:3] mux_top_ipin_8_undriven_sram_inv;
wire [0:3] mux_top_ipin_9_undriven_sram_inv;
wire [0:3] mux_tree_tapbuf_size10_0_sram;
wire [0:3] mux_tree_tapbuf_size10_0_sram_inv;
wire [0:3] mux_tree_tapbuf_size10_1_sram;
wire [0:3] mux_tree_tapbuf_size10_1_sram_inv;
wire [0:3] mux_tree_tapbuf_size10_2_sram;
wire [0:3] mux_tree_tapbuf_size10_2_sram_inv;
wire [0:3] mux_tree_tapbuf_size10_3_sram;
wire [0:3] mux_tree_tapbuf_size10_3_sram_inv;
wire [0:3] mux_tree_tapbuf_size10_4_sram;
wire [0:3] mux_tree_tapbuf_size10_4_sram_inv;
wire [0:3] mux_tree_tapbuf_size10_5_sram;
wire [0:3] mux_tree_tapbuf_size10_5_sram_inv;
wire [0:3] mux_tree_tapbuf_size10_6_sram;
wire [0:3] mux_tree_tapbuf_size10_6_sram_inv;
wire [0:3] mux_tree_tapbuf_size10_7_sram;
wire [0:3] mux_tree_tapbuf_size10_7_sram_inv;
wire [0:3] mux_tree_tapbuf_size10_8_sram;
wire [0:3] mux_tree_tapbuf_size10_8_sram_inv;
wire [0:0] mux_tree_tapbuf_size10_mem_0_ccff_tail;
wire [0:0] mux_tree_tapbuf_size10_mem_1_ccff_tail;
wire [0:0] mux_tree_tapbuf_size10_mem_2_ccff_tail;
@ -64,21 +72,13 @@ module cbx_1__2_
wire [0:0] mux_tree_tapbuf_size10_mem_6_ccff_tail;
wire [0:0] mux_tree_tapbuf_size10_mem_7_ccff_tail;
wire [0:3] mux_tree_tapbuf_size8_0_sram;
wire [0:3] mux_tree_tapbuf_size8_0_sram_inv;
wire [0:3] mux_tree_tapbuf_size8_1_sram;
wire [0:3] mux_tree_tapbuf_size8_1_sram_inv;
wire [0:3] mux_tree_tapbuf_size8_2_sram;
wire [0:3] mux_tree_tapbuf_size8_2_sram_inv;
wire [0:3] mux_tree_tapbuf_size8_3_sram;
wire [0:3] mux_tree_tapbuf_size8_3_sram_inv;
wire [0:3] mux_tree_tapbuf_size8_4_sram;
wire [0:3] mux_tree_tapbuf_size8_4_sram_inv;
wire [0:3] mux_tree_tapbuf_size8_5_sram;
wire [0:3] mux_tree_tapbuf_size8_5_sram_inv;
wire [0:3] mux_tree_tapbuf_size8_6_sram;
wire [0:3] mux_tree_tapbuf_size8_6_sram_inv;
wire [0:3] mux_tree_tapbuf_size8_7_sram;
wire [0:3] mux_tree_tapbuf_size8_7_sram_inv;
wire [0:0] mux_tree_tapbuf_size8_mem_0_ccff_tail;
wire [0:0] mux_tree_tapbuf_size8_mem_1_ccff_tail;
wire [0:0] mux_tree_tapbuf_size8_mem_2_ccff_tail;
@ -137,7 +137,7 @@ module cbx_1__2_
(
.in({ chanx_left_in[0], chanx_right_in[0], chanx_left_in[2], chanx_right_in[2], chanx_left_in[4], chanx_right_in[4], chanx_left_in[10], chanx_right_in[10], chanx_left_in[16], chanx_right_in[16] }),
.sram(mux_tree_tapbuf_size10_0_sram[0:3]),
.sram_inv(mux_tree_tapbuf_size10_0_sram_inv[0:3]),
.sram_inv(mux_bottom_ipin_0_undriven_sram_inv[0:3]),
.out(top_grid_pin_0_[0])
);
@ -147,7 +147,7 @@ module cbx_1__2_
(
.in({ chanx_left_in[1], chanx_right_in[1], chanx_left_in[3], chanx_right_in[3], chanx_left_in[5], chanx_right_in[5], chanx_left_in[11], chanx_right_in[11], chanx_left_in[17], chanx_right_in[17] }),
.sram(mux_tree_tapbuf_size10_1_sram[0:3]),
.sram_inv(mux_tree_tapbuf_size10_1_sram_inv[0:3]),
.sram_inv(mux_top_ipin_0_undriven_sram_inv[0:3]),
.out(bottom_grid_pin_0_[0])
);
@ -157,7 +157,7 @@ module cbx_1__2_
(
.in({ chanx_left_in[0], chanx_right_in[0], chanx_left_in[2], chanx_right_in[2], chanx_left_in[4], chanx_right_in[4], chanx_left_in[8], chanx_right_in[8], chanx_left_in[14], chanx_right_in[14] }),
.sram(mux_tree_tapbuf_size10_2_sram[0:3]),
.sram_inv(mux_tree_tapbuf_size10_2_sram_inv[0:3]),
.sram_inv(mux_top_ipin_3_undriven_sram_inv[0:3]),
.out(bottom_grid_pin_3_[0])
);
@ -167,7 +167,7 @@ module cbx_1__2_
(
.in({ chanx_left_in[1], chanx_right_in[1], chanx_left_in[3], chanx_right_in[3], chanx_left_in[5], chanx_right_in[5], chanx_left_in[9], chanx_right_in[9], chanx_left_in[15], chanx_right_in[15] }),
.sram(mux_tree_tapbuf_size10_3_sram[0:3]),
.sram_inv(mux_tree_tapbuf_size10_3_sram_inv[0:3]),
.sram_inv(mux_top_ipin_4_undriven_sram_inv[0:3]),
.out(bottom_grid_pin_4_[0])
);
@ -177,7 +177,7 @@ module cbx_1__2_
(
.in({ chanx_left_in[0], chanx_right_in[0], chanx_left_in[2], chanx_right_in[2], chanx_left_in[8], chanx_right_in[8], chanx_left_in[12], chanx_right_in[12], chanx_left_in[18], chanx_right_in[18] }),
.sram(mux_tree_tapbuf_size10_4_sram[0:3]),
.sram_inv(mux_tree_tapbuf_size10_4_sram_inv[0:3]),
.sram_inv(mux_top_ipin_7_undriven_sram_inv[0:3]),
.out(bottom_grid_pin_7_[0])
);
@ -187,7 +187,7 @@ module cbx_1__2_
(
.in({ chanx_left_in[1], chanx_right_in[1], chanx_left_in[3], chanx_right_in[3], chanx_left_in[9], chanx_right_in[9], chanx_left_in[13], chanx_right_in[13], chanx_left_in[19], chanx_right_in[19] }),
.sram(mux_tree_tapbuf_size10_5_sram[0:3]),
.sram_inv(mux_tree_tapbuf_size10_5_sram_inv[0:3]),
.sram_inv(mux_top_ipin_8_undriven_sram_inv[0:3]),
.out(bottom_grid_pin_8_[0])
);
@ -197,7 +197,7 @@ module cbx_1__2_
(
.in({ chanx_left_in[0], chanx_right_in[0], chanx_left_in[2], chanx_right_in[2], chanx_left_in[6], chanx_right_in[6], chanx_left_in[12], chanx_right_in[12], chanx_left_in[16], chanx_right_in[16] }),
.sram(mux_tree_tapbuf_size10_6_sram[0:3]),
.sram_inv(mux_tree_tapbuf_size10_6_sram_inv[0:3]),
.sram_inv(mux_top_ipin_11_undriven_sram_inv[0:3]),
.out(bottom_grid_pin_11_[0])
);
@ -207,7 +207,7 @@ module cbx_1__2_
(
.in({ chanx_left_in[1], chanx_right_in[1], chanx_left_in[3], chanx_right_in[3], chanx_left_in[7], chanx_right_in[7], chanx_left_in[13], chanx_right_in[13], chanx_left_in[17], chanx_right_in[17] }),
.sram(mux_tree_tapbuf_size10_7_sram[0:3]),
.sram_inv(mux_tree_tapbuf_size10_7_sram_inv[0:3]),
.sram_inv(mux_top_ipin_12_undriven_sram_inv[0:3]),
.out(bottom_grid_pin_12_[0])
);
@ -217,7 +217,7 @@ module cbx_1__2_
(
.in({ chanx_left_in[0], chanx_right_in[0], chanx_left_in[2], chanx_right_in[2], chanx_left_in[4], chanx_right_in[4], chanx_left_in[10], chanx_right_in[10], chanx_left_in[16], chanx_right_in[16] }),
.sram(mux_tree_tapbuf_size10_8_sram[0:3]),
.sram_inv(mux_tree_tapbuf_size10_8_sram_inv[0:3]),
.sram_inv(mux_top_ipin_15_undriven_sram_inv[0:3]),
.out(bottom_grid_pin_15_[0])
);
@ -228,8 +228,7 @@ module cbx_1__2_
.prog_clk(prog_clk[0]),
.ccff_head(ccff_head[0]),
.ccff_tail(mux_tree_tapbuf_size10_mem_0_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size10_0_sram[0:3]),
.mem_outb(mux_tree_tapbuf_size10_0_sram_inv[0:3])
.mem_out(mux_tree_tapbuf_size10_0_sram[0:3])
);
@ -239,8 +238,7 @@ module cbx_1__2_
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size10_mem_0_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size10_mem_1_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size10_1_sram[0:3]),
.mem_outb(mux_tree_tapbuf_size10_1_sram_inv[0:3])
.mem_out(mux_tree_tapbuf_size10_1_sram[0:3])
);
@ -250,8 +248,7 @@ module cbx_1__2_
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size8_mem_1_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size10_mem_2_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size10_2_sram[0:3]),
.mem_outb(mux_tree_tapbuf_size10_2_sram_inv[0:3])
.mem_out(mux_tree_tapbuf_size10_2_sram[0:3])
);
@ -261,8 +258,7 @@ module cbx_1__2_
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size10_mem_2_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size10_mem_3_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size10_3_sram[0:3]),
.mem_outb(mux_tree_tapbuf_size10_3_sram_inv[0:3])
.mem_out(mux_tree_tapbuf_size10_3_sram[0:3])
);
@ -272,8 +268,7 @@ module cbx_1__2_
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size8_mem_3_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size10_mem_4_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size10_4_sram[0:3]),
.mem_outb(mux_tree_tapbuf_size10_4_sram_inv[0:3])
.mem_out(mux_tree_tapbuf_size10_4_sram[0:3])
);
@ -283,8 +278,7 @@ module cbx_1__2_
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size10_mem_4_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size10_mem_5_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size10_5_sram[0:3]),
.mem_outb(mux_tree_tapbuf_size10_5_sram_inv[0:3])
.mem_out(mux_tree_tapbuf_size10_5_sram[0:3])
);
@ -294,8 +288,7 @@ module cbx_1__2_
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size8_mem_5_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size10_mem_6_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size10_6_sram[0:3]),
.mem_outb(mux_tree_tapbuf_size10_6_sram_inv[0:3])
.mem_out(mux_tree_tapbuf_size10_6_sram[0:3])
);
@ -305,8 +298,7 @@ module cbx_1__2_
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size10_mem_6_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size10_mem_7_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size10_7_sram[0:3]),
.mem_outb(mux_tree_tapbuf_size10_7_sram_inv[0:3])
.mem_out(mux_tree_tapbuf_size10_7_sram[0:3])
);
@ -316,8 +308,7 @@ module cbx_1__2_
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size8_mem_7_ccff_tail[0]),
.ccff_tail(ccff_tail_mid),
.mem_out(mux_tree_tapbuf_size10_8_sram[0:3]),
.mem_outb(mux_tree_tapbuf_size10_8_sram_inv[0:3])
.mem_out(mux_tree_tapbuf_size10_8_sram[0:3])
);
@ -326,7 +317,7 @@ module cbx_1__2_
(
.in({ chanx_left_in[0], chanx_right_in[0], chanx_left_in[2], chanx_right_in[2], chanx_left_in[6], chanx_right_in[6], chanx_left_in[14], chanx_right_in[14] }),
.sram(mux_tree_tapbuf_size8_0_sram[0:3]),
.sram_inv(mux_tree_tapbuf_size8_0_sram_inv[0:3]),
.sram_inv(mux_top_ipin_1_undriven_sram_inv[0:3]),
.out(bottom_grid_pin_1_[0])
);
@ -336,7 +327,7 @@ module cbx_1__2_
(
.in({ chanx_left_in[1], chanx_right_in[1], chanx_left_in[3], chanx_right_in[3], chanx_left_in[7], chanx_right_in[7], chanx_left_in[15], chanx_right_in[15] }),
.sram(mux_tree_tapbuf_size8_1_sram[0:3]),
.sram_inv(mux_tree_tapbuf_size8_1_sram_inv[0:3]),
.sram_inv(mux_top_ipin_2_undriven_sram_inv[0:3]),
.out(bottom_grid_pin_2_[0])
);
@ -346,7 +337,7 @@ module cbx_1__2_
(
.in({ chanx_left_in[0], chanx_right_in[0], chanx_left_in[2], chanx_right_in[2], chanx_left_in[10], chanx_right_in[10], chanx_left_in[18], chanx_right_in[18] }),
.sram(mux_tree_tapbuf_size8_2_sram[0:3]),
.sram_inv(mux_tree_tapbuf_size8_2_sram_inv[0:3]),
.sram_inv(mux_top_ipin_5_undriven_sram_inv[0:3]),
.out(bottom_grid_pin_5_[0])
);
@ -356,7 +347,7 @@ module cbx_1__2_
(
.in({ chanx_left_in[1], chanx_right_in[1], chanx_left_in[3], chanx_right_in[3], chanx_left_in[11], chanx_right_in[11], chanx_left_in[19], chanx_right_in[19] }),
.sram(mux_tree_tapbuf_size8_3_sram[0:3]),
.sram_inv(mux_tree_tapbuf_size8_3_sram_inv[0:3]),
.sram_inv(mux_top_ipin_6_undriven_sram_inv[0:3]),
.out(bottom_grid_pin_6_[0])
);
@ -366,7 +357,7 @@ module cbx_1__2_
(
.in({ chanx_left_in[0], chanx_right_in[0], chanx_left_in[2], chanx_right_in[2], chanx_left_in[6], chanx_right_in[6], chanx_left_in[14], chanx_right_in[14] }),
.sram(mux_tree_tapbuf_size8_4_sram[0:3]),
.sram_inv(mux_tree_tapbuf_size8_4_sram_inv[0:3]),
.sram_inv(mux_top_ipin_9_undriven_sram_inv[0:3]),
.out(bottom_grid_pin_9_[0])
);
@ -376,7 +367,7 @@ module cbx_1__2_
(
.in({ chanx_left_in[1], chanx_right_in[1], chanx_left_in[3], chanx_right_in[3], chanx_left_in[7], chanx_right_in[7], chanx_left_in[15], chanx_right_in[15] }),
.sram(mux_tree_tapbuf_size8_5_sram[0:3]),
.sram_inv(mux_tree_tapbuf_size8_5_sram_inv[0:3]),
.sram_inv(mux_top_ipin_10_undriven_sram_inv[0:3]),
.out(bottom_grid_pin_10_[0])
);
@ -386,7 +377,7 @@ module cbx_1__2_
(
.in({ chanx_left_in[0], chanx_right_in[0], chanx_left_in[2], chanx_right_in[2], chanx_left_in[10], chanx_right_in[10], chanx_left_in[18], chanx_right_in[18] }),
.sram(mux_tree_tapbuf_size8_6_sram[0:3]),
.sram_inv(mux_tree_tapbuf_size8_6_sram_inv[0:3]),
.sram_inv(mux_top_ipin_13_undriven_sram_inv[0:3]),
.out(bottom_grid_pin_13_[0])
);
@ -396,7 +387,7 @@ module cbx_1__2_
(
.in({ chanx_left_in[1], chanx_right_in[1], chanx_left_in[3], chanx_right_in[3], chanx_left_in[11], chanx_right_in[11], chanx_left_in[19], chanx_right_in[19] }),
.sram(mux_tree_tapbuf_size8_7_sram[0:3]),
.sram_inv(mux_tree_tapbuf_size8_7_sram_inv[0:3]),
.sram_inv(mux_top_ipin_14_undriven_sram_inv[0:3]),
.out(bottom_grid_pin_14_[0])
);
@ -407,8 +398,7 @@ module cbx_1__2_
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size10_mem_1_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size8_mem_0_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size8_0_sram[0:3]),
.mem_outb(mux_tree_tapbuf_size8_0_sram_inv[0:3])
.mem_out(mux_tree_tapbuf_size8_0_sram[0:3])
);
@ -418,8 +408,7 @@ module cbx_1__2_
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size8_mem_0_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size8_mem_1_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size8_1_sram[0:3]),
.mem_outb(mux_tree_tapbuf_size8_1_sram_inv[0:3])
.mem_out(mux_tree_tapbuf_size8_1_sram[0:3])
);
@ -429,8 +418,7 @@ module cbx_1__2_
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size10_mem_3_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size8_mem_2_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size8_2_sram[0:3]),
.mem_outb(mux_tree_tapbuf_size8_2_sram_inv[0:3])
.mem_out(mux_tree_tapbuf_size8_2_sram[0:3])
);
@ -440,8 +428,7 @@ module cbx_1__2_
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size8_mem_2_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size8_mem_3_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size8_3_sram[0:3]),
.mem_outb(mux_tree_tapbuf_size8_3_sram_inv[0:3])
.mem_out(mux_tree_tapbuf_size8_3_sram[0:3])
);
@ -451,8 +438,7 @@ module cbx_1__2_
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size10_mem_5_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size8_mem_4_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size8_4_sram[0:3]),
.mem_outb(mux_tree_tapbuf_size8_4_sram_inv[0:3])
.mem_out(mux_tree_tapbuf_size8_4_sram[0:3])
);
@ -462,8 +448,7 @@ module cbx_1__2_
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size8_mem_4_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size8_mem_5_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size8_5_sram[0:3]),
.mem_outb(mux_tree_tapbuf_size8_5_sram_inv[0:3])
.mem_out(mux_tree_tapbuf_size8_5_sram[0:3])
);
@ -473,8 +458,7 @@ module cbx_1__2_
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size10_mem_7_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size8_mem_6_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size8_6_sram[0:3]),
.mem_outb(mux_tree_tapbuf_size8_6_sram_inv[0:3])
.mem_out(mux_tree_tapbuf_size8_6_sram[0:3])
);
@ -484,8 +468,7 @@ module cbx_1__2_
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size8_mem_6_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size8_mem_7_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size8_7_sram[0:3]),
.mem_outb(mux_tree_tapbuf_size8_7_sram_inv[0:3])
.mem_out(mux_tree_tapbuf_size8_7_sram[0:3])
);

7
FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/routing/cby_0__1_.v
View File

@ -17,8 +17,8 @@ module cby_0__1_
output [0:0] right_width_0_height_0__pin_1_upper;
output [0:0] right_width_0_height_0__pin_1_lower;
wire [0:3] mux_right_ipin_0_undriven_sram_inv;
wire [0:3] mux_tree_tapbuf_size10_0_sram;
wire [0:3] mux_tree_tapbuf_size10_0_sram_inv;
wire ccff_tail_mid;
assign chany_top_out[0] = chany_bottom_in[0];
assign chany_top_out[1] = chany_bottom_in[1];
@ -67,7 +67,7 @@ module cby_0__1_
(
.in({ chany_bottom_in[0], chany_top_in[0], chany_bottom_in[2], chany_top_in[2], chany_bottom_in[4], chany_top_in[4], chany_bottom_in[10], chany_top_in[10], chany_bottom_in[16], chany_top_in[16] }),
.sram(mux_tree_tapbuf_size10_0_sram[0:3]),
.sram_inv(mux_tree_tapbuf_size10_0_sram_inv[0:3]),
.sram_inv(mux_right_ipin_0_undriven_sram_inv[0:3]),
.out(left_grid_pin_0_[0])
);
@ -78,8 +78,7 @@ module cby_0__1_
.prog_clk(prog_clk[0]),
.ccff_head(ccff_head[0]),
.ccff_tail(ccff_tail_mid),
.mem_out(mux_tree_tapbuf_size10_0_sram[0:3]),
.mem_outb(mux_tree_tapbuf_size10_0_sram_inv[0:3])
.mem_out(mux_tree_tapbuf_size10_0_sram[0:3])
);

112
FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/routing/cby_1__1_.v
View File

@ -26,22 +26,30 @@ module cby_1__1_
output [0:0] left_grid_pin_31_;
output [0:0] ccff_tail;
wire [0:3] mux_right_ipin_0_undriven_sram_inv;
wire [0:3] mux_right_ipin_10_undriven_sram_inv;
wire [0:3] mux_right_ipin_11_undriven_sram_inv;
wire [0:3] mux_right_ipin_12_undriven_sram_inv;
wire [0:3] mux_right_ipin_13_undriven_sram_inv;
wire [0:3] mux_right_ipin_14_undriven_sram_inv;
wire [0:3] mux_right_ipin_15_undriven_sram_inv;
wire [0:3] mux_right_ipin_1_undriven_sram_inv;
wire [0:3] mux_right_ipin_2_undriven_sram_inv;
wire [0:3] mux_right_ipin_3_undriven_sram_inv;
wire [0:3] mux_right_ipin_4_undriven_sram_inv;
wire [0:3] mux_right_ipin_5_undriven_sram_inv;
wire [0:3] mux_right_ipin_6_undriven_sram_inv;
wire [0:3] mux_right_ipin_7_undriven_sram_inv;
wire [0:3] mux_right_ipin_8_undriven_sram_inv;
wire [0:3] mux_right_ipin_9_undriven_sram_inv;
wire [0:3] mux_tree_tapbuf_size10_0_sram;
wire [0:3] mux_tree_tapbuf_size10_0_sram_inv;
wire [0:3] mux_tree_tapbuf_size10_1_sram;
wire [0:3] mux_tree_tapbuf_size10_1_sram_inv;
wire [0:3] mux_tree_tapbuf_size10_2_sram;
wire [0:3] mux_tree_tapbuf_size10_2_sram_inv;
wire [0:3] mux_tree_tapbuf_size10_3_sram;
wire [0:3] mux_tree_tapbuf_size10_3_sram_inv;
wire [0:3] mux_tree_tapbuf_size10_4_sram;
wire [0:3] mux_tree_tapbuf_size10_4_sram_inv;
wire [0:3] mux_tree_tapbuf_size10_5_sram;
wire [0:3] mux_tree_tapbuf_size10_5_sram_inv;
wire [0:3] mux_tree_tapbuf_size10_6_sram;
wire [0:3] mux_tree_tapbuf_size10_6_sram_inv;
wire [0:3] mux_tree_tapbuf_size10_7_sram;
wire [0:3] mux_tree_tapbuf_size10_7_sram_inv;
wire [0:0] mux_tree_tapbuf_size10_mem_0_ccff_tail;
wire [0:0] mux_tree_tapbuf_size10_mem_1_ccff_tail;
wire [0:0] mux_tree_tapbuf_size10_mem_2_ccff_tail;
@ -50,21 +58,13 @@ module cby_1__1_
wire [0:0] mux_tree_tapbuf_size10_mem_5_ccff_tail;
wire [0:0] mux_tree_tapbuf_size10_mem_6_ccff_tail;
wire [0:3] mux_tree_tapbuf_size8_0_sram;
wire [0:3] mux_tree_tapbuf_size8_0_sram_inv;
wire [0:3] mux_tree_tapbuf_size8_1_sram;
wire [0:3] mux_tree_tapbuf_size8_1_sram_inv;
wire [0:3] mux_tree_tapbuf_size8_2_sram;
wire [0:3] mux_tree_tapbuf_size8_2_sram_inv;
wire [0:3] mux_tree_tapbuf_size8_3_sram;
wire [0:3] mux_tree_tapbuf_size8_3_sram_inv;
wire [0:3] mux_tree_tapbuf_size8_4_sram;
wire [0:3] mux_tree_tapbuf_size8_4_sram_inv;
wire [0:3] mux_tree_tapbuf_size8_5_sram;
wire [0:3] mux_tree_tapbuf_size8_5_sram_inv;
wire [0:3] mux_tree_tapbuf_size8_6_sram;
wire [0:3] mux_tree_tapbuf_size8_6_sram_inv;
wire [0:3] mux_tree_tapbuf_size8_7_sram;
wire [0:3] mux_tree_tapbuf_size8_7_sram_inv;
wire [0:0] mux_tree_tapbuf_size8_mem_0_ccff_tail;
wire [0:0] mux_tree_tapbuf_size8_mem_1_ccff_tail;
wire [0:0] mux_tree_tapbuf_size8_mem_2_ccff_tail;
@ -119,7 +119,7 @@ module cby_1__1_
(
.in({ chany_bottom_in[0], chany_top_in[0], chany_bottom_in[2], chany_top_in[2], chany_bottom_in[4], chany_top_in[4], chany_bottom_in[10], chany_top_in[10], chany_bottom_in[16], chany_top_in[16] }),
.sram(mux_tree_tapbuf_size10_0_sram[0:3]),
.sram_inv(mux_tree_tapbuf_size10_0_sram_inv[0:3]),
.sram_inv(mux_right_ipin_0_undriven_sram_inv[0:3]),
.out(left_grid_pin_16_[0])
);
@ -129,7 +129,7 @@ module cby_1__1_
(
.in({ chany_bottom_in[1], chany_top_in[1], chany_bottom_in[3], chany_top_in[3], chany_bottom_in[7], chany_top_in[7], chany_bottom_in[13], chany_top_in[13], chany_bottom_in[19], chany_top_in[19] }),
.sram(mux_tree_tapbuf_size10_1_sram[0:3]),
.sram_inv(mux_tree_tapbuf_size10_1_sram_inv[0:3]),
.sram_inv(mux_right_ipin_3_undriven_sram_inv[0:3]),
.out(left_grid_pin_19_[0])
);
@ -139,7 +139,7 @@ module cby_1__1_
(
.in({ chany_bottom_in[0], chany_top_in[0], chany_bottom_in[2], chany_top_in[2], chany_bottom_in[4], chany_top_in[4], chany_bottom_in[8], chany_top_in[8], chany_bottom_in[14], chany_top_in[14] }),
.sram(mux_tree_tapbuf_size10_2_sram[0:3]),
.sram_inv(mux_tree_tapbuf_size10_2_sram_inv[0:3]),
.sram_inv(mux_right_ipin_4_undriven_sram_inv[0:3]),
.out(left_grid_pin_20_[0])
);
@ -149,7 +149,7 @@ module cby_1__1_
(
.in({ chany_bottom_in[1], chany_top_in[1], chany_bottom_in[3], chany_top_in[3], chany_bottom_in[7], chany_top_in[7], chany_bottom_in[11], chany_top_in[11], chany_bottom_in[17], chany_top_in[17] }),
.sram(mux_tree_tapbuf_size10_3_sram[0:3]),
.sram_inv(mux_tree_tapbuf_size10_3_sram_inv[0:3]),
.sram_inv(mux_right_ipin_7_undriven_sram_inv[0:3]),
.out(left_grid_pin_23_[0])
);
@ -159,7 +159,7 @@ module cby_1__1_
(
.in({ chany_bottom_in[0], chany_top_in[0], chany_bottom_in[2], chany_top_in[2], chany_bottom_in[8], chany_top_in[8], chany_bottom_in[12], chany_top_in[12], chany_bottom_in[18], chany_top_in[18] }),
.sram(mux_tree_tapbuf_size10_4_sram[0:3]),
.sram_inv(mux_tree_tapbuf_size10_4_sram_inv[0:3]),
.sram_inv(mux_right_ipin_8_undriven_sram_inv[0:3]),
.out(left_grid_pin_24_[0])
);
@ -169,7 +169,7 @@ module cby_1__1_
(
.in({ chany_bottom_in[1], chany_top_in[1], chany_bottom_in[3], chany_top_in[3], chany_bottom_in[5], chany_top_in[5], chany_bottom_in[11], chany_top_in[11], chany_bottom_in[15], chany_top_in[15] }),
.sram(mux_tree_tapbuf_size10_5_sram[0:3]),
.sram_inv(mux_tree_tapbuf_size10_5_sram_inv[0:3]),
.sram_inv(mux_right_ipin_11_undriven_sram_inv[0:3]),
.out(left_grid_pin_27_[0])
);
@ -179,7 +179,7 @@ module cby_1__1_
(
.in({ chany_bottom_in[0], chany_top_in[0], chany_bottom_in[2], chany_top_in[2], chany_bottom_in[6], chany_top_in[6], chany_bottom_in[12], chany_top_in[12], chany_bottom_in[16], chany_top_in[16] }),
.sram(mux_tree_tapbuf_size10_6_sram[0:3]),
.sram_inv(mux_tree_tapbuf_size10_6_sram_inv[0:3]),
.sram_inv(mux_right_ipin_12_undriven_sram_inv[0:3]),
.out(left_grid_pin_28_[0])
);
@ -189,7 +189,7 @@ module cby_1__1_
(
.in({ chany_bottom_in[1], chany_top_in[1], chany_bottom_in[3], chany_top_in[3], chany_bottom_in[9], chany_top_in[9], chany_bottom_in[15], chany_top_in[15], chany_bottom_in[19], chany_top_in[19] }),
.sram(mux_tree_tapbuf_size10_7_sram[0:3]),
.sram_inv(mux_tree_tapbuf_size10_7_sram_inv[0:3]),
.sram_inv(mux_right_ipin_15_undriven_sram_inv[0:3]),
.out(left_grid_pin_31_[0])
);
@ -200,8 +200,7 @@ module cby_1__1_
.prog_clk(prog_clk[0]),
.ccff_head(ccff_head[0]),
.ccff_tail(mux_tree_tapbuf_size10_mem_0_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size10_0_sram[0:3]),
.mem_outb(mux_tree_tapbuf_size10_0_sram_inv[0:3])
.mem_out(mux_tree_tapbuf_size10_0_sram[0:3])
);
@ -211,8 +210,7 @@ module cby_1__1_
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size8_mem_1_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size10_mem_1_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size10_1_sram[0:3]),
.mem_outb(mux_tree_tapbuf_size10_1_sram_inv[0:3])
.mem_out(mux_tree_tapbuf_size10_1_sram[0:3])
);
@ -222,8 +220,7 @@ module cby_1__1_
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size10_mem_1_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size10_mem_2_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size10_2_sram[0:3]),
.mem_outb(mux_tree_tapbuf_size10_2_sram_inv[0:3])
.mem_out(mux_tree_tapbuf_size10_2_sram[0:3])
);
@ -233,8 +230,7 @@ module cby_1__1_
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size8_mem_3_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size10_mem_3_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size10_3_sram[0:3]),
.mem_outb(mux_tree_tapbuf_size10_3_sram_inv[0:3])
.mem_out(mux_tree_tapbuf_size10_3_sram[0:3])
);
@ -244,8 +240,7 @@ module cby_1__1_
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size10_mem_3_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size10_mem_4_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size10_4_sram[0:3]),
.mem_outb(mux_tree_tapbuf_size10_4_sram_inv[0:3])
.mem_out(mux_tree_tapbuf_size10_4_sram[0:3])
);
@ -255,8 +250,7 @@ module cby_1__1_
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size8_mem_5_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size10_mem_5_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size10_5_sram[0:3]),
.mem_outb(mux_tree_tapbuf_size10_5_sram_inv[0:3])
.mem_out(mux_tree_tapbuf_size10_5_sram[0:3])
);
@ -266,8 +260,7 @@ module cby_1__1_
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size10_mem_5_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size10_mem_6_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size10_6_sram[0:3]),
.mem_outb(mux_tree_tapbuf_size10_6_sram_inv[0:3])
.mem_out(mux_tree_tapbuf_size10_6_sram[0:3])
);
@ -277,8 +270,7 @@ module cby_1__1_
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size8_mem_7_ccff_tail[0]),
.ccff_tail(ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size10_7_sram[0:3]),
.mem_outb(mux_tree_tapbuf_size10_7_sram_inv[0:3])
.mem_out(mux_tree_tapbuf_size10_7_sram[0:3])
);
@ -287,7 +279,7 @@ module cby_1__1_
(
.in({ chany_bottom_in[1], chany_top_in[1], chany_bottom_in[3], chany_top_in[3], chany_bottom_in[5], chany_top_in[5], chany_bottom_in[13], chany_top_in[13] }),
.sram(mux_tree_tapbuf_size8_0_sram[0:3]),
.sram_inv(mux_tree_tapbuf_size8_0_sram_inv[0:3]),
.sram_inv(mux_right_ipin_1_undriven_sram_inv[0:3]),
.out(left_grid_pin_17_[0])
);
@ -297,7 +289,7 @@ module cby_1__1_
(
.in({ chany_bottom_in[0], chany_top_in[0], chany_bottom_in[2], chany_top_in[2], chany_bottom_in[6], chany_top_in[6], chany_bottom_in[14], chany_top_in[14] }),
.sram(mux_tree_tapbuf_size8_1_sram[0:3]),
.sram_inv(mux_tree_tapbuf_size8_1_sram_inv[0:3]),
.sram_inv(mux_right_ipin_2_undriven_sram_inv[0:3]),
.out(left_grid_pin_18_[0])
);
@ -307,7 +299,7 @@ module cby_1__1_
(
.in({ chany_bottom_in[1], chany_top_in[1], chany_bottom_in[3], chany_top_in[3], chany_bottom_in[9], chany_top_in[9], chany_bottom_in[17], chany_top_in[17] }),
.sram(mux_tree_tapbuf_size8_2_sram[0:3]),
.sram_inv(mux_tree_tapbuf_size8_2_sram_inv[0:3]),
.sram_inv(mux_right_ipin_5_undriven_sram_inv[0:3]),
.out(left_grid_pin_21_[0])
);
@ -317,7 +309,7 @@ module cby_1__1_
(
.in({ chany_bottom_in[0], chany_top_in[0], chany_bottom_in[2], chany_top_in[2], chany_bottom_in[10], chany_top_in[10], chany_bottom_in[18], chany_top_in[18] }),
.sram(mux_tree_tapbuf_size8_3_sram[0:3]),
.sram_inv(mux_tree_tapbuf_size8_3_sram_inv[0:3]),
.sram_inv(mux_right_ipin_6_undriven_sram_inv[0:3]),
.out(left_grid_pin_22_[0])
);
@ -327,7 +319,7 @@ module cby_1__1_
(
.in({ chany_bottom_in[1], chany_top_in[1], chany_bottom_in[3], chany_top_in[3], chany_bottom_in[5], chany_top_in[5], chany_bottom_in[13], chany_top_in[13] }),
.sram(mux_tree_tapbuf_size8_4_sram[0:3]),
.sram_inv(mux_tree_tapbuf_size8_4_sram_inv[0:3]),
.sram_inv(mux_right_ipin_9_undriven_sram_inv[0:3]),
.out(left_grid_pin_25_[0])
);
@ -337,7 +329,7 @@ module cby_1__1_
(
.in({ chany_bottom_in[0], chany_top_in[0], chany_bottom_in[2], chany_top_in[2], chany_bottom_in[6], chany_top_in[6], chany_bottom_in[14], chany_top_in[14] }),
.sram(mux_tree_tapbuf_size8_5_sram[0:3]),
.sram_inv(mux_tree_tapbuf_size8_5_sram_inv[0:3]),
.sram_inv(mux_right_ipin_10_undriven_sram_inv[0:3]),
.out(left_grid_pin_26_[0])
);
@ -347,7 +339,7 @@ module cby_1__1_
(
.in({ chany_bottom_in[1], chany_top_in[1], chany_bottom_in[3], chany_top_in[3], chany_bottom_in[9], chany_top_in[9], chany_bottom_in[17], chany_top_in[17] }),
.sram(mux_tree_tapbuf_size8_6_sram[0:3]),
.sram_inv(mux_tree_tapbuf_size8_6_sram_inv[0:3]),
.sram_inv(mux_right_ipin_13_undriven_sram_inv[0:3]),
.out(left_grid_pin_29_[0])
);
@ -357,7 +349,7 @@ module cby_1__1_
(
.in({ chany_bottom_in[0], chany_top_in[0], chany_bottom_in[2], chany_top_in[2], chany_bottom_in[10], chany_top_in[10], chany_bottom_in[18], chany_top_in[18] }),
.sram(mux_tree_tapbuf_size8_7_sram[0:3]),
.sram_inv(mux_tree_tapbuf_size8_7_sram_inv[0:3]),
.sram_inv(mux_right_ipin_14_undriven_sram_inv[0:3]),
.out(left_grid_pin_30_[0])
);
@ -368,8 +360,7 @@ module cby_1__1_
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size10_mem_0_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size8_mem_0_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size8_0_sram[0:3]),
.mem_outb(mux_tree_tapbuf_size8_0_sram_inv[0:3])
.mem_out(mux_tree_tapbuf_size8_0_sram[0:3])
);
@ -379,8 +370,7 @@ module cby_1__1_
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size8_mem_0_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size8_mem_1_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size8_1_sram[0:3]),
.mem_outb(mux_tree_tapbuf_size8_1_sram_inv[0:3])
.mem_out(mux_tree_tapbuf_size8_1_sram[0:3])
);
@ -390,8 +380,7 @@ module cby_1__1_
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size10_mem_2_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size8_mem_2_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size8_2_sram[0:3]),
.mem_outb(mux_tree_tapbuf_size8_2_sram_inv[0:3])
.mem_out(mux_tree_tapbuf_size8_2_sram[0:3])
);
@ -401,8 +390,7 @@ module cby_1__1_
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size8_mem_2_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size8_mem_3_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size8_3_sram[0:3]),
.mem_outb(mux_tree_tapbuf_size8_3_sram_inv[0:3])
.mem_out(mux_tree_tapbuf_size8_3_sram[0:3])
);
@ -412,8 +400,7 @@ module cby_1__1_
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size10_mem_4_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size8_mem_4_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size8_4_sram[0:3]),
.mem_outb(mux_tree_tapbuf_size8_4_sram_inv[0:3])
.mem_out(mux_tree_tapbuf_size8_4_sram[0:3])
);
@ -423,8 +410,7 @@ module cby_1__1_
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size8_mem_4_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size8_mem_5_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size8_5_sram[0:3]),
.mem_outb(mux_tree_tapbuf_size8_5_sram_inv[0:3])
.mem_out(mux_tree_tapbuf_size8_5_sram[0:3])
);
@ -434,8 +420,7 @@ module cby_1__1_
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size10_mem_6_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size8_mem_6_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size8_6_sram[0:3]),
.mem_outb(mux_tree_tapbuf_size8_6_sram_inv[0:3])
.mem_out(mux_tree_tapbuf_size8_6_sram[0:3])
);
@ -445,8 +430,7 @@ module cby_1__1_
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size8_mem_6_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size8_mem_7_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size8_7_sram[0:3]),
.mem_outb(mux_tree_tapbuf_size8_7_sram_inv[0:3])
.mem_out(mux_tree_tapbuf_size8_7_sram[0:3])
);

119
FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/routing/cby_2__1_.v
View File

@ -33,24 +33,32 @@ module cby_2__1_
output [0:0] left_width_0_height_0__pin_1_upper;
output [0:0] left_width_0_height_0__pin_1_lower;
wire [0:3] mux_left_ipin_0_undriven_sram_inv;
wire [0:3] mux_right_ipin_0_undriven_sram_inv;
wire [0:3] mux_right_ipin_10_undriven_sram_inv;
wire [0:3] mux_right_ipin_11_undriven_sram_inv;
wire [0:3] mux_right_ipin_12_undriven_sram_inv;
wire [0:3] mux_right_ipin_13_undriven_sram_inv;
wire [0:3] mux_right_ipin_14_undriven_sram_inv;
wire [0:3] mux_right_ipin_15_undriven_sram_inv;
wire [0:3] mux_right_ipin_1_undriven_sram_inv;
wire [0:3] mux_right_ipin_2_undriven_sram_inv;
wire [0:3] mux_right_ipin_3_undriven_sram_inv;
wire [0:3] mux_right_ipin_4_undriven_sram_inv;
wire [0:3] mux_right_ipin_5_undriven_sram_inv;
wire [0:3] mux_right_ipin_6_undriven_sram_inv;
wire [0:3] mux_right_ipin_7_undriven_sram_inv;
wire [0:3] mux_right_ipin_8_undriven_sram_inv;
wire [0:3] mux_right_ipin_9_undriven_sram_inv;
wire [0:3] mux_tree_tapbuf_size10_0_sram;
wire [0:3] mux_tree_tapbuf_size10_0_sram_inv;
wire [0:3] mux_tree_tapbuf_size10_1_sram;
wire [0:3] mux_tree_tapbuf_size10_1_sram_inv;
wire [0:3] mux_tree_tapbuf_size10_2_sram;
wire [0:3] mux_tree_tapbuf_size10_2_sram_inv;
wire [0:3] mux_tree_tapbuf_size10_3_sram;
wire [0:3] mux_tree_tapbuf_size10_3_sram_inv;
wire [0:3] mux_tree_tapbuf_size10_4_sram;
wire [0:3] mux_tree_tapbuf_size10_4_sram_inv;
wire [0:3] mux_tree_tapbuf_size10_5_sram;
wire [0:3] mux_tree_tapbuf_size10_5_sram_inv;
wire [0:3] mux_tree_tapbuf_size10_6_sram;
wire [0:3] mux_tree_tapbuf_size10_6_sram_inv;
wire [0:3] mux_tree_tapbuf_size10_7_sram;
wire [0:3] mux_tree_tapbuf_size10_7_sram_inv;
wire [0:3] mux_tree_tapbuf_size10_8_sram;
wire [0:3] mux_tree_tapbuf_size10_8_sram_inv;
wire [0:0] mux_tree_tapbuf_size10_mem_0_ccff_tail;
wire [0:0] mux_tree_tapbuf_size10_mem_1_ccff_tail;
wire [0:0] mux_tree_tapbuf_size10_mem_2_ccff_tail;
@ -60,21 +68,13 @@ module cby_2__1_
wire [0:0] mux_tree_tapbuf_size10_mem_6_ccff_tail;
wire [0:0] mux_tree_tapbuf_size10_mem_7_ccff_tail;
wire [0:3] mux_tree_tapbuf_size8_0_sram;
wire [0:3] mux_tree_tapbuf_size8_0_sram_inv;
wire [0:3] mux_tree_tapbuf_size8_1_sram;
wire [0:3] mux_tree_tapbuf_size8_1_sram_inv;
wire [0:3] mux_tree_tapbuf_size8_2_sram;
wire [0:3] mux_tree_tapbuf_size8_2_sram_inv;
wire [0:3] mux_tree_tapbuf_size8_3_sram;
wire [0:3] mux_tree_tapbuf_size8_3_sram_inv;
wire [0:3] mux_tree_tapbuf_size8_4_sram;
wire [0:3] mux_tree_tapbuf_size8_4_sram_inv;
wire [0:3] mux_tree_tapbuf_size8_5_sram;
wire [0:3] mux_tree_tapbuf_size8_5_sram_inv;
wire [0:3] mux_tree_tapbuf_size8_6_sram;
wire [0:3] mux_tree_tapbuf_size8_6_sram_inv;
wire [0:3] mux_tree_tapbuf_size8_7_sram;
wire [0:3] mux_tree_tapbuf_size8_7_sram_inv;
wire [0:0] mux_tree_tapbuf_size8_mem_0_ccff_tail;
wire [0:0] mux_tree_tapbuf_size8_mem_1_ccff_tail;
wire [0:0] mux_tree_tapbuf_size8_mem_2_ccff_tail;
@ -131,7 +131,7 @@ module cby_2__1_
(
.in({ chany_bottom_in[0], chany_top_in[0], chany_bottom_in[2], chany_top_in[2], chany_bottom_in[4], chany_top_in[4], chany_bottom_in[10], chany_top_in[10], chany_bottom_in[16], chany_top_in[16] }),
.sram(mux_tree_tapbuf_size10_0_sram[0:3]),
.sram_inv(mux_tree_tapbuf_size10_0_sram_inv[0:3]),
.sram_inv(mux_left_ipin_0_undriven_sram_inv[0:3]),
.out(right_grid_pin_0_[0])
);
@ -141,7 +141,7 @@ module cby_2__1_
(
.in({ chany_bottom_in[1], chany_top_in[1], chany_bottom_in[3], chany_top_in[3], chany_bottom_in[5], chany_top_in[5], chany_bottom_in[11], chany_top_in[11], chany_bottom_in[17], chany_top_in[17] }),
.sram(mux_tree_tapbuf_size10_1_sram[0:3]),
.sram_inv(mux_tree_tapbuf_size10_1_sram_inv[0:3]),
.sram_inv(mux_right_ipin_0_undriven_sram_inv[0:3]),
.out(left_grid_pin_16_[0])
);
@ -151,7 +151,7 @@ module cby_2__1_
(
.in({ chany_bottom_in[0], chany_top_in[0], chany_bottom_in[2], chany_top_in[2], chany_bottom_in[4], chany_top_in[4], chany_bottom_in[8], chany_top_in[8], chany_bottom_in[14], chany_top_in[14] }),
.sram(mux_tree_tapbuf_size10_2_sram[0:3]),
.sram_inv(mux_tree_tapbuf_size10_2_sram_inv[0:3]),
.sram_inv(mux_right_ipin_3_undriven_sram_inv[0:3]),
.out(left_grid_pin_19_[0])
);
@ -161,7 +161,7 @@ module cby_2__1_
(
.in({ chany_bottom_in[1], chany_top_in[1], chany_bottom_in[3], chany_top_in[3], chany_bottom_in[5], chany_top_in[5], chany_bottom_in[9], chany_top_in[9], chany_bottom_in[15], chany_top_in[15] }),
.sram(mux_tree_tapbuf_size10_3_sram[0:3]),
.sram_inv(mux_tree_tapbuf_size10_3_sram_inv[0:3]),
.sram_inv(mux_right_ipin_4_undriven_sram_inv[0:3]),
.out(left_grid_pin_20_[0])
);
@ -171,7 +171,7 @@ module cby_2__1_
(
.in({ chany_bottom_in[0], chany_top_in[0], chany_bottom_in[2], chany_top_in[2], chany_bottom_in[8], chany_top_in[8], chany_bottom_in[12], chany_top_in[12], chany_bottom_in[18], chany_top_in[18] }),
.sram(mux_tree_tapbuf_size10_4_sram[0:3]),
.sram_inv(mux_tree_tapbuf_size10_4_sram_inv[0:3]),
.sram_inv(mux_right_ipin_7_undriven_sram_inv[0:3]),
.out(left_grid_pin_23_[0])
);
@ -181,7 +181,7 @@ module cby_2__1_
(
.in({ chany_bottom_in[1], chany_top_in[1], chany_bottom_in[3], chany_top_in[3], chany_bottom_in[9], chany_top_in[9], chany_bottom_in[13], chany_top_in[13], chany_bottom_in[19], chany_top_in[19] }),
.sram(mux_tree_tapbuf_size10_5_sram[0:3]),
.sram_inv(mux_tree_tapbuf_size10_5_sram_inv[0:3]),
.sram_inv(mux_right_ipin_8_undriven_sram_inv[0:3]),
.out(left_grid_pin_24_[0])
);
@ -191,7 +191,7 @@ module cby_2__1_
(
.in({ chany_bottom_in[0], chany_top_in[0], chany_bottom_in[2], chany_top_in[2], chany_bottom_in[6], chany_top_in[6], chany_bottom_in[12], chany_top_in[12], chany_bottom_in[16], chany_top_in[16] }),
.sram(mux_tree_tapbuf_size10_6_sram[0:3]),
.sram_inv(mux_tree_tapbuf_size10_6_sram_inv[0:3]),
.sram_inv(mux_right_ipin_11_undriven_sram_inv[0:3]),
.out(left_grid_pin_27_[0])
);
@ -201,7 +201,7 @@ module cby_2__1_
(
.in({ chany_bottom_in[1], chany_top_in[1], chany_bottom_in[3], chany_top_in[3], chany_bottom_in[7], chany_top_in[7], chany_bottom_in[13], chany_top_in[13], chany_bottom_in[17], chany_top_in[17] }),
.sram(mux_tree_tapbuf_size10_7_sram[0:3]),
.sram_inv(mux_tree_tapbuf_size10_7_sram_inv[0:3]),
.sram_inv(mux_right_ipin_12_undriven_sram_inv[0:3]),
.out(left_grid_pin_28_[0])
);
@ -211,7 +211,7 @@ module cby_2__1_
(
.in({ chany_bottom_in[0], chany_top_in[0], chany_bottom_in[2], chany_top_in[2], chany_bottom_in[4], chany_top_in[4], chany_bottom_in[10], chany_top_in[10], chany_bottom_in[16], chany_top_in[16] }),
.sram(mux_tree_tapbuf_size10_8_sram[0:3]),
.sram_inv(mux_tree_tapbuf_size10_8_sram_inv[0:3]),
.sram_inv(mux_right_ipin_15_undriven_sram_inv[0:3]),
.out(left_grid_pin_31_[0])
);
@ -222,8 +222,7 @@ module cby_2__1_
.prog_clk(prog_clk[0]),
.ccff_head(ccff_head[0]),
.ccff_tail(mux_tree_tapbuf_size10_mem_0_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size10_0_sram[0:3]),
.mem_outb(mux_tree_tapbuf_size10_0_sram_inv[0:3])
.mem_out(mux_tree_tapbuf_size10_0_sram[0:3])
);
@ -233,8 +232,7 @@ module cby_2__1_
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size10_mem_0_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size10_mem_1_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size10_1_sram[0:3]),
.mem_outb(mux_tree_tapbuf_size10_1_sram_inv[0:3])
.mem_out(mux_tree_tapbuf_size10_1_sram[0:3])
);
@ -244,8 +242,7 @@ module cby_2__1_
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size8_mem_1_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size10_mem_2_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size10_2_sram[0:3]),
.mem_outb(mux_tree_tapbuf_size10_2_sram_inv[0:3])
.mem_out(mux_tree_tapbuf_size10_2_sram[0:3])
);
@ -255,8 +252,7 @@ module cby_2__1_
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size10_mem_2_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size10_mem_3_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size10_3_sram[0:3]),
.mem_outb(mux_tree_tapbuf_size10_3_sram_inv[0:3])
.mem_out(mux_tree_tapbuf_size10_3_sram[0:3])
);
@ -266,8 +262,7 @@ module cby_2__1_
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size8_mem_3_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size10_mem_4_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size10_4_sram[0:3]),
.mem_outb(mux_tree_tapbuf_size10_4_sram_inv[0:3])
.mem_out(mux_tree_tapbuf_size10_4_sram[0:3])
);
@ -277,8 +272,7 @@ module cby_2__1_
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size10_mem_4_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size10_mem_5_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size10_5_sram[0:3]),
.mem_outb(mux_tree_tapbuf_size10_5_sram_inv[0:3])
.mem_out(mux_tree_tapbuf_size10_5_sram[0:3])
);
@ -288,8 +282,7 @@ module cby_2__1_
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size8_mem_5_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size10_mem_6_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size10_6_sram[0:3]),
.mem_outb(mux_tree_tapbuf_size10_6_sram_inv[0:3])
.mem_out(mux_tree_tapbuf_size10_6_sram[0:3])
);
@ -299,8 +292,7 @@ module cby_2__1_
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size10_mem_6_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size10_mem_7_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size10_7_sram[0:3]),
.mem_outb(mux_tree_tapbuf_size10_7_sram_inv[0:3])
.mem_out(mux_tree_tapbuf_size10_7_sram[0:3])
);
@ -310,8 +302,7 @@ module cby_2__1_
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size8_mem_7_ccff_tail[0]),
.ccff_tail(ccff_tail_mid),
.mem_out(mux_tree_tapbuf_size10_8_sram[0:3]),
.mem_outb(mux_tree_tapbuf_size10_8_sram_inv[0:3])
.mem_out(mux_tree_tapbuf_size10_8_sram[0:3])
);
@ -320,7 +311,7 @@ module cby_2__1_
(
.in({ chany_bottom_in[0], chany_top_in[0], chany_bottom_in[2], chany_top_in[2], chany_bottom_in[6], chany_top_in[6], chany_bottom_in[14], chany_top_in[14] }),
.sram(mux_tree_tapbuf_size8_0_sram[0:3]),
.sram_inv(mux_tree_tapbuf_size8_0_sram_inv[0:3]),
.sram_inv(mux_right_ipin_1_undriven_sram_inv[0:3]),
.out(left_grid_pin_17_[0])
);
@ -330,7 +321,7 @@ module cby_2__1_
(
.in({ chany_bottom_in[1], chany_top_in[1], chany_bottom_in[3], chany_top_in[3], chany_bottom_in[7], chany_top_in[7], chany_bottom_in[15], chany_top_in[15] }),
.sram(mux_tree_tapbuf_size8_1_sram[0:3]),
.sram_inv(mux_tree_tapbuf_size8_1_sram_inv[0:3]),
.sram_inv(mux_right_ipin_2_undriven_sram_inv[0:3]),
.out(left_grid_pin_18_[0])
);
@ -340,7 +331,7 @@ module cby_2__1_
(
.in({ chany_bottom_in[0], chany_top_in[0], chany_bottom_in[2], chany_top_in[2], chany_bottom_in[10], chany_top_in[10], chany_bottom_in[18], chany_top_in[18] }),
.sram(mux_tree_tapbuf_size8_2_sram[0:3]),
.sram_inv(mux_tree_tapbuf_size8_2_sram_inv[0:3]),
.sram_inv(mux_right_ipin_5_undriven_sram_inv[0:3]),
.out(left_grid_pin_21_[0])
);
@ -350,7 +341,7 @@ module cby_2__1_
(
.in({ chany_bottom_in[1], chany_top_in[1], chany_bottom_in[3], chany_top_in[3], chany_bottom_in[11], chany_top_in[11], chany_bottom_in[19], chany_top_in[19] }),
.sram(mux_tree_tapbuf_size8_3_sram[0:3]),
.sram_inv(mux_tree_tapbuf_size8_3_sram_inv[0:3]),
.sram_inv(mux_right_ipin_6_undriven_sram_inv[0:3]),
.out(left_grid_pin_22_[0])
);
@ -360,7 +351,7 @@ module cby_2__1_
(
.in({ chany_bottom_in[0], chany_top_in[0], chany_bottom_in[2], chany_top_in[2], chany_bottom_in[6], chany_top_in[6], chany_bottom_in[14], chany_top_in[14] }),
.sram(mux_tree_tapbuf_size8_4_sram[0:3]),
.sram_inv(mux_tree_tapbuf_size8_4_sram_inv[0:3]),
.sram_inv(mux_right_ipin_9_undriven_sram_inv[0:3]),
.out(left_grid_pin_25_[0])
);
@ -370,7 +361,7 @@ module cby_2__1_
(
.in({ chany_bottom_in[1], chany_top_in[1], chany_bottom_in[3], chany_top_in[3], chany_bottom_in[7], chany_top_in[7], chany_bottom_in[15], chany_top_in[15] }),
.sram(mux_tree_tapbuf_size8_5_sram[0:3]),
.sram_inv(mux_tree_tapbuf_size8_5_sram_inv[0:3]),
.sram_inv(mux_right_ipin_10_undriven_sram_inv[0:3]),
.out(left_grid_pin_26_[0])
);
@ -380,7 +371,7 @@ module cby_2__1_
(
.in({ chany_bottom_in[0], chany_top_in[0], chany_bottom_in[2], chany_top_in[2], chany_bottom_in[10], chany_top_in[10], chany_bottom_in[18], chany_top_in[18] }),
.sram(mux_tree_tapbuf_size8_6_sram[0:3]),
.sram_inv(mux_tree_tapbuf_size8_6_sram_inv[0:3]),
.sram_inv(mux_right_ipin_13_undriven_sram_inv[0:3]),
.out(left_grid_pin_29_[0])
);
@ -390,7 +381,7 @@ module cby_2__1_
(
.in({ chany_bottom_in[1], chany_top_in[1], chany_bottom_in[3], chany_top_in[3], chany_bottom_in[11], chany_top_in[11], chany_bottom_in[19], chany_top_in[19] }),
.sram(mux_tree_tapbuf_size8_7_sram[0:3]),
.sram_inv(mux_tree_tapbuf_size8_7_sram_inv[0:3]),
.sram_inv(mux_right_ipin_14_undriven_sram_inv[0:3]),
.out(left_grid_pin_30_[0])
);
@ -401,8 +392,7 @@ module cby_2__1_
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size10_mem_1_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size8_mem_0_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size8_0_sram[0:3]),
.mem_outb(mux_tree_tapbuf_size8_0_sram_inv[0:3])
.mem_out(mux_tree_tapbuf_size8_0_sram[0:3])
);
@ -412,8 +402,7 @@ module cby_2__1_
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size8_mem_0_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size8_mem_1_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size8_1_sram[0:3]),
.mem_outb(mux_tree_tapbuf_size8_1_sram_inv[0:3])
.mem_out(mux_tree_tapbuf_size8_1_sram[0:3])
);
@ -423,8 +412,7 @@ module cby_2__1_
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size10_mem_3_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size8_mem_2_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size8_2_sram[0:3]),
.mem_outb(mux_tree_tapbuf_size8_2_sram_inv[0:3])
.mem_out(mux_tree_tapbuf_size8_2_sram[0:3])
);
@ -434,8 +422,7 @@ module cby_2__1_
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size8_mem_2_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size8_mem_3_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size8_3_sram[0:3]),
.mem_outb(mux_tree_tapbuf_size8_3_sram_inv[0:3])
.mem_out(mux_tree_tapbuf_size8_3_sram[0:3])
);
@ -445,8 +432,7 @@ module cby_2__1_
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size10_mem_5_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size8_mem_4_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size8_4_sram[0:3]),
.mem_outb(mux_tree_tapbuf_size8_4_sram_inv[0:3])
.mem_out(mux_tree_tapbuf_size8_4_sram[0:3])
);
@ -456,8 +442,7 @@ module cby_2__1_
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size8_mem_4_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size8_mem_5_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size8_5_sram[0:3]),
.mem_outb(mux_tree_tapbuf_size8_5_sram_inv[0:3])
.mem_out(mux_tree_tapbuf_size8_5_sram[0:3])
);
@ -467,8 +452,7 @@ module cby_2__1_
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size10_mem_7_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size8_mem_6_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size8_6_sram[0:3]),
.mem_outb(mux_tree_tapbuf_size8_6_sram_inv[0:3])
.mem_out(mux_tree_tapbuf_size8_6_sram[0:3])
);
@ -478,8 +462,7 @@ module cby_2__1_
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size8_mem_6_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size8_mem_7_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size8_7_sram[0:3]),
.mem_outb(mux_tree_tapbuf_size8_7_sram_inv[0:3])
.mem_out(mux_tree_tapbuf_size8_7_sram[0:3])
);

140
FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/routing/sb_0__0_.v
View File

@ -17,38 +17,42 @@ module sb_0__0_
output [0:19] chanx_right_out;
output [0:0] ccff_tail;
wire [0:2] mux_right_track_0_undriven_sram_inv;
wire [0:1] mux_right_track_10_undriven_sram_inv;
wire [0:1] mux_right_track_12_undriven_sram_inv;
wire [0:1] mux_right_track_14_undriven_sram_inv;
wire [0:1] mux_right_track_16_undriven_sram_inv;
wire [0:1] mux_right_track_18_undriven_sram_inv;
wire [0:1] mux_right_track_24_undriven_sram_inv;
wire [0:1] mux_right_track_26_undriven_sram_inv;
wire [0:1] mux_right_track_28_undriven_sram_inv;
wire [0:2] mux_right_track_2_undriven_sram_inv;
wire [0:1] mux_right_track_30_undriven_sram_inv;
wire [0:1] mux_right_track_32_undriven_sram_inv;
wire [0:1] mux_right_track_34_undriven_sram_inv;
wire [0:2] mux_right_track_4_undriven_sram_inv;
wire [0:2] mux_right_track_6_undriven_sram_inv;
wire [0:1] mux_right_track_8_undriven_sram_inv;
wire [0:1] mux_top_track_0_undriven_sram_inv;
wire [0:1] mux_top_track_24_undriven_sram_inv;
wire [0:1] mux_top_track_4_undriven_sram_inv;
wire [0:1] mux_top_track_8_undriven_sram_inv;
wire [0:1] mux_tree_tapbuf_size2_0_sram;
wire [0:1] mux_tree_tapbuf_size2_0_sram_inv;
wire [0:1] mux_tree_tapbuf_size2_10_sram;
wire [0:1] mux_tree_tapbuf_size2_10_sram_inv;
wire [0:1] mux_tree_tapbuf_size2_11_sram;
wire [0:1] mux_tree_tapbuf_size2_11_sram_inv;
wire [0:1] mux_tree_tapbuf_size2_12_sram;
wire [0:1] mux_tree_tapbuf_size2_12_sram_inv;
wire [0:1] mux_tree_tapbuf_size2_13_sram;
wire [0:1] mux_tree_tapbuf_size2_13_sram_inv;
wire [0:1] mux_tree_tapbuf_size2_14_sram;
wire [0:1] mux_tree_tapbuf_size2_14_sram_inv;
wire [0:1] mux_tree_tapbuf_size2_15_sram;
wire [0:1] mux_tree_tapbuf_size2_15_sram_inv;
wire [0:1] mux_tree_tapbuf_size2_1_sram;
wire [0:1] mux_tree_tapbuf_size2_1_sram_inv;
wire [0:1] mux_tree_tapbuf_size2_2_sram;
wire [0:1] mux_tree_tapbuf_size2_2_sram_inv;
wire [0:1] mux_tree_tapbuf_size2_3_sram;
wire [0:1] mux_tree_tapbuf_size2_3_sram_inv;
wire [0:1] mux_tree_tapbuf_size2_4_sram;
wire [0:1] mux_tree_tapbuf_size2_4_sram_inv;
wire [0:1] mux_tree_tapbuf_size2_5_sram;
wire [0:1] mux_tree_tapbuf_size2_5_sram_inv;
wire [0:1] mux_tree_tapbuf_size2_6_sram;
wire [0:1] mux_tree_tapbuf_size2_6_sram_inv;
wire [0:1] mux_tree_tapbuf_size2_7_sram;
wire [0:1] mux_tree_tapbuf_size2_7_sram_inv;
wire [0:1] mux_tree_tapbuf_size2_8_sram;
wire [0:1] mux_tree_tapbuf_size2_8_sram_inv;
wire [0:1] mux_tree_tapbuf_size2_9_sram;
wire [0:1] mux_tree_tapbuf_size2_9_sram_inv;
wire [0:0] mux_tree_tapbuf_size2_mem_0_ccff_tail;
wire [0:0] mux_tree_tapbuf_size2_mem_10_ccff_tail;
wire [0:0] mux_tree_tapbuf_size2_mem_11_ccff_tail;
@ -65,13 +69,9 @@ module sb_0__0_
wire [0:0] mux_tree_tapbuf_size2_mem_8_ccff_tail;
wire [0:0] mux_tree_tapbuf_size2_mem_9_ccff_tail;
wire [0:2] mux_tree_tapbuf_size4_0_sram;
wire [0:2] mux_tree_tapbuf_size4_0_sram_inv;
wire [0:2] mux_tree_tapbuf_size4_1_sram;
wire [0:2] mux_tree_tapbuf_size4_1_sram_inv;
wire [0:2] mux_tree_tapbuf_size4_2_sram;
wire [0:2] mux_tree_tapbuf_size4_2_sram_inv;
wire [0:2] mux_tree_tapbuf_size4_3_sram;
wire [0:2] mux_tree_tapbuf_size4_3_sram_inv;
wire [0:0] mux_tree_tapbuf_size4_mem_0_ccff_tail;
wire [0:0] mux_tree_tapbuf_size4_mem_1_ccff_tail;
wire [0:0] mux_tree_tapbuf_size4_mem_2_ccff_tail;
@ -102,7 +102,7 @@ module sb_0__0_
(
.in({ top_left_grid_pin_1_[0], chanx_right_in[1] }),
.sram(mux_tree_tapbuf_size2_0_sram[0:1]),
.sram_inv(mux_tree_tapbuf_size2_0_sram_inv[0:1]),
.sram_inv(mux_top_track_0_undriven_sram_inv[0:1]),
.out(chany_top_out[0])
);
@ -112,7 +112,7 @@ module sb_0__0_
(
.in({ top_left_grid_pin_1_[0], chanx_right_in[3] }),
.sram(mux_tree_tapbuf_size2_1_sram[0:1]),
.sram_inv(mux_tree_tapbuf_size2_1_sram_inv[0:1]),
.sram_inv(mux_top_track_4_undriven_sram_inv[0:1]),
.out(chany_top_out[2])
);
@ -122,7 +122,7 @@ module sb_0__0_
(
.in({ top_left_grid_pin_1_[0], chanx_right_in[5] }),
.sram(mux_tree_tapbuf_size2_2_sram[0:1]),
.sram_inv(mux_tree_tapbuf_size2_2_sram_inv[0:1]),
.sram_inv(mux_top_track_8_undriven_sram_inv[0:1]),
.out(chany_top_out[4])
);
@ -132,7 +132,7 @@ module sb_0__0_
(
.in({ top_left_grid_pin_1_[0], chanx_right_in[13] }),
.sram(mux_tree_tapbuf_size2_3_sram[0:1]),
.sram_inv(mux_tree_tapbuf_size2_3_sram_inv[0:1]),
.sram_inv(mux_top_track_24_undriven_sram_inv[0:1]),
.out(chany_top_out[12])
);
@ -142,7 +142,7 @@ module sb_0__0_
(
.in({ chany_top_in[3], right_bottom_grid_pin_1_[0] }),
.sram(mux_tree_tapbuf_size2_4_sram[0:1]),
.sram_inv(mux_tree_tapbuf_size2_4_sram_inv[0:1]),
.sram_inv(mux_right_track_8_undriven_sram_inv[0:1]),
.out(chanx_right_out[4])
);
@ -152,7 +152,7 @@ module sb_0__0_
(
.in({ chany_top_in[4], right_bottom_grid_pin_3_[0] }),
.sram(mux_tree_tapbuf_size2_5_sram[0:1]),
.sram_inv(mux_tree_tapbuf_size2_5_sram_inv[0:1]),
.sram_inv(mux_right_track_10_undriven_sram_inv[0:1]),
.out(chanx_right_out[5])
);
@ -162,7 +162,7 @@ module sb_0__0_
(
.in({ chany_top_in[5], right_bottom_grid_pin_5_[0] }),
.sram(mux_tree_tapbuf_size2_6_sram[0:1]),
.sram_inv(mux_tree_tapbuf_size2_6_sram_inv[0:1]),
.sram_inv(mux_right_track_12_undriven_sram_inv[0:1]),
.out(chanx_right_out[6])
);
@ -172,7 +172,7 @@ module sb_0__0_
(
.in({ chany_top_in[6], right_bottom_grid_pin_7_[0] }),
.sram(mux_tree_tapbuf_size2_7_sram[0:1]),
.sram_inv(mux_tree_tapbuf_size2_7_sram_inv[0:1]),
.sram_inv(mux_right_track_14_undriven_sram_inv[0:1]),
.out(chanx_right_out[7])
);
@ -182,7 +182,7 @@ module sb_0__0_
(
.in({ chany_top_in[7], right_bottom_grid_pin_9_[0] }),
.sram(mux_tree_tapbuf_size2_8_sram[0:1]),
.sram_inv(mux_tree_tapbuf_size2_8_sram_inv[0:1]),
.sram_inv(mux_right_track_16_undriven_sram_inv[0:1]),
.out(chanx_right_out[8])
);
@ -192,7 +192,7 @@ module sb_0__0_
(
.in({ chany_top_in[8], right_bottom_grid_pin_11_[0] }),
.sram(mux_tree_tapbuf_size2_9_sram[0:1]),
.sram_inv(mux_tree_tapbuf_size2_9_sram_inv[0:1]),
.sram_inv(mux_right_track_18_undriven_sram_inv[0:1]),
.out(chanx_right_out[9])
);
@ -202,7 +202,7 @@ module sb_0__0_
(
.in({ chany_top_in[11], right_bottom_grid_pin_1_[0] }),
.sram(mux_tree_tapbuf_size2_10_sram[0:1]),
.sram_inv(mux_tree_tapbuf_size2_10_sram_inv[0:1]),
.sram_inv(mux_right_track_24_undriven_sram_inv[0:1]),
.out(chanx_right_out[12])
);
@ -212,7 +212,7 @@ module sb_0__0_
(
.in({ chany_top_in[12], right_bottom_grid_pin_3_[0] }),
.sram(mux_tree_tapbuf_size2_11_sram[0:1]),
.sram_inv(mux_tree_tapbuf_size2_11_sram_inv[0:1]),
.sram_inv(mux_right_track_26_undriven_sram_inv[0:1]),
.out(chanx_right_out[13])
);
@ -222,7 +222,7 @@ module sb_0__0_
(
.in({ chany_top_in[13], right_bottom_grid_pin_5_[0] }),
.sram(mux_tree_tapbuf_size2_12_sram[0:1]),
.sram_inv(mux_tree_tapbuf_size2_12_sram_inv[0:1]),
.sram_inv(mux_right_track_28_undriven_sram_inv[0:1]),
.out(chanx_right_out[14])
);
@ -232,7 +232,7 @@ module sb_0__0_
(
.in({ chany_top_in[14], right_bottom_grid_pin_7_[0] }),
.sram(mux_tree_tapbuf_size2_13_sram[0:1]),
.sram_inv(mux_tree_tapbuf_size2_13_sram_inv[0:1]),
.sram_inv(mux_right_track_30_undriven_sram_inv[0:1]),
.out(chanx_right_out[15])
);
@ -242,7 +242,7 @@ module sb_0__0_
(
.in({ chany_top_in[15], right_bottom_grid_pin_9_[0] }),
.sram(mux_tree_tapbuf_size2_14_sram[0:1]),
.sram_inv(mux_tree_tapbuf_size2_14_sram_inv[0:1]),
.sram_inv(mux_right_track_32_undriven_sram_inv[0:1]),
.out(chanx_right_out[16])
);
@ -252,7 +252,7 @@ module sb_0__0_
(
.in({ chany_top_in[16], right_bottom_grid_pin_11_[0] }),
.sram(mux_tree_tapbuf_size2_15_sram[0:1]),
.sram_inv(mux_tree_tapbuf_size2_15_sram_inv[0:1]),
.sram_inv(mux_right_track_34_undriven_sram_inv[0:1]),
.out(chanx_right_out[17])
);
@ -263,8 +263,7 @@ module sb_0__0_
.prog_clk(prog_clk[0]),
.ccff_head(ccff_head[0]),
.ccff_tail(mux_tree_tapbuf_size2_mem_0_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size2_0_sram[0:1]),
.mem_outb(mux_tree_tapbuf_size2_0_sram_inv[0:1])
.mem_out(mux_tree_tapbuf_size2_0_sram[0:1])
);
@ -274,8 +273,7 @@ module sb_0__0_
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size2_mem_0_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size2_mem_1_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size2_1_sram[0:1]),
.mem_outb(mux_tree_tapbuf_size2_1_sram_inv[0:1])
.mem_out(mux_tree_tapbuf_size2_1_sram[0:1])
);
@ -285,8 +283,7 @@ module sb_0__0_
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size2_mem_1_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size2_mem_2_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size2_2_sram[0:1]),
.mem_outb(mux_tree_tapbuf_size2_2_sram_inv[0:1])
.mem_out(mux_tree_tapbuf_size2_2_sram[0:1])
);
@ -296,8 +293,7 @@ module sb_0__0_
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size2_mem_2_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size2_mem_3_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size2_3_sram[0:1]),
.mem_outb(mux_tree_tapbuf_size2_3_sram_inv[0:1])
.mem_out(mux_tree_tapbuf_size2_3_sram[0:1])
);
@ -307,8 +303,7 @@ module sb_0__0_
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size4_mem_3_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size2_mem_4_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size2_4_sram[0:1]),
.mem_outb(mux_tree_tapbuf_size2_4_sram_inv[0:1])
.mem_out(mux_tree_tapbuf_size2_4_sram[0:1])
);
@ -318,8 +313,7 @@ module sb_0__0_
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size2_mem_4_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size2_mem_5_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size2_5_sram[0:1]),
.mem_outb(mux_tree_tapbuf_size2_5_sram_inv[0:1])
.mem_out(mux_tree_tapbuf_size2_5_sram[0:1])
);
@ -329,8 +323,7 @@ module sb_0__0_
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size2_mem_5_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size2_mem_6_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size2_6_sram[0:1]),
.mem_outb(mux_tree_tapbuf_size2_6_sram_inv[0:1])
.mem_out(mux_tree_tapbuf_size2_6_sram[0:1])
);
@ -340,8 +333,7 @@ module sb_0__0_
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size2_mem_6_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size2_mem_7_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size2_7_sram[0:1]),
.mem_outb(mux_tree_tapbuf_size2_7_sram_inv[0:1])
.mem_out(mux_tree_tapbuf_size2_7_sram[0:1])
);
@ -351,8 +343,7 @@ module sb_0__0_
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size2_mem_7_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size2_mem_8_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size2_8_sram[0:1]),
.mem_outb(mux_tree_tapbuf_size2_8_sram_inv[0:1])
.mem_out(mux_tree_tapbuf_size2_8_sram[0:1])
);
@ -362,8 +353,7 @@ module sb_0__0_
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size2_mem_8_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size2_mem_9_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size2_9_sram[0:1]),
.mem_outb(mux_tree_tapbuf_size2_9_sram_inv[0:1])
.mem_out(mux_tree_tapbuf_size2_9_sram[0:1])
);
@ -373,8 +363,7 @@ module sb_0__0_
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size2_mem_9_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size2_mem_10_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size2_10_sram[0:1]),
.mem_outb(mux_tree_tapbuf_size2_10_sram_inv[0:1])
.mem_out(mux_tree_tapbuf_size2_10_sram[0:1])
);
@ -384,8 +373,7 @@ module sb_0__0_
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size2_mem_10_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size2_mem_11_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size2_11_sram[0:1]),
.mem_outb(mux_tree_tapbuf_size2_11_sram_inv[0:1])
.mem_out(mux_tree_tapbuf_size2_11_sram[0:1])
);
@ -395,8 +383,7 @@ module sb_0__0_
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size2_mem_11_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size2_mem_12_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size2_12_sram[0:1]),
.mem_outb(mux_tree_tapbuf_size2_12_sram_inv[0:1])
.mem_out(mux_tree_tapbuf_size2_12_sram[0:1])
);
@ -406,8 +393,7 @@ module sb_0__0_
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size2_mem_12_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size2_mem_13_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size2_13_sram[0:1]),
.mem_outb(mux_tree_tapbuf_size2_13_sram_inv[0:1])
.mem_out(mux_tree_tapbuf_size2_13_sram[0:1])
);
@ -417,8 +403,7 @@ module sb_0__0_
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size2_mem_13_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size2_mem_14_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size2_14_sram[0:1]),
.mem_outb(mux_tree_tapbuf_size2_14_sram_inv[0:1])
.mem_out(mux_tree_tapbuf_size2_14_sram[0:1])
);
@ -428,8 +413,7 @@ module sb_0__0_
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size2_mem_14_ccff_tail[0]),
.ccff_tail(ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size2_15_sram[0:1]),
.mem_outb(mux_tree_tapbuf_size2_15_sram_inv[0:1])
.mem_out(mux_tree_tapbuf_size2_15_sram[0:1])
);
@ -438,7 +422,7 @@ module sb_0__0_
(
.in({ chany_top_in[19], right_bottom_grid_pin_1_[0], right_bottom_grid_pin_5_[0], right_bottom_grid_pin_9_[0] }),
.sram(mux_tree_tapbuf_size4_0_sram[0:2]),
.sram_inv(mux_tree_tapbuf_size4_0_sram_inv[0:2]),
.sram_inv(mux_right_track_0_undriven_sram_inv[0:2]),
.out(chanx_right_out[0])
);
@ -448,7 +432,7 @@ module sb_0__0_
(
.in({ chany_top_in[0], right_bottom_grid_pin_3_[0], right_bottom_grid_pin_7_[0], right_bottom_grid_pin_11_[0] }),
.sram(mux_tree_tapbuf_size4_1_sram[0:2]),
.sram_inv(mux_tree_tapbuf_size4_1_sram_inv[0:2]),
.sram_inv(mux_right_track_2_undriven_sram_inv[0:2]),
.out(chanx_right_out[1])
);
@ -458,7 +442,7 @@ module sb_0__0_
(
.in({ chany_top_in[1], right_bottom_grid_pin_1_[0], right_bottom_grid_pin_5_[0], right_bottom_grid_pin_9_[0] }),
.sram(mux_tree_tapbuf_size4_2_sram[0:2]),
.sram_inv(mux_tree_tapbuf_size4_2_sram_inv[0:2]),
.sram_inv(mux_right_track_4_undriven_sram_inv[0:2]),
.out(chanx_right_out[2])
);
@ -468,7 +452,7 @@ module sb_0__0_
(
.in({ chany_top_in[2], right_bottom_grid_pin_3_[0], right_bottom_grid_pin_7_[0], right_bottom_grid_pin_11_[0] }),
.sram(mux_tree_tapbuf_size4_3_sram[0:2]),
.sram_inv(mux_tree_tapbuf_size4_3_sram_inv[0:2]),
.sram_inv(mux_right_track_6_undriven_sram_inv[0:2]),
.out(chanx_right_out[3])
);
@ -479,8 +463,7 @@ module sb_0__0_
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size2_mem_3_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size4_mem_0_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size4_0_sram[0:2]),
.mem_outb(mux_tree_tapbuf_size4_0_sram_inv[0:2])
.mem_out(mux_tree_tapbuf_size4_0_sram[0:2])
);
@ -490,8 +473,7 @@ module sb_0__0_
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size4_mem_0_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size4_mem_1_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size4_1_sram[0:2]),
.mem_outb(mux_tree_tapbuf_size4_1_sram_inv[0:2])
.mem_out(mux_tree_tapbuf_size4_1_sram[0:2])
);
@ -501,8 +483,7 @@ module sb_0__0_
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size4_mem_1_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size4_mem_2_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size4_2_sram[0:2]),
.mem_outb(mux_tree_tapbuf_size4_2_sram_inv[0:2])
.mem_out(mux_tree_tapbuf_size4_2_sram[0:2])
);
@ -512,8 +493,7 @@ module sb_0__0_
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size4_mem_2_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size4_mem_3_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size4_3_sram[0:2]),
.mem_outb(mux_tree_tapbuf_size4_3_sram_inv[0:2])
.mem_out(mux_tree_tapbuf_size4_3_sram[0:2])
);

231
FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/routing/sb_0__1_.v
View File

@ -22,18 +22,45 @@ module sb_0__1_
output [0:19] chany_bottom_out;
output [0:0] ccff_tail;
wire [0:2] mux_bottom_track_17_undriven_sram_inv;
wire [0:2] mux_bottom_track_1_undriven_sram_inv;
wire [0:2] mux_bottom_track_25_undriven_sram_inv;
wire [0:1] mux_bottom_track_33_undriven_sram_inv;
wire [0:2] mux_bottom_track_3_undriven_sram_inv;
wire [0:2] mux_bottom_track_5_undriven_sram_inv;
wire [0:2] mux_bottom_track_9_undriven_sram_inv;
wire [0:2] mux_right_track_0_undriven_sram_inv;
wire [0:2] mux_right_track_10_undriven_sram_inv;
wire [0:2] mux_right_track_12_undriven_sram_inv;
wire [0:2] mux_right_track_14_undriven_sram_inv;
wire [0:1] mux_right_track_16_undriven_sram_inv;
wire [0:1] mux_right_track_18_undriven_sram_inv;
wire [0:1] mux_right_track_20_undriven_sram_inv;
wire [0:1] mux_right_track_22_undriven_sram_inv;
wire [0:2] mux_right_track_24_undriven_sram_inv;
wire [0:1] mux_right_track_26_undriven_sram_inv;
wire [0:1] mux_right_track_28_undriven_sram_inv;
wire [0:2] mux_right_track_2_undriven_sram_inv;
wire [0:1] mux_right_track_30_undriven_sram_inv;
wire [0:1] mux_right_track_32_undriven_sram_inv;
wire [0:1] mux_right_track_34_undriven_sram_inv;
wire [0:1] mux_right_track_36_undriven_sram_inv;
wire [0:2] mux_right_track_4_undriven_sram_inv;
wire [0:2] mux_right_track_6_undriven_sram_inv;
wire [0:2] mux_right_track_8_undriven_sram_inv;
wire [0:2] mux_top_track_0_undriven_sram_inv;
wire [0:2] mux_top_track_16_undriven_sram_inv;
wire [0:2] mux_top_track_24_undriven_sram_inv;
wire [0:2] mux_top_track_2_undriven_sram_inv;
wire [0:2] mux_top_track_32_undriven_sram_inv;
wire [0:2] mux_top_track_4_undriven_sram_inv;
wire [0:2] mux_top_track_8_undriven_sram_inv;
wire [0:1] mux_tree_tapbuf_size2_0_sram;
wire [0:1] mux_tree_tapbuf_size2_0_sram_inv;
wire [0:1] mux_tree_tapbuf_size2_1_sram;
wire [0:1] mux_tree_tapbuf_size2_1_sram_inv;
wire [0:1] mux_tree_tapbuf_size2_2_sram;
wire [0:1] mux_tree_tapbuf_size2_2_sram_inv;
wire [0:1] mux_tree_tapbuf_size2_3_sram;
wire [0:1] mux_tree_tapbuf_size2_3_sram_inv;
wire [0:1] mux_tree_tapbuf_size2_4_sram;
wire [0:1] mux_tree_tapbuf_size2_4_sram_inv;
wire [0:1] mux_tree_tapbuf_size2_5_sram;
wire [0:1] mux_tree_tapbuf_size2_5_sram_inv;
wire [0:0] mux_tree_tapbuf_size2_mem_0_ccff_tail;
wire [0:0] mux_tree_tapbuf_size2_mem_1_ccff_tail;
wire [0:0] mux_tree_tapbuf_size2_mem_2_ccff_tail;
@ -41,33 +68,21 @@ module sb_0__1_
wire [0:0] mux_tree_tapbuf_size2_mem_4_ccff_tail;
wire [0:0] mux_tree_tapbuf_size2_mem_5_ccff_tail;
wire [0:1] mux_tree_tapbuf_size3_0_sram;
wire [0:1] mux_tree_tapbuf_size3_0_sram_inv;
wire [0:1] mux_tree_tapbuf_size3_1_sram;
wire [0:1] mux_tree_tapbuf_size3_1_sram_inv;
wire [0:1] mux_tree_tapbuf_size3_2_sram;
wire [0:1] mux_tree_tapbuf_size3_2_sram_inv;
wire [0:1] mux_tree_tapbuf_size3_3_sram;
wire [0:1] mux_tree_tapbuf_size3_3_sram_inv;
wire [0:1] mux_tree_tapbuf_size3_4_sram;
wire [0:1] mux_tree_tapbuf_size3_4_sram_inv;
wire [0:0] mux_tree_tapbuf_size3_mem_0_ccff_tail;
wire [0:0] mux_tree_tapbuf_size3_mem_1_ccff_tail;
wire [0:0] mux_tree_tapbuf_size3_mem_2_ccff_tail;
wire [0:0] mux_tree_tapbuf_size3_mem_3_ccff_tail;
wire [0:2] mux_tree_tapbuf_size4_0_sram;
wire [0:2] mux_tree_tapbuf_size4_0_sram_inv;
wire [0:2] mux_tree_tapbuf_size4_1_sram;
wire [0:2] mux_tree_tapbuf_size4_1_sram_inv;
wire [0:2] mux_tree_tapbuf_size4_2_sram;
wire [0:2] mux_tree_tapbuf_size4_2_sram_inv;
wire [0:2] mux_tree_tapbuf_size4_3_sram;
wire [0:2] mux_tree_tapbuf_size4_3_sram_inv;
wire [0:2] mux_tree_tapbuf_size4_4_sram;
wire [0:2] mux_tree_tapbuf_size4_4_sram_inv;
wire [0:2] mux_tree_tapbuf_size4_5_sram;
wire [0:2] mux_tree_tapbuf_size4_5_sram_inv;
wire [0:2] mux_tree_tapbuf_size4_6_sram;
wire [0:2] mux_tree_tapbuf_size4_6_sram_inv;
wire [0:0] mux_tree_tapbuf_size4_mem_0_ccff_tail;
wire [0:0] mux_tree_tapbuf_size4_mem_1_ccff_tail;
wire [0:0] mux_tree_tapbuf_size4_mem_2_ccff_tail;
@ -76,34 +91,22 @@ module sb_0__1_
wire [0:0] mux_tree_tapbuf_size4_mem_5_ccff_tail;
wire [0:0] mux_tree_tapbuf_size4_mem_6_ccff_tail;
wire [0:2] mux_tree_tapbuf_size5_0_sram;
wire [0:2] mux_tree_tapbuf_size5_0_sram_inv;
wire [0:2] mux_tree_tapbuf_size5_1_sram;
wire [0:2] mux_tree_tapbuf_size5_1_sram_inv;
wire [0:2] mux_tree_tapbuf_size5_2_sram;
wire [0:2] mux_tree_tapbuf_size5_2_sram_inv;
wire [0:2] mux_tree_tapbuf_size5_3_sram;
wire [0:2] mux_tree_tapbuf_size5_3_sram_inv;
wire [0:2] mux_tree_tapbuf_size5_4_sram;
wire [0:2] mux_tree_tapbuf_size5_4_sram_inv;
wire [0:0] mux_tree_tapbuf_size5_mem_0_ccff_tail;
wire [0:0] mux_tree_tapbuf_size5_mem_1_ccff_tail;
wire [0:0] mux_tree_tapbuf_size5_mem_2_ccff_tail;
wire [0:0] mux_tree_tapbuf_size5_mem_3_ccff_tail;
wire [0:0] mux_tree_tapbuf_size5_mem_4_ccff_tail;
wire [0:2] mux_tree_tapbuf_size6_0_sram;
wire [0:2] mux_tree_tapbuf_size6_0_sram_inv;
wire [0:2] mux_tree_tapbuf_size6_1_sram;
wire [0:2] mux_tree_tapbuf_size6_1_sram_inv;
wire [0:2] mux_tree_tapbuf_size6_2_sram;
wire [0:2] mux_tree_tapbuf_size6_2_sram_inv;
wire [0:2] mux_tree_tapbuf_size6_3_sram;
wire [0:2] mux_tree_tapbuf_size6_3_sram_inv;
wire [0:2] mux_tree_tapbuf_size6_4_sram;
wire [0:2] mux_tree_tapbuf_size6_4_sram_inv;
wire [0:2] mux_tree_tapbuf_size6_5_sram;
wire [0:2] mux_tree_tapbuf_size6_5_sram_inv;
wire [0:2] mux_tree_tapbuf_size6_6_sram;
wire [0:2] mux_tree_tapbuf_size6_6_sram_inv;
wire [0:0] mux_tree_tapbuf_size6_mem_0_ccff_tail;
wire [0:0] mux_tree_tapbuf_size6_mem_1_ccff_tail;
wire [0:0] mux_tree_tapbuf_size6_mem_2_ccff_tail;
@ -112,11 +115,8 @@ module sb_0__1_
wire [0:0] mux_tree_tapbuf_size6_mem_5_ccff_tail;
wire [0:0] mux_tree_tapbuf_size6_mem_6_ccff_tail;
wire [0:2] mux_tree_tapbuf_size7_0_sram;
wire [0:2] mux_tree_tapbuf_size7_0_sram_inv;
wire [0:2] mux_tree_tapbuf_size7_1_sram;
wire [0:2] mux_tree_tapbuf_size7_1_sram_inv;
wire [0:2] mux_tree_tapbuf_size7_2_sram;
wire [0:2] mux_tree_tapbuf_size7_2_sram_inv;
wire [0:0] mux_tree_tapbuf_size7_mem_0_ccff_tail;
wire [0:0] mux_tree_tapbuf_size7_mem_1_ccff_tail;
wire [0:0] mux_tree_tapbuf_size7_mem_2_ccff_tail;
@ -153,7 +153,7 @@ module sb_0__1_
(
.in({ top_left_grid_pin_1_[0], chanx_right_in[1], chanx_right_in[8], chanx_right_in[15], chany_bottom_in[2], chany_bottom_in[12] }),
.sram(mux_tree_tapbuf_size6_0_sram[0:2]),
.sram_inv(mux_tree_tapbuf_size6_0_sram_inv[0:2]),
.sram_inv(mux_top_track_0_undriven_sram_inv[0:2]),
.out(chany_top_out[0])
);
@ -163,7 +163,7 @@ module sb_0__1_
(
.in({ top_left_grid_pin_1_[0], chanx_right_in[3], chanx_right_in[10], chanx_right_in[17], chany_bottom_in[5], chany_bottom_in[14] }),
.sram(mux_tree_tapbuf_size6_1_sram[0:2]),
.sram_inv(mux_tree_tapbuf_size6_1_sram_inv[0:2]),
.sram_inv(mux_top_track_4_undriven_sram_inv[0:2]),
.out(chany_top_out[2])
);
@ -173,7 +173,7 @@ module sb_0__1_
(
.in({ top_left_grid_pin_1_[0], chanx_right_in[4], chanx_right_in[11], chanx_right_in[18], chany_bottom_in[6], chany_bottom_in[16] }),
.sram(mux_tree_tapbuf_size6_2_sram[0:2]),
.sram_inv(mux_tree_tapbuf_size6_2_sram_inv[0:2]),
.sram_inv(mux_top_track_8_undriven_sram_inv[0:2]),
.out(chany_top_out[4])
);
@ -183,7 +183,7 @@ module sb_0__1_
(
.in({ chany_top_in[2], right_bottom_grid_pin_34_[0], right_bottom_grid_pin_36_[0], right_bottom_grid_pin_38_[0], right_bottom_grid_pin_40_[0], chany_bottom_in[2] }),
.sram(mux_tree_tapbuf_size6_3_sram[0:2]),
.sram_inv(mux_tree_tapbuf_size6_3_sram_inv[0:2]),
.sram_inv(mux_right_track_0_undriven_sram_inv[0:2]),
.out(chanx_right_out[0])
);
@ -193,7 +193,7 @@ module sb_0__1_
(
.in({ chany_top_in[2], chany_top_in[12], chanx_right_in[5], chanx_right_in[12], chanx_right_in[19], bottom_left_grid_pin_1_[0] }),
.sram(mux_tree_tapbuf_size6_4_sram[0:2]),
.sram_inv(mux_tree_tapbuf_size6_4_sram_inv[0:2]),
.sram_inv(mux_bottom_track_1_undriven_sram_inv[0:2]),
.out(chany_bottom_out[0])
);
@ -203,7 +203,7 @@ module sb_0__1_
(
.in({ chany_top_in[5], chany_top_in[14], chanx_right_in[3], chanx_right_in[10], chanx_right_in[17], bottom_left_grid_pin_1_[0] }),
.sram(mux_tree_tapbuf_size6_5_sram[0:2]),
.sram_inv(mux_tree_tapbuf_size6_5_sram_inv[0:2]),
.sram_inv(mux_bottom_track_5_undriven_sram_inv[0:2]),
.out(chany_bottom_out[2])
);
@ -213,7 +213,7 @@ module sb_0__1_
(
.in({ chany_top_in[6], chany_top_in[16], chanx_right_in[2], chanx_right_in[9], chanx_right_in[16], bottom_left_grid_pin_1_[0] }),
.sram(mux_tree_tapbuf_size6_6_sram[0:2]),
.sram_inv(mux_tree_tapbuf_size6_6_sram_inv[0:2]),
.sram_inv(mux_bottom_track_9_undriven_sram_inv[0:2]),
.out(chany_bottom_out[4])
);
@ -224,8 +224,7 @@ module sb_0__1_
.prog_clk(prog_clk[0]),
.ccff_head(ccff_head[0]),
.ccff_tail(mux_tree_tapbuf_size6_mem_0_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size6_0_sram[0:2]),
.mem_outb(mux_tree_tapbuf_size6_0_sram_inv[0:2])
.mem_out(mux_tree_tapbuf_size6_0_sram[0:2])
);
@ -235,8 +234,7 @@ module sb_0__1_
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size5_mem_0_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size6_mem_1_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size6_1_sram[0:2]),
.mem_outb(mux_tree_tapbuf_size6_1_sram_inv[0:2])
.mem_out(mux_tree_tapbuf_size6_1_sram[0:2])
);
@ -246,8 +244,7 @@ module sb_0__1_
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size6_mem_1_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size6_mem_2_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size6_2_sram[0:2]),
.mem_outb(mux_tree_tapbuf_size6_2_sram_inv[0:2])
.mem_out(mux_tree_tapbuf_size6_2_sram[0:2])
);
@ -257,8 +254,7 @@ module sb_0__1_
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size4_mem_1_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size6_mem_3_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size6_3_sram[0:2]),
.mem_outb(mux_tree_tapbuf_size6_3_sram_inv[0:2])
.mem_out(mux_tree_tapbuf_size6_3_sram[0:2])
);
@ -268,8 +264,7 @@ module sb_0__1_
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size2_mem_5_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size6_mem_4_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size6_4_sram[0:2]),
.mem_outb(mux_tree_tapbuf_size6_4_sram_inv[0:2])
.mem_out(mux_tree_tapbuf_size6_4_sram[0:2])
);
@ -279,8 +274,7 @@ module sb_0__1_
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size5_mem_2_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size6_mem_5_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size6_5_sram[0:2]),
.mem_outb(mux_tree_tapbuf_size6_5_sram_inv[0:2])
.mem_out(mux_tree_tapbuf_size6_5_sram[0:2])
);
@ -290,8 +284,7 @@ module sb_0__1_
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size6_mem_5_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size6_mem_6_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size6_6_sram[0:2]),
.mem_outb(mux_tree_tapbuf_size6_6_sram_inv[0:2])
.mem_out(mux_tree_tapbuf_size6_6_sram[0:2])
);
@ -300,7 +293,7 @@ module sb_0__1_
(
.in({ chanx_right_in[2], chanx_right_in[9], chanx_right_in[16], chany_bottom_in[4], chany_bottom_in[13] }),
.sram(mux_tree_tapbuf_size5_0_sram[0:2]),
.sram_inv(mux_tree_tapbuf_size5_0_sram_inv[0:2]),
.sram_inv(mux_top_track_2_undriven_sram_inv[0:2]),
.out(chany_top_out[1])
);
@ -310,7 +303,7 @@ module sb_0__1_
(
.in({ chanx_right_in[5], chanx_right_in[12], chanx_right_in[19], chany_bottom_in[8], chany_bottom_in[17] }),
.sram(mux_tree_tapbuf_size5_1_sram[0:2]),
.sram_inv(mux_tree_tapbuf_size5_1_sram_inv[0:2]),
.sram_inv(mux_top_track_16_undriven_sram_inv[0:2]),
.out(chany_top_out[8])
);
@ -320,7 +313,7 @@ module sb_0__1_
(
.in({ chany_top_in[4], chany_top_in[13], chanx_right_in[4], chanx_right_in[11], chanx_right_in[18] }),
.sram(mux_tree_tapbuf_size5_2_sram[0:2]),
.sram_inv(mux_tree_tapbuf_size5_2_sram_inv[0:2]),
.sram_inv(mux_bottom_track_3_undriven_sram_inv[0:2]),
.out(chany_bottom_out[1])
);
@ -330,7 +323,7 @@ module sb_0__1_
(
.in({ chany_top_in[8], chany_top_in[17], chanx_right_in[1], chanx_right_in[8], chanx_right_in[15] }),
.sram(mux_tree_tapbuf_size5_3_sram[0:2]),
.sram_inv(mux_tree_tapbuf_size5_3_sram_inv[0:2]),
.sram_inv(mux_bottom_track_17_undriven_sram_inv[0:2]),
.out(chany_bottom_out[8])
);
@ -340,7 +333,7 @@ module sb_0__1_
(
.in({ chany_top_in[9], chany_top_in[18], chanx_right_in[0], chanx_right_in[7], chanx_right_in[14] }),
.sram(mux_tree_tapbuf_size5_4_sram[0:2]),
.sram_inv(mux_tree_tapbuf_size5_4_sram_inv[0:2]),
.sram_inv(mux_bottom_track_25_undriven_sram_inv[0:2]),
.out(chany_bottom_out[12])
);
@ -351,8 +344,7 @@ module sb_0__1_
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size6_mem_0_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size5_mem_0_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size5_0_sram[0:2]),
.mem_outb(mux_tree_tapbuf_size5_0_sram_inv[0:2])
.mem_out(mux_tree_tapbuf_size5_0_sram[0:2])
);
@ -362,8 +354,7 @@ module sb_0__1_
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size6_mem_2_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size5_mem_1_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size5_1_sram[0:2]),
.mem_outb(mux_tree_tapbuf_size5_1_sram_inv[0:2])
.mem_out(mux_tree_tapbuf_size5_1_sram[0:2])
);
@ -373,8 +364,7 @@ module sb_0__1_
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size6_mem_4_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size5_mem_2_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size5_2_sram[0:2]),
.mem_outb(mux_tree_tapbuf_size5_2_sram_inv[0:2])
.mem_out(mux_tree_tapbuf_size5_2_sram[0:2])
);
@ -384,8 +374,7 @@ module sb_0__1_
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size6_mem_6_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size5_mem_3_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size5_3_sram[0:2]),
.mem_outb(mux_tree_tapbuf_size5_3_sram_inv[0:2])
.mem_out(mux_tree_tapbuf_size5_3_sram[0:2])
);
@ -395,8 +384,7 @@ module sb_0__1_
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size5_mem_3_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size5_mem_4_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size5_4_sram[0:2]),
.mem_outb(mux_tree_tapbuf_size5_4_sram_inv[0:2])
.mem_out(mux_tree_tapbuf_size5_4_sram[0:2])
);
@ -405,7 +393,7 @@ module sb_0__1_
(
.in({ chanx_right_in[6], chanx_right_in[13], chany_bottom_in[9], chany_bottom_in[18] }),
.sram(mux_tree_tapbuf_size4_0_sram[0:2]),
.sram_inv(mux_tree_tapbuf_size4_0_sram_inv[0:2]),
.sram_inv(mux_top_track_24_undriven_sram_inv[0:2]),
.out(chany_top_out[12])
);
@ -415,7 +403,7 @@ module sb_0__1_
(
.in({ chanx_right_in[0], chanx_right_in[7], chanx_right_in[14], chany_bottom_in[10] }),
.sram(mux_tree_tapbuf_size4_1_sram[0:2]),
.sram_inv(mux_tree_tapbuf_size4_1_sram_inv[0:2]),
.sram_inv(mux_top_track_32_undriven_sram_inv[0:2]),
.out(chany_top_out[16])
);
@ -425,7 +413,7 @@ module sb_0__1_
(
.in({ chany_top_in[7:8], right_bottom_grid_pin_34_[0], chany_bottom_in[8] }),
.sram(mux_tree_tapbuf_size4_2_sram[0:2]),
.sram_inv(mux_tree_tapbuf_size4_2_sram_inv[0:2]),
.sram_inv(mux_right_track_8_undriven_sram_inv[0:2]),
.out(chanx_right_out[4])
);
@ -435,7 +423,7 @@ module sb_0__1_
(
.in({ chany_top_in[9], chany_top_in[11], right_bottom_grid_pin_35_[0], chany_bottom_in[9] }),
.sram(mux_tree_tapbuf_size4_3_sram[0:2]),
.sram_inv(mux_tree_tapbuf_size4_3_sram_inv[0:2]),
.sram_inv(mux_right_track_10_undriven_sram_inv[0:2]),
.out(chanx_right_out[5])
);
@ -445,7 +433,7 @@ module sb_0__1_
(
.in({ chany_top_in[10], chany_top_in[15], right_bottom_grid_pin_36_[0], chany_bottom_in[10] }),
.sram(mux_tree_tapbuf_size4_4_sram[0:2]),
.sram_inv(mux_tree_tapbuf_size4_4_sram_inv[0:2]),
.sram_inv(mux_right_track_12_undriven_sram_inv[0:2]),
.out(chanx_right_out[6])
);
@ -455,7 +443,7 @@ module sb_0__1_
(
.in({ chany_top_in[12], chany_top_in[19], right_bottom_grid_pin_37_[0], chany_bottom_in[12] }),
.sram(mux_tree_tapbuf_size4_5_sram[0:2]),
.sram_inv(mux_tree_tapbuf_size4_5_sram_inv[0:2]),
.sram_inv(mux_right_track_14_undriven_sram_inv[0:2]),
.out(chanx_right_out[7])
);
@ -465,7 +453,7 @@ module sb_0__1_
(
.in({ chany_top_in[18], right_bottom_grid_pin_34_[0], chany_bottom_in[18:19] }),
.sram(mux_tree_tapbuf_size4_6_sram[0:2]),
.sram_inv(mux_tree_tapbuf_size4_6_sram_inv[0:2]),
.sram_inv(mux_right_track_24_undriven_sram_inv[0:2]),
.out(chanx_right_out[12])
);
@ -476,8 +464,7 @@ module sb_0__1_
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size5_mem_1_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size4_mem_0_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size4_0_sram[0:2]),
.mem_outb(mux_tree_tapbuf_size4_0_sram_inv[0:2])
.mem_out(mux_tree_tapbuf_size4_0_sram[0:2])
);
@ -487,8 +474,7 @@ module sb_0__1_
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size4_mem_0_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size4_mem_1_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size4_1_sram[0:2]),
.mem_outb(mux_tree_tapbuf_size4_1_sram_inv[0:2])
.mem_out(mux_tree_tapbuf_size4_1_sram[0:2])
);
@ -498,8 +484,7 @@ module sb_0__1_
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size7_mem_2_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size4_mem_2_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size4_2_sram[0:2]),
.mem_outb(mux_tree_tapbuf_size4_2_sram_inv[0:2])
.mem_out(mux_tree_tapbuf_size4_2_sram[0:2])
);
@ -509,8 +494,7 @@ module sb_0__1_
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size4_mem_2_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size4_mem_3_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size4_3_sram[0:2]),
.mem_outb(mux_tree_tapbuf_size4_3_sram_inv[0:2])
.mem_out(mux_tree_tapbuf_size4_3_sram[0:2])
);
@ -520,8 +504,7 @@ module sb_0__1_
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size4_mem_3_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size4_mem_4_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size4_4_sram[0:2]),
.mem_outb(mux_tree_tapbuf_size4_4_sram_inv[0:2])
.mem_out(mux_tree_tapbuf_size4_4_sram[0:2])
);
@ -531,8 +514,7 @@ module sb_0__1_
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size4_mem_4_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size4_mem_5_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size4_5_sram[0:2]),
.mem_outb(mux_tree_tapbuf_size4_5_sram_inv[0:2])
.mem_out(mux_tree_tapbuf_size4_5_sram[0:2])
);
@ -542,8 +524,7 @@ module sb_0__1_
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size3_mem_3_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size4_mem_6_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size4_6_sram[0:2]),
.mem_outb(mux_tree_tapbuf_size4_6_sram_inv[0:2])
.mem_out(mux_tree_tapbuf_size4_6_sram[0:2])
);
@ -552,7 +533,7 @@ module sb_0__1_
(
.in({ chany_top_in[0], chany_top_in[4], right_bottom_grid_pin_35_[0], right_bottom_grid_pin_37_[0], right_bottom_grid_pin_39_[0], right_bottom_grid_pin_41_[0], chany_bottom_in[4] }),
.sram(mux_tree_tapbuf_size7_0_sram[0:2]),
.sram_inv(mux_tree_tapbuf_size7_0_sram_inv[0:2]),
.sram_inv(mux_right_track_2_undriven_sram_inv[0:2]),
.out(chanx_right_out[1])
);
@ -562,7 +543,7 @@ module sb_0__1_
(
.in({ chany_top_in[1], chany_top_in[5], right_bottom_grid_pin_34_[0], right_bottom_grid_pin_36_[0], right_bottom_grid_pin_38_[0], right_bottom_grid_pin_40_[0], chany_bottom_in[5] }),
.sram(mux_tree_tapbuf_size7_1_sram[0:2]),
.sram_inv(mux_tree_tapbuf_size7_1_sram_inv[0:2]),
.sram_inv(mux_right_track_4_undriven_sram_inv[0:2]),
.out(chanx_right_out[2])
);
@ -572,7 +553,7 @@ module sb_0__1_
(
.in({ chany_top_in[3], chany_top_in[6], right_bottom_grid_pin_35_[0], right_bottom_grid_pin_37_[0], right_bottom_grid_pin_39_[0], right_bottom_grid_pin_41_[0], chany_bottom_in[6] }),
.sram(mux_tree_tapbuf_size7_2_sram[0:2]),
.sram_inv(mux_tree_tapbuf_size7_2_sram_inv[0:2]),
.sram_inv(mux_right_track_6_undriven_sram_inv[0:2]),
.out(chanx_right_out[3])
);
@ -583,8 +564,7 @@ module sb_0__1_
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size6_mem_3_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size7_mem_0_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size7_0_sram[0:2]),
.mem_outb(mux_tree_tapbuf_size7_0_sram_inv[0:2])
.mem_out(mux_tree_tapbuf_size7_0_sram[0:2])
);
@ -594,8 +574,7 @@ module sb_0__1_
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size7_mem_0_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size7_mem_1_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size7_1_sram[0:2]),
.mem_outb(mux_tree_tapbuf_size7_1_sram_inv[0:2])
.mem_out(mux_tree_tapbuf_size7_1_sram[0:2])
);
@ -605,8 +584,7 @@ module sb_0__1_
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size7_mem_1_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size7_mem_2_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size7_2_sram[0:2]),
.mem_outb(mux_tree_tapbuf_size7_2_sram_inv[0:2])
.mem_out(mux_tree_tapbuf_size7_2_sram[0:2])
);
@ -615,7 +593,7 @@ module sb_0__1_
(
.in({ chany_top_in[13], right_bottom_grid_pin_38_[0], chany_bottom_in[13] }),
.sram(mux_tree_tapbuf_size3_0_sram[0:1]),
.sram_inv(mux_tree_tapbuf_size3_0_sram_inv[0:1]),
.sram_inv(mux_right_track_16_undriven_sram_inv[0:1]),
.out(chanx_right_out[8])
);
@ -625,7 +603,7 @@ module sb_0__1_
(
.in({ chany_top_in[14], right_bottom_grid_pin_39_[0], chany_bottom_in[14] }),
.sram(mux_tree_tapbuf_size3_1_sram[0:1]),
.sram_inv(mux_tree_tapbuf_size3_1_sram_inv[0:1]),
.sram_inv(mux_right_track_18_undriven_sram_inv[0:1]),
.out(chanx_right_out[9])
);
@ -635,7 +613,7 @@ module sb_0__1_
(
.in({ chany_top_in[16], right_bottom_grid_pin_40_[0], chany_bottom_in[16] }),
.sram(mux_tree_tapbuf_size3_2_sram[0:1]),
.sram_inv(mux_tree_tapbuf_size3_2_sram_inv[0:1]),
.sram_inv(mux_right_track_20_undriven_sram_inv[0:1]),
.out(chanx_right_out[10])
);
@ -645,7 +623,7 @@ module sb_0__1_
(
.in({ chany_top_in[17], right_bottom_grid_pin_41_[0], chany_bottom_in[17] }),
.sram(mux_tree_tapbuf_size3_3_sram[0:1]),
.sram_inv(mux_tree_tapbuf_size3_3_sram_inv[0:1]),
.sram_inv(mux_right_track_22_undriven_sram_inv[0:1]),
.out(chanx_right_out[11])
);
@ -655,7 +633,7 @@ module sb_0__1_
(
.in({ chany_top_in[10], chanx_right_in[6], chanx_right_in[13] }),
.sram(mux_tree_tapbuf_size3_4_sram[0:1]),
.sram_inv(mux_tree_tapbuf_size3_4_sram_inv[0:1]),
.sram_inv(mux_bottom_track_33_undriven_sram_inv[0:1]),
.out(chany_bottom_out[16])
);
@ -666,8 +644,7 @@ module sb_0__1_
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size4_mem_5_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size3_mem_0_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size3_0_sram[0:1]),
.mem_outb(mux_tree_tapbuf_size3_0_sram_inv[0:1])
.mem_out(mux_tree_tapbuf_size3_0_sram[0:1])
);
@ -677,8 +654,7 @@ module sb_0__1_
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size3_mem_0_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size3_mem_1_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size3_1_sram[0:1]),
.mem_outb(mux_tree_tapbuf_size3_1_sram_inv[0:1])
.mem_out(mux_tree_tapbuf_size3_1_sram[0:1])
);
@ -688,8 +664,7 @@ module sb_0__1_
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size3_mem_1_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size3_mem_2_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size3_2_sram[0:1]),
.mem_outb(mux_tree_tapbuf_size3_2_sram_inv[0:1])
.mem_out(mux_tree_tapbuf_size3_2_sram[0:1])
);
@ -699,8 +674,7 @@ module sb_0__1_
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size3_mem_2_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size3_mem_3_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size3_3_sram[0:1]),
.mem_outb(mux_tree_tapbuf_size3_3_sram_inv[0:1])
.mem_out(mux_tree_tapbuf_size3_3_sram[0:1])
);
@ -710,8 +684,7 @@ module sb_0__1_
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size5_mem_4_ccff_tail[0]),
.ccff_tail(ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size3_4_sram[0:1]),
.mem_outb(mux_tree_tapbuf_size3_4_sram_inv[0:1])
.mem_out(mux_tree_tapbuf_size3_4_sram[0:1])
);
@ -720,7 +693,7 @@ module sb_0__1_
(
.in({ right_bottom_grid_pin_35_[0], chany_bottom_in[15] }),
.sram(mux_tree_tapbuf_size2_0_sram[0:1]),
.sram_inv(mux_tree_tapbuf_size2_0_sram_inv[0:1]),
.sram_inv(mux_right_track_26_undriven_sram_inv[0:1]),
.out(chanx_right_out[13])
);
@ -730,7 +703,7 @@ module sb_0__1_
(
.in({ right_bottom_grid_pin_36_[0], chany_bottom_in[11] }),
.sram(mux_tree_tapbuf_size2_1_sram[0:1]),
.sram_inv(mux_tree_tapbuf_size2_1_sram_inv[0:1]),
.sram_inv(mux_right_track_28_undriven_sram_inv[0:1]),
.out(chanx_right_out[14])
);
@ -740,7 +713,7 @@ module sb_0__1_
(
.in({ right_bottom_grid_pin_37_[0], chany_bottom_in[7] }),
.sram(mux_tree_tapbuf_size2_2_sram[0:1]),
.sram_inv(mux_tree_tapbuf_size2_2_sram_inv[0:1]),
.sram_inv(mux_right_track_30_undriven_sram_inv[0:1]),
.out(chanx_right_out[15])
);
@ -750,7 +723,7 @@ module sb_0__1_
(
.in({ right_bottom_grid_pin_38_[0], chany_bottom_in[3] }),
.sram(mux_tree_tapbuf_size2_3_sram[0:1]),
.sram_inv(mux_tree_tapbuf_size2_3_sram_inv[0:1]),
.sram_inv(mux_right_track_32_undriven_sram_inv[0:1]),
.out(chanx_right_out[16])
);
@ -760,7 +733,7 @@ module sb_0__1_
(
.in({ right_bottom_grid_pin_39_[0], chany_bottom_in[1] }),
.sram(mux_tree_tapbuf_size2_4_sram[0:1]),
.sram_inv(mux_tree_tapbuf_size2_4_sram_inv[0:1]),
.sram_inv(mux_right_track_34_undriven_sram_inv[0:1]),
.out(chanx_right_out[17])
);
@ -770,7 +743,7 @@ module sb_0__1_
(
.in({ right_bottom_grid_pin_40_[0], chany_bottom_in[0] }),
.sram(mux_tree_tapbuf_size2_5_sram[0:1]),
.sram_inv(mux_tree_tapbuf_size2_5_sram_inv[0:1]),
.sram_inv(mux_right_track_36_undriven_sram_inv[0:1]),
.out(chanx_right_out[18])
);
@ -781,8 +754,7 @@ module sb_0__1_
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size4_mem_6_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size2_mem_0_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size2_0_sram[0:1]),
.mem_outb(mux_tree_tapbuf_size2_0_sram_inv[0:1])
.mem_out(mux_tree_tapbuf_size2_0_sram[0:1])
);
@ -792,8 +764,7 @@ module sb_0__1_
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size2_mem_0_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size2_mem_1_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size2_1_sram[0:1]),
.mem_outb(mux_tree_tapbuf_size2_1_sram_inv[0:1])
.mem_out(mux_tree_tapbuf_size2_1_sram[0:1])
);
@ -803,8 +774,7 @@ module sb_0__1_
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size2_mem_1_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size2_mem_2_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size2_2_sram[0:1]),
.mem_outb(mux_tree_tapbuf_size2_2_sram_inv[0:1])
.mem_out(mux_tree_tapbuf_size2_2_sram[0:1])
);
@ -814,8 +784,7 @@ module sb_0__1_
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size2_mem_2_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size2_mem_3_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size2_3_sram[0:1]),
.mem_outb(mux_tree_tapbuf_size2_3_sram_inv[0:1])
.mem_out(mux_tree_tapbuf_size2_3_sram[0:1])
);
@ -825,8 +794,7 @@ module sb_0__1_
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size2_mem_3_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size2_mem_4_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size2_4_sram[0:1]),
.mem_outb(mux_tree_tapbuf_size2_4_sram_inv[0:1])
.mem_out(mux_tree_tapbuf_size2_4_sram[0:1])
);
@ -836,8 +804,7 @@ module sb_0__1_
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size2_mem_4_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size2_mem_5_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size2_5_sram[0:1]),
.mem_outb(mux_tree_tapbuf_size2_5_sram_inv[0:1])
.mem_out(mux_tree_tapbuf_size2_5_sram[0:1])
);

168
FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/routing/sb_0__2_.v
View File

@ -24,42 +24,48 @@ module sb_0__2_
output SC_OUT_TOP;
output SC_OUT_BOT;
wire [0:1] mux_bottom_track_1_undriven_sram_inv;
wire [0:1] mux_bottom_track_25_undriven_sram_inv;
wire [0:1] mux_bottom_track_5_undriven_sram_inv;
wire [0:1] mux_bottom_track_9_undriven_sram_inv;
wire [0:2] mux_right_track_0_undriven_sram_inv;
wire [0:1] mux_right_track_10_undriven_sram_inv;
wire [0:1] mux_right_track_12_undriven_sram_inv;
wire [0:1] mux_right_track_14_undriven_sram_inv;
wire [0:1] mux_right_track_16_undriven_sram_inv;
wire [0:1] mux_right_track_18_undriven_sram_inv;
wire [0:1] mux_right_track_20_undriven_sram_inv;
wire [0:1] mux_right_track_22_undriven_sram_inv;
wire [0:1] mux_right_track_24_undriven_sram_inv;
wire [0:1] mux_right_track_26_undriven_sram_inv;
wire [0:1] mux_right_track_28_undriven_sram_inv;
wire [0:2] mux_right_track_2_undriven_sram_inv;
wire [0:1] mux_right_track_30_undriven_sram_inv;
wire [0:1] mux_right_track_32_undriven_sram_inv;
wire [0:1] mux_right_track_34_undriven_sram_inv;
wire [0:1] mux_right_track_36_undriven_sram_inv;
wire [0:1] mux_right_track_38_undriven_sram_inv;
wire [0:2] mux_right_track_4_undriven_sram_inv;
wire [0:2] mux_right_track_6_undriven_sram_inv;
wire [0:1] mux_right_track_8_undriven_sram_inv;
wire [0:1] mux_tree_tapbuf_size2_0_sram;
wire [0:1] mux_tree_tapbuf_size2_0_sram_inv;
wire [0:1] mux_tree_tapbuf_size2_10_sram;
wire [0:1] mux_tree_tapbuf_size2_10_sram_inv;
wire [0:1] mux_tree_tapbuf_size2_11_sram;
wire [0:1] mux_tree_tapbuf_size2_11_sram_inv;
wire [0:1] mux_tree_tapbuf_size2_12_sram;
wire [0:1] mux_tree_tapbuf_size2_12_sram_inv;
wire [0:1] mux_tree_tapbuf_size2_13_sram;
wire [0:1] mux_tree_tapbuf_size2_13_sram_inv;
wire [0:1] mux_tree_tapbuf_size2_14_sram;
wire [0:1] mux_tree_tapbuf_size2_14_sram_inv;
wire [0:1] mux_tree_tapbuf_size2_15_sram;
wire [0:1] mux_tree_tapbuf_size2_15_sram_inv;
wire [0:1] mux_tree_tapbuf_size2_16_sram;
wire [0:1] mux_tree_tapbuf_size2_16_sram_inv;
wire [0:1] mux_tree_tapbuf_size2_17_sram;
wire [0:1] mux_tree_tapbuf_size2_17_sram_inv;
wire [0:1] mux_tree_tapbuf_size2_1_sram;
wire [0:1] mux_tree_tapbuf_size2_1_sram_inv;
wire [0:1] mux_tree_tapbuf_size2_2_sram;
wire [0:1] mux_tree_tapbuf_size2_2_sram_inv;
wire [0:1] mux_tree_tapbuf_size2_3_sram;
wire [0:1] mux_tree_tapbuf_size2_3_sram_inv;
wire [0:1] mux_tree_tapbuf_size2_4_sram;
wire [0:1] mux_tree_tapbuf_size2_4_sram_inv;
wire [0:1] mux_tree_tapbuf_size2_5_sram;
wire [0:1] mux_tree_tapbuf_size2_5_sram_inv;
wire [0:1] mux_tree_tapbuf_size2_6_sram;
wire [0:1] mux_tree_tapbuf_size2_6_sram_inv;
wire [0:1] mux_tree_tapbuf_size2_7_sram;
wire [0:1] mux_tree_tapbuf_size2_7_sram_inv;
wire [0:1] mux_tree_tapbuf_size2_8_sram;
wire [0:1] mux_tree_tapbuf_size2_8_sram_inv;
wire [0:1] mux_tree_tapbuf_size2_9_sram;
wire [0:1] mux_tree_tapbuf_size2_9_sram_inv;
wire [0:0] mux_tree_tapbuf_size2_mem_0_ccff_tail;
wire [0:0] mux_tree_tapbuf_size2_mem_10_ccff_tail;
wire [0:0] mux_tree_tapbuf_size2_mem_11_ccff_tail;
@ -78,21 +84,15 @@ module sb_0__2_
wire [0:0] mux_tree_tapbuf_size2_mem_8_ccff_tail;
wire [0:0] mux_tree_tapbuf_size2_mem_9_ccff_tail;
wire [0:1] mux_tree_tapbuf_size3_0_sram;
wire [0:1] mux_tree_tapbuf_size3_0_sram_inv;
wire [0:1] mux_tree_tapbuf_size3_1_sram;
wire [0:1] mux_tree_tapbuf_size3_1_sram_inv;
wire [0:0] mux_tree_tapbuf_size3_mem_0_ccff_tail;
wire [0:0] mux_tree_tapbuf_size3_mem_1_ccff_tail;
wire [0:2] mux_tree_tapbuf_size5_0_sram;
wire [0:2] mux_tree_tapbuf_size5_0_sram_inv;
wire [0:2] mux_tree_tapbuf_size5_1_sram;
wire [0:2] mux_tree_tapbuf_size5_1_sram_inv;
wire [0:0] mux_tree_tapbuf_size5_mem_0_ccff_tail;
wire [0:0] mux_tree_tapbuf_size5_mem_1_ccff_tail;
wire [0:2] mux_tree_tapbuf_size6_0_sram;
wire [0:2] mux_tree_tapbuf_size6_0_sram_inv;
wire [0:2] mux_tree_tapbuf_size6_1_sram;
wire [0:2] mux_tree_tapbuf_size6_1_sram_inv;
wire [0:0] mux_tree_tapbuf_size6_mem_0_ccff_tail;
wire [0:0] mux_tree_tapbuf_size6_mem_1_ccff_tail;
assign chany_bottom_out[18] = chanx_right_in[0];
@ -119,7 +119,7 @@ module sb_0__2_
(
.in({ right_top_grid_pin_1_[0], right_bottom_grid_pin_35_[0], right_bottom_grid_pin_37_[0], right_bottom_grid_pin_39_[0], right_bottom_grid_pin_41_[0], chany_bottom_in[18] }),
.sram(mux_tree_tapbuf_size6_0_sram[0:2]),
.sram_inv(mux_tree_tapbuf_size6_0_sram_inv[0:2]),
.sram_inv(mux_right_track_0_undriven_sram_inv[0:2]),
.out(chanx_right_out[0])
);
@ -129,7 +129,7 @@ module sb_0__2_
(
.in({ right_top_grid_pin_1_[0], right_bottom_grid_pin_35_[0], right_bottom_grid_pin_37_[0], right_bottom_grid_pin_39_[0], right_bottom_grid_pin_41_[0], chany_bottom_in[16] }),
.sram(mux_tree_tapbuf_size6_1_sram[0:2]),
.sram_inv(mux_tree_tapbuf_size6_1_sram_inv[0:2]),
.sram_inv(mux_right_track_4_undriven_sram_inv[0:2]),
.out(chanx_right_out[2])
);
@ -140,8 +140,7 @@ module sb_0__2_
.prog_clk(prog_clk[0]),
.ccff_head(ccff_head[0]),
.ccff_tail(mux_tree_tapbuf_size6_mem_0_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size6_0_sram[0:2]),
.mem_outb(mux_tree_tapbuf_size6_0_sram_inv[0:2])
.mem_out(mux_tree_tapbuf_size6_0_sram[0:2])
);
@ -151,8 +150,7 @@ module sb_0__2_
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size5_mem_0_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size6_mem_1_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size6_1_sram[0:2]),
.mem_outb(mux_tree_tapbuf_size6_1_sram_inv[0:2])
.mem_out(mux_tree_tapbuf_size6_1_sram[0:2])
);
@ -161,7 +159,7 @@ module sb_0__2_
(
.in({ right_bottom_grid_pin_34_[0], right_bottom_grid_pin_36_[0], right_bottom_grid_pin_38_[0], right_bottom_grid_pin_40_[0], chany_bottom_in[17] }),
.sram(mux_tree_tapbuf_size5_0_sram[0:2]),
.sram_inv(mux_tree_tapbuf_size5_0_sram_inv[0:2]),
.sram_inv(mux_right_track_2_undriven_sram_inv[0:2]),
.out(chanx_right_out[1])
);
@ -171,7 +169,7 @@ module sb_0__2_
(
.in({ right_bottom_grid_pin_34_[0], right_bottom_grid_pin_36_[0], right_bottom_grid_pin_38_[0], right_bottom_grid_pin_40_[0], chany_bottom_in[15] }),
.sram(mux_tree_tapbuf_size5_1_sram[0:2]),
.sram_inv(mux_tree_tapbuf_size5_1_sram_inv[0:2]),
.sram_inv(mux_right_track_6_undriven_sram_inv[0:2]),
.out(chanx_right_out[3])
);
@ -182,8 +180,7 @@ module sb_0__2_
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size6_mem_0_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size5_mem_0_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size5_0_sram[0:2]),
.mem_outb(mux_tree_tapbuf_size5_0_sram_inv[0:2])
.mem_out(mux_tree_tapbuf_size5_0_sram[0:2])
);
@ -193,8 +190,7 @@ module sb_0__2_
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size6_mem_1_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size5_mem_1_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size5_1_sram[0:2]),
.mem_outb(mux_tree_tapbuf_size5_1_sram_inv[0:2])
.mem_out(mux_tree_tapbuf_size5_1_sram[0:2])
);
@ -203,7 +199,7 @@ module sb_0__2_
(
.in({ right_top_grid_pin_1_[0], right_bottom_grid_pin_41_[0], chany_bottom_in[14] }),
.sram(mux_tree_tapbuf_size3_0_sram[0:1]),
.sram_inv(mux_tree_tapbuf_size3_0_sram_inv[0:1]),
.sram_inv(mux_right_track_8_undriven_sram_inv[0:1]),
.out(chanx_right_out[4])
);
@ -213,7 +209,7 @@ module sb_0__2_
(
.in({ right_top_grid_pin_1_[0], right_bottom_grid_pin_41_[0], chany_bottom_in[6] }),
.sram(mux_tree_tapbuf_size3_1_sram[0:1]),
.sram_inv(mux_tree_tapbuf_size3_1_sram_inv[0:1]),
.sram_inv(mux_right_track_24_undriven_sram_inv[0:1]),
.out(chanx_right_out[12])
);
@ -224,8 +220,7 @@ module sb_0__2_
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size5_mem_1_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size3_mem_0_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size3_0_sram[0:1]),
.mem_outb(mux_tree_tapbuf_size3_0_sram_inv[0:1])
.mem_out(mux_tree_tapbuf_size3_0_sram[0:1])
);
@ -235,8 +230,7 @@ module sb_0__2_
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size2_mem_6_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size3_mem_1_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size3_1_sram[0:1]),
.mem_outb(mux_tree_tapbuf_size3_1_sram_inv[0:1])
.mem_out(mux_tree_tapbuf_size3_1_sram[0:1])
);
@ -245,7 +239,7 @@ module sb_0__2_
(
.in({ right_bottom_grid_pin_34_[0], chany_bottom_in[13] }),
.sram(mux_tree_tapbuf_size2_0_sram[0:1]),
.sram_inv(mux_tree_tapbuf_size2_0_sram_inv[0:1]),
.sram_inv(mux_right_track_10_undriven_sram_inv[0:1]),
.out(chanx_right_out[5])
);
@ -255,7 +249,7 @@ module sb_0__2_
(
.in({ right_bottom_grid_pin_35_[0], chany_bottom_in[12] }),
.sram(mux_tree_tapbuf_size2_1_sram[0:1]),
.sram_inv(mux_tree_tapbuf_size2_1_sram_inv[0:1]),
.sram_inv(mux_right_track_12_undriven_sram_inv[0:1]),
.out(chanx_right_out[6])
);
@ -265,7 +259,7 @@ module sb_0__2_
(
.in({ right_bottom_grid_pin_36_[0], chany_bottom_in[11] }),
.sram(mux_tree_tapbuf_size2_2_sram[0:1]),
.sram_inv(mux_tree_tapbuf_size2_2_sram_inv[0:1]),
.sram_inv(mux_right_track_14_undriven_sram_inv[0:1]),
.out(chanx_right_out[7])
);
@ -275,7 +269,7 @@ module sb_0__2_
(
.in({ right_bottom_grid_pin_37_[0], chany_bottom_in[10] }),
.sram(mux_tree_tapbuf_size2_3_sram[0:1]),
.sram_inv(mux_tree_tapbuf_size2_3_sram_inv[0:1]),
.sram_inv(mux_right_track_16_undriven_sram_inv[0:1]),
.out(chanx_right_out[8])
);
@ -285,7 +279,7 @@ module sb_0__2_
(
.in({ right_bottom_grid_pin_38_[0], chany_bottom_in[9] }),
.sram(mux_tree_tapbuf_size2_4_sram[0:1]),
.sram_inv(mux_tree_tapbuf_size2_4_sram_inv[0:1]),
.sram_inv(mux_right_track_18_undriven_sram_inv[0:1]),
.out(chanx_right_out[9])
);
@ -295,7 +289,7 @@ module sb_0__2_
(
.in({ right_bottom_grid_pin_39_[0], chany_bottom_in[8] }),
.sram(mux_tree_tapbuf_size2_5_sram[0:1]),
.sram_inv(mux_tree_tapbuf_size2_5_sram_inv[0:1]),
.sram_inv(mux_right_track_20_undriven_sram_inv[0:1]),
.out(chanx_right_out[10])
);
@ -305,7 +299,7 @@ module sb_0__2_
(
.in({ right_bottom_grid_pin_40_[0], chany_bottom_in[7] }),
.sram(mux_tree_tapbuf_size2_6_sram[0:1]),
.sram_inv(mux_tree_tapbuf_size2_6_sram_inv[0:1]),
.sram_inv(mux_right_track_22_undriven_sram_inv[0:1]),
.out(chanx_right_out[11])
);
@ -315,7 +309,7 @@ module sb_0__2_
(
.in({ right_bottom_grid_pin_34_[0], chany_bottom_in[5] }),
.sram(mux_tree_tapbuf_size2_7_sram[0:1]),
.sram_inv(mux_tree_tapbuf_size2_7_sram_inv[0:1]),
.sram_inv(mux_right_track_26_undriven_sram_inv[0:1]),
.out(chanx_right_out[13])
);
@ -325,7 +319,7 @@ module sb_0__2_
(
.in({ right_bottom_grid_pin_35_[0], chany_bottom_in[4] }),
.sram(mux_tree_tapbuf_size2_8_sram[0:1]),
.sram_inv(mux_tree_tapbuf_size2_8_sram_inv[0:1]),
.sram_inv(mux_right_track_28_undriven_sram_inv[0:1]),
.out(chanx_right_out[14])
);
@ -335,7 +329,7 @@ module sb_0__2_
(
.in({ right_bottom_grid_pin_36_[0], chany_bottom_in[3] }),
.sram(mux_tree_tapbuf_size2_9_sram[0:1]),
.sram_inv(mux_tree_tapbuf_size2_9_sram_inv[0:1]),
.sram_inv(mux_right_track_30_undriven_sram_inv[0:1]),
.out(chanx_right_out[15])
);
@ -345,7 +339,7 @@ module sb_0__2_
(
.in({ right_bottom_grid_pin_37_[0], chany_bottom_in[2] }),
.sram(mux_tree_tapbuf_size2_10_sram[0:1]),
.sram_inv(mux_tree_tapbuf_size2_10_sram_inv[0:1]),
.sram_inv(mux_right_track_32_undriven_sram_inv[0:1]),
.out(chanx_right_out[16])
);
@ -355,7 +349,7 @@ module sb_0__2_
(
.in({ right_bottom_grid_pin_38_[0], chany_bottom_in[1] }),
.sram(mux_tree_tapbuf_size2_11_sram[0:1]),
.sram_inv(mux_tree_tapbuf_size2_11_sram_inv[0:1]),
.sram_inv(mux_right_track_34_undriven_sram_inv[0:1]),
.out(chanx_right_out[17])
);
@ -365,7 +359,7 @@ module sb_0__2_
(
.in({ right_bottom_grid_pin_39_[0], chany_bottom_in[0] }),
.sram(mux_tree_tapbuf_size2_12_sram[0:1]),
.sram_inv(mux_tree_tapbuf_size2_12_sram_inv[0:1]),
.sram_inv(mux_right_track_36_undriven_sram_inv[0:1]),
.out(chanx_right_out[18])
);
@ -375,7 +369,7 @@ module sb_0__2_
(
.in({ right_bottom_grid_pin_40_[0], chany_bottom_in[19] }),
.sram(mux_tree_tapbuf_size2_13_sram[0:1]),
.sram_inv(mux_tree_tapbuf_size2_13_sram_inv[0:1]),
.sram_inv(mux_right_track_38_undriven_sram_inv[0:1]),
.out(chanx_right_out[19])
);
@ -385,7 +379,7 @@ module sb_0__2_
(
.in({ chanx_right_in[18], bottom_left_grid_pin_1_[0] }),
.sram(mux_tree_tapbuf_size2_14_sram[0:1]),
.sram_inv(mux_tree_tapbuf_size2_14_sram_inv[0:1]),
.sram_inv(mux_bottom_track_1_undriven_sram_inv[0:1]),
.out(chany_bottom_out[0])
);
@ -395,7 +389,7 @@ module sb_0__2_
(
.in({ chanx_right_in[16], bottom_left_grid_pin_1_[0] }),
.sram(mux_tree_tapbuf_size2_15_sram[0:1]),
.sram_inv(mux_tree_tapbuf_size2_15_sram_inv[0:1]),
.sram_inv(mux_bottom_track_5_undriven_sram_inv[0:1]),
.out(chany_bottom_out[2])
);
@ -405,7 +399,7 @@ module sb_0__2_
(
.in({ chanx_right_in[14], bottom_left_grid_pin_1_[0] }),
.sram(mux_tree_tapbuf_size2_16_sram[0:1]),
.sram_inv(mux_tree_tapbuf_size2_16_sram_inv[0:1]),
.sram_inv(mux_bottom_track_9_undriven_sram_inv[0:1]),
.out(chany_bottom_out[4])
);
@ -415,7 +409,7 @@ module sb_0__2_
(
.in({ chanx_right_in[6], bottom_left_grid_pin_1_[0] }),
.sram(mux_tree_tapbuf_size2_17_sram[0:1]),
.sram_inv(mux_tree_tapbuf_size2_17_sram_inv[0:1]),
.sram_inv(mux_bottom_track_25_undriven_sram_inv[0:1]),
.out(chany_bottom_out[12])
);
@ -426,8 +420,7 @@ module sb_0__2_
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size3_mem_0_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size2_mem_0_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size2_0_sram[0:1]),
.mem_outb(mux_tree_tapbuf_size2_0_sram_inv[0:1])
.mem_out(mux_tree_tapbuf_size2_0_sram[0:1])
);
@ -437,8 +430,7 @@ module sb_0__2_
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size2_mem_0_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size2_mem_1_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size2_1_sram[0:1]),
.mem_outb(mux_tree_tapbuf_size2_1_sram_inv[0:1])
.mem_out(mux_tree_tapbuf_size2_1_sram[0:1])
);
@ -448,8 +440,7 @@ module sb_0__2_
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size2_mem_1_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size2_mem_2_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size2_2_sram[0:1]),
.mem_outb(mux_tree_tapbuf_size2_2_sram_inv[0:1])
.mem_out(mux_tree_tapbuf_size2_2_sram[0:1])
);
@ -459,8 +450,7 @@ module sb_0__2_
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size2_mem_2_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size2_mem_3_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size2_3_sram[0:1]),
.mem_outb(mux_tree_tapbuf_size2_3_sram_inv[0:1])
.mem_out(mux_tree_tapbuf_size2_3_sram[0:1])
);
@ -470,8 +460,7 @@ module sb_0__2_
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size2_mem_3_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size2_mem_4_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size2_4_sram[0:1]),
.mem_outb(mux_tree_tapbuf_size2_4_sram_inv[0:1])
.mem_out(mux_tree_tapbuf_size2_4_sram[0:1])
);
@ -481,8 +470,7 @@ module sb_0__2_
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size2_mem_4_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size2_mem_5_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size2_5_sram[0:1]),
.mem_outb(mux_tree_tapbuf_size2_5_sram_inv[0:1])
.mem_out(mux_tree_tapbuf_size2_5_sram[0:1])
);
@ -492,8 +480,7 @@ module sb_0__2_
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size2_mem_5_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size2_mem_6_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size2_6_sram[0:1]),
.mem_outb(mux_tree_tapbuf_size2_6_sram_inv[0:1])
.mem_out(mux_tree_tapbuf_size2_6_sram[0:1])
);
@ -503,8 +490,7 @@ module sb_0__2_
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size3_mem_1_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size2_mem_7_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size2_7_sram[0:1]),
.mem_outb(mux_tree_tapbuf_size2_7_sram_inv[0:1])
.mem_out(mux_tree_tapbuf_size2_7_sram[0:1])
);
@ -514,8 +500,7 @@ module sb_0__2_
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size2_mem_7_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size2_mem_8_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size2_8_sram[0:1]),
.mem_outb(mux_tree_tapbuf_size2_8_sram_inv[0:1])
.mem_out(mux_tree_tapbuf_size2_8_sram[0:1])
);
@ -525,8 +510,7 @@ module sb_0__2_
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size2_mem_8_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size2_mem_9_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size2_9_sram[0:1]),
.mem_outb(mux_tree_tapbuf_size2_9_sram_inv[0:1])
.mem_out(mux_tree_tapbuf_size2_9_sram[0:1])
);
@ -536,8 +520,7 @@ module sb_0__2_
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size2_mem_9_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size2_mem_10_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size2_10_sram[0:1]),
.mem_outb(mux_tree_tapbuf_size2_10_sram_inv[0:1])
.mem_out(mux_tree_tapbuf_size2_10_sram[0:1])
);
@ -547,8 +530,7 @@ module sb_0__2_
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size2_mem_10_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size2_mem_11_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size2_11_sram[0:1]),
.mem_outb(mux_tree_tapbuf_size2_11_sram_inv[0:1])
.mem_out(mux_tree_tapbuf_size2_11_sram[0:1])
);
@ -558,8 +540,7 @@ module sb_0__2_
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size2_mem_11_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size2_mem_12_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size2_12_sram[0:1]),
.mem_outb(mux_tree_tapbuf_size2_12_sram_inv[0:1])
.mem_out(mux_tree_tapbuf_size2_12_sram[0:1])
);
@ -569,8 +550,7 @@ module sb_0__2_
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size2_mem_12_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size2_mem_13_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size2_13_sram[0:1]),
.mem_outb(mux_tree_tapbuf_size2_13_sram_inv[0:1])
.mem_out(mux_tree_tapbuf_size2_13_sram[0:1])
);
@ -580,8 +560,7 @@ module sb_0__2_
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size2_mem_13_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size2_mem_14_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size2_14_sram[0:1]),
.mem_outb(mux_tree_tapbuf_size2_14_sram_inv[0:1])
.mem_out(mux_tree_tapbuf_size2_14_sram[0:1])
);
@ -591,8 +570,7 @@ module sb_0__2_
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size2_mem_14_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size2_mem_15_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size2_15_sram[0:1]),
.mem_outb(mux_tree_tapbuf_size2_15_sram_inv[0:1])
.mem_out(mux_tree_tapbuf_size2_15_sram[0:1])
);
@ -602,8 +580,7 @@ module sb_0__2_
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size2_mem_15_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size2_mem_16_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size2_16_sram[0:1]),
.mem_outb(mux_tree_tapbuf_size2_16_sram_inv[0:1])
.mem_out(mux_tree_tapbuf_size2_16_sram[0:1])
);
@ -613,8 +590,7 @@ module sb_0__2_
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size2_mem_16_ccff_tail[0]),
.ccff_tail(ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size2_17_sram[0:1]),
.mem_outb(mux_tree_tapbuf_size2_17_sram_inv[0:1])
.mem_out(mux_tree_tapbuf_size2_17_sram[0:1])
);

196
FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/routing/sb_1__0_.v
View File

@ -36,29 +36,47 @@ module sb_1__0_
output SC_OUT_TOP;
output SC_OUT_BOT;
wire [0:2] mux_left_track_17_undriven_sram_inv;
wire [0:3] mux_left_track_1_undriven_sram_inv;
wire [0:2] mux_left_track_25_undriven_sram_inv;
wire [0:2] mux_left_track_33_undriven_sram_inv;
wire [0:2] mux_left_track_3_undriven_sram_inv;
wire [0:3] mux_left_track_5_undriven_sram_inv;
wire [0:2] mux_left_track_9_undriven_sram_inv;
wire [0:2] mux_right_track_0_undriven_sram_inv;
wire [0:2] mux_right_track_16_undriven_sram_inv;
wire [0:2] mux_right_track_24_undriven_sram_inv;
wire [0:3] mux_right_track_2_undriven_sram_inv;
wire [0:2] mux_right_track_32_undriven_sram_inv;
wire [0:3] mux_right_track_4_undriven_sram_inv;
wire [0:2] mux_right_track_8_undriven_sram_inv;
wire [0:3] mux_top_track_0_undriven_sram_inv;
wire [0:2] mux_top_track_10_undriven_sram_inv;
wire [0:1] mux_top_track_12_undriven_sram_inv;
wire [0:1] mux_top_track_14_undriven_sram_inv;
wire [0:1] mux_top_track_16_undriven_sram_inv;
wire [0:1] mux_top_track_18_undriven_sram_inv;
wire [0:1] mux_top_track_20_undriven_sram_inv;
wire [0:1] mux_top_track_22_undriven_sram_inv;
wire [0:1] mux_top_track_24_undriven_sram_inv;
wire [0:2] mux_top_track_2_undriven_sram_inv;
wire [0:1] mux_top_track_38_undriven_sram_inv;
wire [0:2] mux_top_track_4_undriven_sram_inv;
wire [0:2] mux_top_track_6_undriven_sram_inv;
wire [0:2] mux_top_track_8_undriven_sram_inv;
wire [0:3] mux_tree_tapbuf_size11_0_sram;
wire [0:3] mux_tree_tapbuf_size11_0_sram_inv;
wire [0:3] mux_tree_tapbuf_size11_1_sram;
wire [0:3] mux_tree_tapbuf_size11_1_sram_inv;
wire [0:0] mux_tree_tapbuf_size11_mem_0_ccff_tail;
wire [0:0] mux_tree_tapbuf_size11_mem_1_ccff_tail;
wire [0:1] mux_tree_tapbuf_size2_0_sram;
wire [0:1] mux_tree_tapbuf_size2_0_sram_inv;
wire [0:0] mux_tree_tapbuf_size2_mem_0_ccff_tail;
wire [0:1] mux_tree_tapbuf_size3_0_sram;
wire [0:1] mux_tree_tapbuf_size3_0_sram_inv;
wire [0:1] mux_tree_tapbuf_size3_1_sram;
wire [0:1] mux_tree_tapbuf_size3_1_sram_inv;
wire [0:1] mux_tree_tapbuf_size3_2_sram;
wire [0:1] mux_tree_tapbuf_size3_2_sram_inv;
wire [0:1] mux_tree_tapbuf_size3_3_sram;
wire [0:1] mux_tree_tapbuf_size3_3_sram_inv;
wire [0:1] mux_tree_tapbuf_size3_4_sram;
wire [0:1] mux_tree_tapbuf_size3_4_sram_inv;
wire [0:1] mux_tree_tapbuf_size3_5_sram;
wire [0:1] mux_tree_tapbuf_size3_5_sram_inv;
wire [0:1] mux_tree_tapbuf_size3_6_sram;
wire [0:1] mux_tree_tapbuf_size3_6_sram_inv;
wire [0:0] mux_tree_tapbuf_size3_mem_0_ccff_tail;
wire [0:0] mux_tree_tapbuf_size3_mem_1_ccff_tail;
wire [0:0] mux_tree_tapbuf_size3_mem_2_ccff_tail;
@ -67,40 +85,25 @@ module sb_1__0_
wire [0:0] mux_tree_tapbuf_size3_mem_5_ccff_tail;
wire [0:0] mux_tree_tapbuf_size3_mem_6_ccff_tail;
wire [0:2] mux_tree_tapbuf_size4_0_sram;
wire [0:2] mux_tree_tapbuf_size4_0_sram_inv;
wire [0:2] mux_tree_tapbuf_size4_1_sram;
wire [0:2] mux_tree_tapbuf_size4_1_sram_inv;
wire [0:0] mux_tree_tapbuf_size4_mem_0_ccff_tail;
wire [0:0] mux_tree_tapbuf_size4_mem_1_ccff_tail;
wire [0:2] mux_tree_tapbuf_size5_0_sram;
wire [0:2] mux_tree_tapbuf_size5_0_sram_inv;
wire [0:2] mux_tree_tapbuf_size5_1_sram;
wire [0:2] mux_tree_tapbuf_size5_1_sram_inv;
wire [0:0] mux_tree_tapbuf_size5_mem_0_ccff_tail;
wire [0:2] mux_tree_tapbuf_size6_0_sram;
wire [0:2] mux_tree_tapbuf_size6_0_sram_inv;
wire [0:2] mux_tree_tapbuf_size6_1_sram;
wire [0:2] mux_tree_tapbuf_size6_1_sram_inv;
wire [0:0] mux_tree_tapbuf_size6_mem_0_ccff_tail;
wire [0:0] mux_tree_tapbuf_size6_mem_1_ccff_tail;
wire [0:2] mux_tree_tapbuf_size7_0_sram;
wire [0:2] mux_tree_tapbuf_size7_0_sram_inv;
wire [0:2] mux_tree_tapbuf_size7_1_sram;
wire [0:2] mux_tree_tapbuf_size7_1_sram_inv;
wire [0:2] mux_tree_tapbuf_size7_2_sram;
wire [0:2] mux_tree_tapbuf_size7_2_sram_inv;
wire [0:2] mux_tree_tapbuf_size7_3_sram;
wire [0:2] mux_tree_tapbuf_size7_3_sram_inv;
wire [0:2] mux_tree_tapbuf_size7_4_sram;
wire [0:2] mux_tree_tapbuf_size7_4_sram_inv;
wire [0:2] mux_tree_tapbuf_size7_5_sram;
wire [0:2] mux_tree_tapbuf_size7_5_sram_inv;
wire [0:2] mux_tree_tapbuf_size7_6_sram;
wire [0:2] mux_tree_tapbuf_size7_6_sram_inv;
wire [0:2] mux_tree_tapbuf_size7_7_sram;
wire [0:2] mux_tree_tapbuf_size7_7_sram_inv;
wire [0:2] mux_tree_tapbuf_size7_8_sram;
wire [0:2] mux_tree_tapbuf_size7_8_sram_inv;
wire [0:0] mux_tree_tapbuf_size7_mem_0_ccff_tail;
wire [0:0] mux_tree_tapbuf_size7_mem_1_ccff_tail;
wire [0:0] mux_tree_tapbuf_size7_mem_2_ccff_tail;
@ -111,11 +114,8 @@ module sb_1__0_
wire [0:0] mux_tree_tapbuf_size7_mem_7_ccff_tail;
wire [0:0] mux_tree_tapbuf_size7_mem_8_ccff_tail;
wire [0:3] mux_tree_tapbuf_size8_0_sram;
wire [0:3] mux_tree_tapbuf_size8_0_sram_inv;
wire [0:3] mux_tree_tapbuf_size8_1_sram;
wire [0:3] mux_tree_tapbuf_size8_1_sram_inv;
wire [0:3] mux_tree_tapbuf_size8_2_sram;
wire [0:3] mux_tree_tapbuf_size8_2_sram_inv;
wire [0:0] mux_tree_tapbuf_size8_mem_0_ccff_tail;
wire [0:0] mux_tree_tapbuf_size8_mem_1_ccff_tail;
wire [0:0] mux_tree_tapbuf_size8_mem_2_ccff_tail;
@ -159,7 +159,7 @@ module sb_1__0_
(
.in({ top_left_grid_pin_42_[0], top_left_grid_pin_44_[0], top_left_grid_pin_46_[0], top_left_grid_pin_48_[0], chanx_right_in[1:2], chanx_left_in[0], chanx_left_in[2] }),
.sram(mux_tree_tapbuf_size8_0_sram[0:3]),
.sram_inv(mux_tree_tapbuf_size8_0_sram_inv[0:3]),
.sram_inv(mux_top_track_0_undriven_sram_inv[0:3]),
.out(chany_top_out[0])
);
@ -169,7 +169,7 @@ module sb_1__0_
(
.in({ chany_top_in[0], chany_top_in[7], chany_top_in[14], right_bottom_grid_pin_3_[0], right_bottom_grid_pin_7_[0], right_bottom_grid_pin_11_[0], chanx_left_in[4], chanx_left_in[13] }),
.sram(mux_tree_tapbuf_size8_1_sram[0:3]),
.sram_inv(mux_tree_tapbuf_size8_1_sram_inv[0:3]),
.sram_inv(mux_right_track_2_undriven_sram_inv[0:3]),
.out(chanx_right_out[1])
);
@ -179,7 +179,7 @@ module sb_1__0_
(
.in({ chany_top_in[0], chany_top_in[7], chany_top_in[14], chanx_right_in[2], chanx_right_in[12], left_bottom_grid_pin_1_[0], left_bottom_grid_pin_5_[0], left_bottom_grid_pin_9_[0] }),
.sram(mux_tree_tapbuf_size8_2_sram[0:3]),
.sram_inv(mux_tree_tapbuf_size8_2_sram_inv[0:3]),
.sram_inv(mux_left_track_1_undriven_sram_inv[0:3]),
.out(chanx_left_out[0])
);
@ -190,8 +190,7 @@ module sb_1__0_
.prog_clk(prog_clk[0]),
.ccff_head(ccff_head[0]),
.ccff_tail(mux_tree_tapbuf_size8_mem_0_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size8_0_sram[0:3]),
.mem_outb(mux_tree_tapbuf_size8_0_sram_inv[0:3])
.mem_out(mux_tree_tapbuf_size8_0_sram[0:3])
);
@ -201,8 +200,7 @@ module sb_1__0_
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size7_mem_3_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size8_mem_1_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size8_1_sram[0:3]),
.mem_outb(mux_tree_tapbuf_size8_1_sram_inv[0:3])
.mem_out(mux_tree_tapbuf_size8_1_sram[0:3])
);
@ -212,8 +210,7 @@ module sb_1__0_
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size5_mem_0_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size8_mem_2_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size8_2_sram[0:3]),
.mem_outb(mux_tree_tapbuf_size8_2_sram_inv[0:3])
.mem_out(mux_tree_tapbuf_size8_2_sram[0:3])
);
@ -222,7 +219,7 @@ module sb_1__0_
(
.in({ top_left_grid_pin_43_[0], top_left_grid_pin_45_[0], top_left_grid_pin_47_[0], top_left_grid_pin_49_[0], chanx_right_in[3:4], chanx_left_in[4] }),
.sram(mux_tree_tapbuf_size7_0_sram[0:2]),
.sram_inv(mux_tree_tapbuf_size7_0_sram_inv[0:2]),
.sram_inv(mux_top_track_2_undriven_sram_inv[0:2]),
.out(chany_top_out[1])
);
@ -232,7 +229,7 @@ module sb_1__0_
(
.in({ top_left_grid_pin_42_[0], top_left_grid_pin_44_[0], top_left_grid_pin_46_[0], top_left_grid_pin_48_[0], chanx_right_in[5], chanx_right_in[7], chanx_left_in[5] }),
.sram(mux_tree_tapbuf_size7_1_sram[0:2]),
.sram_inv(mux_tree_tapbuf_size7_1_sram_inv[0:2]),
.sram_inv(mux_top_track_4_undriven_sram_inv[0:2]),
.out(chany_top_out[2])
);
@ -242,7 +239,7 @@ module sb_1__0_
(
.in({ top_left_grid_pin_43_[0], top_left_grid_pin_45_[0], top_left_grid_pin_47_[0], top_left_grid_pin_49_[0], chanx_right_in[6], chanx_right_in[11], chanx_left_in[6] }),
.sram(mux_tree_tapbuf_size7_2_sram[0:2]),
.sram_inv(mux_tree_tapbuf_size7_2_sram_inv[0:2]),
.sram_inv(mux_top_track_6_undriven_sram_inv[0:2]),
.out(chany_top_out[3])
);
@ -252,7 +249,7 @@ module sb_1__0_
(
.in({ chany_top_in[6], chany_top_in[13], right_bottom_grid_pin_1_[0], right_bottom_grid_pin_5_[0], right_bottom_grid_pin_9_[0], chanx_left_in[2], chanx_left_in[12] }),
.sram(mux_tree_tapbuf_size7_3_sram[0:2]),
.sram_inv(mux_tree_tapbuf_size7_3_sram_inv[0:2]),
.sram_inv(mux_right_track_0_undriven_sram_inv[0:2]),
.out(chanx_right_out[0])
);
@ -262,7 +259,7 @@ module sb_1__0_
(
.in({ chany_top_in[2], chany_top_in[9], chany_top_in[16], right_bottom_grid_pin_1_[0], right_bottom_grid_pin_9_[0], chanx_left_in[6], chanx_left_in[16] }),
.sram(mux_tree_tapbuf_size7_4_sram[0:2]),
.sram_inv(mux_tree_tapbuf_size7_4_sram_inv[0:2]),
.sram_inv(mux_right_track_8_undriven_sram_inv[0:2]),
.out(chanx_right_out[4])
);
@ -272,7 +269,7 @@ module sb_1__0_
(
.in({ chany_top_in[3], chany_top_in[10], chany_top_in[17], right_bottom_grid_pin_3_[0], right_bottom_grid_pin_11_[0], chanx_left_in[8], chanx_left_in[17] }),
.sram(mux_tree_tapbuf_size7_5_sram[0:2]),
.sram_inv(mux_tree_tapbuf_size7_5_sram_inv[0:2]),
.sram_inv(mux_right_track_16_undriven_sram_inv[0:2]),
.out(chanx_right_out[8])
);
@ -282,7 +279,7 @@ module sb_1__0_
(
.in({ chany_top_in[6], chany_top_in[13], chanx_right_in[4], chanx_right_in[13], left_bottom_grid_pin_3_[0], left_bottom_grid_pin_7_[0], left_bottom_grid_pin_11_[0] }),
.sram(mux_tree_tapbuf_size7_6_sram[0:2]),
.sram_inv(mux_tree_tapbuf_size7_6_sram_inv[0:2]),
.sram_inv(mux_left_track_3_undriven_sram_inv[0:2]),
.out(chanx_left_out[1])
);
@ -292,7 +289,7 @@ module sb_1__0_
(
.in({ chany_top_in[4], chany_top_in[11], chany_top_in[18], chanx_right_in[6], chanx_right_in[16], left_bottom_grid_pin_1_[0], left_bottom_grid_pin_9_[0] }),
.sram(mux_tree_tapbuf_size7_7_sram[0:2]),
.sram_inv(mux_tree_tapbuf_size7_7_sram_inv[0:2]),
.sram_inv(mux_left_track_9_undriven_sram_inv[0:2]),
.out(chanx_left_out[4])
);
@ -302,7 +299,7 @@ module sb_1__0_
(
.in({ chany_top_in[3], chany_top_in[10], chany_top_in[17], chanx_right_in[8], chanx_right_in[17], left_bottom_grid_pin_3_[0], left_bottom_grid_pin_11_[0] }),
.sram(mux_tree_tapbuf_size7_8_sram[0:2]),
.sram_inv(mux_tree_tapbuf_size7_8_sram_inv[0:2]),
.sram_inv(mux_left_track_17_undriven_sram_inv[0:2]),
.out(chanx_left_out[8])
);
@ -313,8 +310,7 @@ module sb_1__0_
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size8_mem_0_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size7_mem_0_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size7_0_sram[0:2]),
.mem_outb(mux_tree_tapbuf_size7_0_sram_inv[0:2])
.mem_out(mux_tree_tapbuf_size7_0_sram[0:2])
);
@ -324,8 +320,7 @@ module sb_1__0_
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size7_mem_0_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size7_mem_1_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size7_1_sram[0:2]),
.mem_outb(mux_tree_tapbuf_size7_1_sram_inv[0:2])
.mem_out(mux_tree_tapbuf_size7_1_sram[0:2])
);
@ -335,8 +330,7 @@ module sb_1__0_
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size7_mem_1_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size7_mem_2_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size7_2_sram[0:2]),
.mem_outb(mux_tree_tapbuf_size7_2_sram_inv[0:2])
.mem_out(mux_tree_tapbuf_size7_2_sram[0:2])
);
@ -346,8 +340,7 @@ module sb_1__0_
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size2_mem_0_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size7_mem_3_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size7_3_sram[0:2]),
.mem_outb(mux_tree_tapbuf_size7_3_sram_inv[0:2])
.mem_out(mux_tree_tapbuf_size7_3_sram[0:2])
);
@ -357,8 +350,7 @@ module sb_1__0_
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size11_mem_0_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size7_mem_4_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size7_4_sram[0:2]),
.mem_outb(mux_tree_tapbuf_size7_4_sram_inv[0:2])
.mem_out(mux_tree_tapbuf_size7_4_sram[0:2])
);
@ -368,8 +360,7 @@ module sb_1__0_
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size7_mem_4_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size7_mem_5_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size7_5_sram[0:2]),
.mem_outb(mux_tree_tapbuf_size7_5_sram_inv[0:2])
.mem_out(mux_tree_tapbuf_size7_5_sram[0:2])
);
@ -379,8 +370,7 @@ module sb_1__0_
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size8_mem_2_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size7_mem_6_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size7_6_sram[0:2]),
.mem_outb(mux_tree_tapbuf_size7_6_sram_inv[0:2])
.mem_out(mux_tree_tapbuf_size7_6_sram[0:2])
);
@ -390,8 +380,7 @@ module sb_1__0_
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size11_mem_1_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size7_mem_7_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size7_7_sram[0:2]),
.mem_outb(mux_tree_tapbuf_size7_7_sram_inv[0:2])
.mem_out(mux_tree_tapbuf_size7_7_sram[0:2])
);
@ -401,8 +390,7 @@ module sb_1__0_
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size7_mem_7_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size7_mem_8_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size7_8_sram[0:2]),
.mem_outb(mux_tree_tapbuf_size7_8_sram_inv[0:2])
.mem_out(mux_tree_tapbuf_size7_8_sram[0:2])
);
@ -411,7 +399,7 @@ module sb_1__0_
(
.in({ top_left_grid_pin_42_[0], chanx_right_in[8], chanx_right_in[15], chanx_left_in[8] }),
.sram(mux_tree_tapbuf_size4_0_sram[0:2]),
.sram_inv(mux_tree_tapbuf_size4_0_sram_inv[0:2]),
.sram_inv(mux_top_track_8_undriven_sram_inv[0:2]),
.out(chany_top_out[4])
);
@ -421,7 +409,7 @@ module sb_1__0_
(
.in({ top_left_grid_pin_43_[0], chanx_right_in[9], chanx_right_in[19], chanx_left_in[9] }),
.sram(mux_tree_tapbuf_size4_1_sram[0:2]),
.sram_inv(mux_tree_tapbuf_size4_1_sram_inv[0:2]),
.sram_inv(mux_top_track_10_undriven_sram_inv[0:2]),
.out(chany_top_out[5])
);
@ -432,8 +420,7 @@ module sb_1__0_
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size7_mem_2_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size4_mem_0_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size4_0_sram[0:2]),
.mem_outb(mux_tree_tapbuf_size4_0_sram_inv[0:2])
.mem_out(mux_tree_tapbuf_size4_0_sram[0:2])
);
@ -443,8 +430,7 @@ module sb_1__0_
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size4_mem_0_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size4_mem_1_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size4_1_sram[0:2]),
.mem_outb(mux_tree_tapbuf_size4_1_sram_inv[0:2])
.mem_out(mux_tree_tapbuf_size4_1_sram[0:2])
);
@ -453,7 +439,7 @@ module sb_1__0_
(
.in({ top_left_grid_pin_44_[0], chanx_right_in[10], chanx_left_in[10] }),
.sram(mux_tree_tapbuf_size3_0_sram[0:1]),
.sram_inv(mux_tree_tapbuf_size3_0_sram_inv[0:1]),
.sram_inv(mux_top_track_12_undriven_sram_inv[0:1]),
.out(chany_top_out[6])
);
@ -463,7 +449,7 @@ module sb_1__0_
(
.in({ top_left_grid_pin_45_[0], chanx_right_in[12], chanx_left_in[12] }),
.sram(mux_tree_tapbuf_size3_1_sram[0:1]),
.sram_inv(mux_tree_tapbuf_size3_1_sram_inv[0:1]),
.sram_inv(mux_top_track_14_undriven_sram_inv[0:1]),
.out(chany_top_out[7])
);
@ -473,7 +459,7 @@ module sb_1__0_
(
.in({ top_left_grid_pin_46_[0], chanx_right_in[13], chanx_left_in[13] }),
.sram(mux_tree_tapbuf_size3_2_sram[0:1]),
.sram_inv(mux_tree_tapbuf_size3_2_sram_inv[0:1]),
.sram_inv(mux_top_track_16_undriven_sram_inv[0:1]),
.out(chany_top_out[8])
);
@ -483,7 +469,7 @@ module sb_1__0_
(
.in({ top_left_grid_pin_47_[0], chanx_right_in[14], chanx_left_in[14] }),
.sram(mux_tree_tapbuf_size3_3_sram[0:1]),
.sram_inv(mux_tree_tapbuf_size3_3_sram_inv[0:1]),
.sram_inv(mux_top_track_18_undriven_sram_inv[0:1]),
.out(chany_top_out[9])
);
@ -493,7 +479,7 @@ module sb_1__0_
(
.in({ top_left_grid_pin_48_[0], chanx_right_in[16], chanx_left_in[16] }),
.sram(mux_tree_tapbuf_size3_4_sram[0:1]),
.sram_inv(mux_tree_tapbuf_size3_4_sram_inv[0:1]),
.sram_inv(mux_top_track_20_undriven_sram_inv[0:1]),
.out(chany_top_out[10])
);
@ -503,7 +489,7 @@ module sb_1__0_
(
.in({ top_left_grid_pin_49_[0], chanx_right_in[17], chanx_left_in[17] }),
.sram(mux_tree_tapbuf_size3_5_sram[0:1]),
.sram_inv(mux_tree_tapbuf_size3_5_sram_inv[0:1]),
.sram_inv(mux_top_track_22_undriven_sram_inv[0:1]),
.out(chany_top_out[11])
);
@ -513,7 +499,7 @@ module sb_1__0_
(
.in({ top_left_grid_pin_42_[0], chanx_right_in[18], chanx_left_in[18] }),
.sram(mux_tree_tapbuf_size3_6_sram[0:1]),
.sram_inv(mux_tree_tapbuf_size3_6_sram_inv[0:1]),
.sram_inv(mux_top_track_24_undriven_sram_inv[0:1]),
.out(chany_top_out[12])
);
@ -524,8 +510,7 @@ module sb_1__0_
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size4_mem_1_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size3_mem_0_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size3_0_sram[0:1]),
.mem_outb(mux_tree_tapbuf_size3_0_sram_inv[0:1])
.mem_out(mux_tree_tapbuf_size3_0_sram[0:1])
);
@ -535,8 +520,7 @@ module sb_1__0_
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size3_mem_0_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size3_mem_1_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size3_1_sram[0:1]),
.mem_outb(mux_tree_tapbuf_size3_1_sram_inv[0:1])
.mem_out(mux_tree_tapbuf_size3_1_sram[0:1])
);
@ -546,8 +530,7 @@ module sb_1__0_
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size3_mem_1_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size3_mem_2_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size3_2_sram[0:1]),
.mem_outb(mux_tree_tapbuf_size3_2_sram_inv[0:1])
.mem_out(mux_tree_tapbuf_size3_2_sram[0:1])
);
@ -557,8 +540,7 @@ module sb_1__0_
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size3_mem_2_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size3_mem_3_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size3_3_sram[0:1]),
.mem_outb(mux_tree_tapbuf_size3_3_sram_inv[0:1])
.mem_out(mux_tree_tapbuf_size3_3_sram[0:1])
);
@ -568,8 +550,7 @@ module sb_1__0_
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size3_mem_3_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size3_mem_4_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size3_4_sram[0:1]),
.mem_outb(mux_tree_tapbuf_size3_4_sram_inv[0:1])
.mem_out(mux_tree_tapbuf_size3_4_sram[0:1])
);
@ -579,8 +560,7 @@ module sb_1__0_
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size3_mem_4_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size3_mem_5_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size3_5_sram[0:1]),
.mem_outb(mux_tree_tapbuf_size3_5_sram_inv[0:1])
.mem_out(mux_tree_tapbuf_size3_5_sram[0:1])
);
@ -590,8 +570,7 @@ module sb_1__0_
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size3_mem_5_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size3_mem_6_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size3_6_sram[0:1]),
.mem_outb(mux_tree_tapbuf_size3_6_sram_inv[0:1])
.mem_out(mux_tree_tapbuf_size3_6_sram[0:1])
);
@ -600,7 +579,7 @@ module sb_1__0_
(
.in({ chanx_right_in[0], chanx_left_in[1] }),
.sram(mux_tree_tapbuf_size2_0_sram[0:1]),
.sram_inv(mux_tree_tapbuf_size2_0_sram_inv[0:1]),
.sram_inv(mux_top_track_38_undriven_sram_inv[0:1]),
.out(chany_top_out[19])
);
@ -611,8 +590,7 @@ module sb_1__0_
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size3_mem_6_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size2_mem_0_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size2_0_sram[0:1]),
.mem_outb(mux_tree_tapbuf_size2_0_sram_inv[0:1])
.mem_out(mux_tree_tapbuf_size2_0_sram[0:1])
);
@ -621,7 +599,7 @@ module sb_1__0_
(
.in({ chany_top_in[1], chany_top_in[8], chany_top_in[15], right_bottom_grid_pin_1_[0], right_bottom_grid_pin_3_[0], right_bottom_grid_pin_5_[0], right_bottom_grid_pin_7_[0], right_bottom_grid_pin_9_[0], right_bottom_grid_pin_11_[0], chanx_left_in[5], chanx_left_in[14] }),
.sram(mux_tree_tapbuf_size11_0_sram[0:3]),
.sram_inv(mux_tree_tapbuf_size11_0_sram_inv[0:3]),
.sram_inv(mux_right_track_4_undriven_sram_inv[0:3]),
.out(chanx_right_out[2])
);
@ -631,7 +609,7 @@ module sb_1__0_
(
.in({ chany_top_in[5], chany_top_in[12], chany_top_in[19], chanx_right_in[5], chanx_right_in[14], left_bottom_grid_pin_1_[0], left_bottom_grid_pin_3_[0], left_bottom_grid_pin_5_[0], left_bottom_grid_pin_7_[0], left_bottom_grid_pin_9_[0], left_bottom_grid_pin_11_[0] }),
.sram(mux_tree_tapbuf_size11_1_sram[0:3]),
.sram_inv(mux_tree_tapbuf_size11_1_sram_inv[0:3]),
.sram_inv(mux_left_track_5_undriven_sram_inv[0:3]),
.out(chanx_left_out[2])
);
@ -642,8 +620,7 @@ module sb_1__0_
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size8_mem_1_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size11_mem_0_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size11_0_sram[0:3]),
.mem_outb(mux_tree_tapbuf_size11_0_sram_inv[0:3])
.mem_out(mux_tree_tapbuf_size11_0_sram[0:3])
);
@ -653,8 +630,7 @@ module sb_1__0_
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size7_mem_6_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size11_mem_1_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size11_1_sram[0:3]),
.mem_outb(mux_tree_tapbuf_size11_1_sram_inv[0:3])
.mem_out(mux_tree_tapbuf_size11_1_sram[0:3])
);
@ -663,7 +639,7 @@ module sb_1__0_
(
.in({ chany_top_in[4], chany_top_in[11], chany_top_in[18], right_bottom_grid_pin_5_[0], chanx_left_in[9], chanx_left_in[18] }),
.sram(mux_tree_tapbuf_size6_0_sram[0:2]),
.sram_inv(mux_tree_tapbuf_size6_0_sram_inv[0:2]),
.sram_inv(mux_right_track_24_undriven_sram_inv[0:2]),
.out(chanx_right_out[12])
);
@ -673,7 +649,7 @@ module sb_1__0_
(
.in({ chany_top_in[2], chany_top_in[9], chany_top_in[16], chanx_right_in[9], chanx_right_in[18], left_bottom_grid_pin_5_[0] }),
.sram(mux_tree_tapbuf_size6_1_sram[0:2]),
.sram_inv(mux_tree_tapbuf_size6_1_sram_inv[0:2]),
.sram_inv(mux_left_track_25_undriven_sram_inv[0:2]),
.out(chanx_left_out[12])
);
@ -684,8 +660,7 @@ module sb_1__0_
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size7_mem_5_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size6_mem_0_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size6_0_sram[0:2]),
.mem_outb(mux_tree_tapbuf_size6_0_sram_inv[0:2])
.mem_out(mux_tree_tapbuf_size6_0_sram[0:2])
);
@ -695,8 +670,7 @@ module sb_1__0_
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size7_mem_8_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size6_mem_1_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size6_1_sram[0:2]),
.mem_outb(mux_tree_tapbuf_size6_1_sram_inv[0:2])
.mem_out(mux_tree_tapbuf_size6_1_sram[0:2])
);
@ -705,7 +679,7 @@ module sb_1__0_
(
.in({ chany_top_in[5], chany_top_in[12], chany_top_in[19], right_bottom_grid_pin_7_[0], chanx_left_in[10] }),
.sram(mux_tree_tapbuf_size5_0_sram[0:2]),
.sram_inv(mux_tree_tapbuf_size5_0_sram_inv[0:2]),
.sram_inv(mux_right_track_32_undriven_sram_inv[0:2]),
.out(chanx_right_out[16])
);
@ -715,7 +689,7 @@ module sb_1__0_
(
.in({ chany_top_in[1], chany_top_in[8], chany_top_in[15], chanx_right_in[10], left_bottom_grid_pin_7_[0] }),
.sram(mux_tree_tapbuf_size5_1_sram[0:2]),
.sram_inv(mux_tree_tapbuf_size5_1_sram_inv[0:2]),
.sram_inv(mux_left_track_33_undriven_sram_inv[0:2]),
.out(chanx_left_out[16])
);
@ -726,8 +700,7 @@ module sb_1__0_
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size6_mem_0_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size5_mem_0_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size5_0_sram[0:2]),
.mem_outb(mux_tree_tapbuf_size5_0_sram_inv[0:2])
.mem_out(mux_tree_tapbuf_size5_0_sram[0:2])
);
@ -737,8 +710,7 @@ module sb_1__0_
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size6_mem_1_ccff_tail[0]),
.ccff_tail(ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size5_1_sram[0:2]),
.mem_outb(mux_tree_tapbuf_size5_1_sram_inv[0:2])
.mem_out(mux_tree_tapbuf_size5_1_sram[0:2])
);

196
FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/routing/sb_1__1_.v
View File

@ -46,30 +46,46 @@ module sb_1__1_
output [0:19] chanx_left_out;
output [0:0] ccff_tail;
wire [0:3] mux_bottom_track_17_undriven_sram_inv;
wire [0:3] mux_bottom_track_1_undriven_sram_inv;
wire [0:3] mux_bottom_track_25_undriven_sram_inv;
wire [0:2] mux_bottom_track_33_undriven_sram_inv;
wire [0:3] mux_bottom_track_3_undriven_sram_inv;
wire [0:4] mux_bottom_track_5_undriven_sram_inv;
wire [0:3] mux_bottom_track_9_undriven_sram_inv;
wire [0:3] mux_left_track_17_undriven_sram_inv;
wire [0:3] mux_left_track_1_undriven_sram_inv;
wire [0:3] mux_left_track_25_undriven_sram_inv;
wire [0:2] mux_left_track_33_undriven_sram_inv;
wire [0:3] mux_left_track_3_undriven_sram_inv;
wire [0:4] mux_left_track_5_undriven_sram_inv;
wire [0:3] mux_left_track_9_undriven_sram_inv;
wire [0:3] mux_right_track_0_undriven_sram_inv;
wire [0:3] mux_right_track_16_undriven_sram_inv;
wire [0:3] mux_right_track_24_undriven_sram_inv;
wire [0:3] mux_right_track_2_undriven_sram_inv;
wire [0:2] mux_right_track_32_undriven_sram_inv;
wire [0:4] mux_right_track_4_undriven_sram_inv;
wire [0:3] mux_right_track_8_undriven_sram_inv;
wire [0:3] mux_top_track_0_undriven_sram_inv;
wire [0:3] mux_top_track_16_undriven_sram_inv;
wire [0:3] mux_top_track_24_undriven_sram_inv;
wire [0:3] mux_top_track_2_undriven_sram_inv;
wire [0:2] mux_top_track_32_undriven_sram_inv;
wire [0:4] mux_top_track_4_undriven_sram_inv;
wire [0:3] mux_top_track_8_undriven_sram_inv;
wire [0:3] mux_tree_tapbuf_size10_0_sram;
wire [0:3] mux_tree_tapbuf_size10_0_sram_inv;
wire [0:3] mux_tree_tapbuf_size10_10_sram;
wire [0:3] mux_tree_tapbuf_size10_10_sram_inv;
wire [0:3] mux_tree_tapbuf_size10_11_sram;
wire [0:3] mux_tree_tapbuf_size10_11_sram_inv;
wire [0:3] mux_tree_tapbuf_size10_1_sram;
wire [0:3] mux_tree_tapbuf_size10_1_sram_inv;
wire [0:3] mux_tree_tapbuf_size10_2_sram;
wire [0:3] mux_tree_tapbuf_size10_2_sram_inv;
wire [0:3] mux_tree_tapbuf_size10_3_sram;
wire [0:3] mux_tree_tapbuf_size10_3_sram_inv;
wire [0:3] mux_tree_tapbuf_size10_4_sram;
wire [0:3] mux_tree_tapbuf_size10_4_sram_inv;
wire [0:3] mux_tree_tapbuf_size10_5_sram;
wire [0:3] mux_tree_tapbuf_size10_5_sram_inv;
wire [0:3] mux_tree_tapbuf_size10_6_sram;
wire [0:3] mux_tree_tapbuf_size10_6_sram_inv;
wire [0:3] mux_tree_tapbuf_size10_7_sram;
wire [0:3] mux_tree_tapbuf_size10_7_sram_inv;
wire [0:3] mux_tree_tapbuf_size10_8_sram;
wire [0:3] mux_tree_tapbuf_size10_8_sram_inv;
wire [0:3] mux_tree_tapbuf_size10_9_sram;
wire [0:3] mux_tree_tapbuf_size10_9_sram_inv;
wire [0:0] mux_tree_tapbuf_size10_mem_0_ccff_tail;
wire [0:0] mux_tree_tapbuf_size10_mem_10_ccff_tail;
wire [0:0] mux_tree_tapbuf_size10_mem_11_ccff_tail;
@ -83,21 +99,13 @@ module sb_1__1_
wire [0:0] mux_tree_tapbuf_size10_mem_8_ccff_tail;
wire [0:0] mux_tree_tapbuf_size10_mem_9_ccff_tail;
wire [0:3] mux_tree_tapbuf_size12_0_sram;
wire [0:3] mux_tree_tapbuf_size12_0_sram_inv;
wire [0:3] mux_tree_tapbuf_size12_1_sram;
wire [0:3] mux_tree_tapbuf_size12_1_sram_inv;
wire [0:3] mux_tree_tapbuf_size12_2_sram;
wire [0:3] mux_tree_tapbuf_size12_2_sram_inv;
wire [0:3] mux_tree_tapbuf_size12_3_sram;
wire [0:3] mux_tree_tapbuf_size12_3_sram_inv;
wire [0:3] mux_tree_tapbuf_size12_4_sram;
wire [0:3] mux_tree_tapbuf_size12_4_sram_inv;
wire [0:3] mux_tree_tapbuf_size12_5_sram;
wire [0:3] mux_tree_tapbuf_size12_5_sram_inv;
wire [0:3] mux_tree_tapbuf_size12_6_sram;
wire [0:3] mux_tree_tapbuf_size12_6_sram_inv;
wire [0:3] mux_tree_tapbuf_size12_7_sram;
wire [0:3] mux_tree_tapbuf_size12_7_sram_inv;
wire [0:0] mux_tree_tapbuf_size12_mem_0_ccff_tail;
wire [0:0] mux_tree_tapbuf_size12_mem_1_ccff_tail;
wire [0:0] mux_tree_tapbuf_size12_mem_2_ccff_tail;
@ -107,25 +115,17 @@ module sb_1__1_
wire [0:0] mux_tree_tapbuf_size12_mem_6_ccff_tail;
wire [0:0] mux_tree_tapbuf_size12_mem_7_ccff_tail;
wire [0:4] mux_tree_tapbuf_size16_0_sram;
wire [0:4] mux_tree_tapbuf_size16_0_sram_inv;
wire [0:4] mux_tree_tapbuf_size16_1_sram;
wire [0:4] mux_tree_tapbuf_size16_1_sram_inv;
wire [0:4] mux_tree_tapbuf_size16_2_sram;
wire [0:4] mux_tree_tapbuf_size16_2_sram_inv;
wire [0:4] mux_tree_tapbuf_size16_3_sram;
wire [0:4] mux_tree_tapbuf_size16_3_sram_inv;
wire [0:0] mux_tree_tapbuf_size16_mem_0_ccff_tail;
wire [0:0] mux_tree_tapbuf_size16_mem_1_ccff_tail;
wire [0:0] mux_tree_tapbuf_size16_mem_2_ccff_tail;
wire [0:0] mux_tree_tapbuf_size16_mem_3_ccff_tail;
wire [0:2] mux_tree_tapbuf_size7_0_sram;
wire [0:2] mux_tree_tapbuf_size7_0_sram_inv;
wire [0:2] mux_tree_tapbuf_size7_1_sram;
wire [0:2] mux_tree_tapbuf_size7_1_sram_inv;
wire [0:2] mux_tree_tapbuf_size7_2_sram;
wire [0:2] mux_tree_tapbuf_size7_2_sram_inv;
wire [0:2] mux_tree_tapbuf_size7_3_sram;
wire [0:2] mux_tree_tapbuf_size7_3_sram_inv;
wire [0:0] mux_tree_tapbuf_size7_mem_0_ccff_tail;
wire [0:0] mux_tree_tapbuf_size7_mem_1_ccff_tail;
wire [0:0] mux_tree_tapbuf_size7_mem_2_ccff_tail;
@ -187,7 +187,7 @@ module sb_1__1_
(
.in({ top_left_grid_pin_42_[0], top_left_grid_pin_44_[0], top_left_grid_pin_46_[0], top_left_grid_pin_48_[0], chanx_right_in[1:2], chanx_right_in[12], chany_bottom_in[2], chany_bottom_in[12], chanx_left_in[0], chanx_left_in[2], chanx_left_in[12] }),
.sram(mux_tree_tapbuf_size12_0_sram[0:3]),
.sram_inv(mux_tree_tapbuf_size12_0_sram_inv[0:3]),
.sram_inv(mux_top_track_0_undriven_sram_inv[0:3]),
.out(chany_top_out[0])
);
@ -197,7 +197,7 @@ module sb_1__1_
(
.in({ top_left_grid_pin_43_[0], top_left_grid_pin_45_[0], top_left_grid_pin_47_[0], top_left_grid_pin_49_[0], chanx_right_in[3:4], chanx_right_in[13], chany_bottom_in[4], chany_bottom_in[13], chanx_left_in[4], chanx_left_in[13], chanx_left_in[19] }),
.sram(mux_tree_tapbuf_size12_1_sram[0:3]),
.sram_inv(mux_tree_tapbuf_size12_1_sram_inv[0:3]),
.sram_inv(mux_top_track_2_undriven_sram_inv[0:3]),
.out(chany_top_out[1])
);
@ -207,7 +207,7 @@ module sb_1__1_
(
.in({ chany_top_in[2], chany_top_in[12], chany_top_in[19], right_bottom_grid_pin_34_[0], right_bottom_grid_pin_36_[0], right_bottom_grid_pin_38_[0], right_bottom_grid_pin_40_[0], chany_bottom_in[2], chany_bottom_in[12], chany_bottom_in[15], chanx_left_in[2], chanx_left_in[12] }),
.sram(mux_tree_tapbuf_size12_2_sram[0:3]),
.sram_inv(mux_tree_tapbuf_size12_2_sram_inv[0:3]),
.sram_inv(mux_right_track_0_undriven_sram_inv[0:3]),
.out(chanx_right_out[0])
);
@ -217,7 +217,7 @@ module sb_1__1_
(
.in({ chany_top_in[0], chany_top_in[4], chany_top_in[13], right_bottom_grid_pin_35_[0], right_bottom_grid_pin_37_[0], right_bottom_grid_pin_39_[0], right_bottom_grid_pin_41_[0], chany_bottom_in[4], chany_bottom_in[11], chany_bottom_in[13], chanx_left_in[4], chanx_left_in[13] }),
.sram(mux_tree_tapbuf_size12_3_sram[0:3]),
.sram_inv(mux_tree_tapbuf_size12_3_sram_inv[0:3]),
.sram_inv(mux_right_track_2_undriven_sram_inv[0:3]),
.out(chanx_right_out[1])
);
@ -227,7 +227,7 @@ module sb_1__1_
(
.in({ chany_top_in[2], chany_top_in[12], chanx_right_in[2], chanx_right_in[12], chanx_right_in[15], bottom_left_grid_pin_42_[0], bottom_left_grid_pin_44_[0], bottom_left_grid_pin_46_[0], bottom_left_grid_pin_48_[0], chanx_left_in[1:2], chanx_left_in[12] }),
.sram(mux_tree_tapbuf_size12_4_sram[0:3]),
.sram_inv(mux_tree_tapbuf_size12_4_sram_inv[0:3]),
.sram_inv(mux_bottom_track_1_undriven_sram_inv[0:3]),
.out(chany_bottom_out[0])
);
@ -237,7 +237,7 @@ module sb_1__1_
(
.in({ chany_top_in[4], chany_top_in[13], chanx_right_in[4], chanx_right_in[11], chanx_right_in[13], bottom_left_grid_pin_43_[0], bottom_left_grid_pin_45_[0], bottom_left_grid_pin_47_[0], bottom_left_grid_pin_49_[0], chanx_left_in[3:4], chanx_left_in[13] }),
.sram(mux_tree_tapbuf_size12_5_sram[0:3]),
.sram_inv(mux_tree_tapbuf_size12_5_sram_inv[0:3]),
.sram_inv(mux_bottom_track_3_undriven_sram_inv[0:3]),
.out(chany_bottom_out[1])
);
@ -247,7 +247,7 @@ module sb_1__1_
(
.in({ chany_top_in[0], chany_top_in[2], chany_top_in[12], chanx_right_in[2], chanx_right_in[12], chany_bottom_in[2], chany_bottom_in[12], chany_bottom_in[19], left_bottom_grid_pin_34_[0], left_bottom_grid_pin_36_[0], left_bottom_grid_pin_38_[0], left_bottom_grid_pin_40_[0] }),
.sram(mux_tree_tapbuf_size12_6_sram[0:3]),
.sram_inv(mux_tree_tapbuf_size12_6_sram_inv[0:3]),
.sram_inv(mux_left_track_1_undriven_sram_inv[0:3]),
.out(chanx_left_out[0])
);
@ -257,7 +257,7 @@ module sb_1__1_
(
.in({ chany_top_in[4], chany_top_in[13], chany_top_in[19], chanx_right_in[4], chanx_right_in[13], chany_bottom_in[0], chany_bottom_in[4], chany_bottom_in[13], left_bottom_grid_pin_35_[0], left_bottom_grid_pin_37_[0], left_bottom_grid_pin_39_[0], left_bottom_grid_pin_41_[0] }),
.sram(mux_tree_tapbuf_size12_7_sram[0:3]),
.sram_inv(mux_tree_tapbuf_size12_7_sram_inv[0:3]),
.sram_inv(mux_left_track_3_undriven_sram_inv[0:3]),
.out(chanx_left_out[1])
);
@ -268,8 +268,7 @@ module sb_1__1_
.prog_clk(prog_clk[0]),
.ccff_head(ccff_head[0]),
.ccff_tail(mux_tree_tapbuf_size12_mem_0_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size12_0_sram[0:3]),
.mem_outb(mux_tree_tapbuf_size12_0_sram_inv[0:3])
.mem_out(mux_tree_tapbuf_size12_0_sram[0:3])
);
@ -279,8 +278,7 @@ module sb_1__1_
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size12_mem_0_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size12_mem_1_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size12_1_sram[0:3]),
.mem_outb(mux_tree_tapbuf_size12_1_sram_inv[0:3])
.mem_out(mux_tree_tapbuf_size12_1_sram[0:3])
);
@ -290,8 +288,7 @@ module sb_1__1_
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size7_mem_0_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size12_mem_2_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size12_2_sram[0:3]),
.mem_outb(mux_tree_tapbuf_size12_2_sram_inv[0:3])
.mem_out(mux_tree_tapbuf_size12_2_sram[0:3])
);
@ -301,8 +298,7 @@ module sb_1__1_
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size12_mem_2_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size12_mem_3_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size12_3_sram[0:3]),
.mem_outb(mux_tree_tapbuf_size12_3_sram_inv[0:3])
.mem_out(mux_tree_tapbuf_size12_3_sram[0:3])
);
@ -312,8 +308,7 @@ module sb_1__1_
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size7_mem_1_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size12_mem_4_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size12_4_sram[0:3]),
.mem_outb(mux_tree_tapbuf_size12_4_sram_inv[0:3])
.mem_out(mux_tree_tapbuf_size12_4_sram[0:3])
);
@ -323,8 +318,7 @@ module sb_1__1_
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size12_mem_4_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size12_mem_5_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size12_5_sram[0:3]),
.mem_outb(mux_tree_tapbuf_size12_5_sram_inv[0:3])
.mem_out(mux_tree_tapbuf_size12_5_sram[0:3])
);
@ -334,8 +328,7 @@ module sb_1__1_
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size7_mem_2_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size12_mem_6_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size12_6_sram[0:3]),
.mem_outb(mux_tree_tapbuf_size12_6_sram_inv[0:3])
.mem_out(mux_tree_tapbuf_size12_6_sram[0:3])
);
@ -345,8 +338,7 @@ module sb_1__1_
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size12_mem_6_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size12_mem_7_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size12_7_sram[0:3]),
.mem_outb(mux_tree_tapbuf_size12_7_sram_inv[0:3])
.mem_out(mux_tree_tapbuf_size12_7_sram[0:3])
);
@ -355,7 +347,7 @@ module sb_1__1_
(
.in({ top_left_grid_pin_42_[0], top_left_grid_pin_43_[0], top_left_grid_pin_44_[0], top_left_grid_pin_45_[0], top_left_grid_pin_46_[0], top_left_grid_pin_47_[0], top_left_grid_pin_48_[0], top_left_grid_pin_49_[0], chanx_right_in[5], chanx_right_in[7], chanx_right_in[14], chany_bottom_in[5], chany_bottom_in[14], chanx_left_in[5], chanx_left_in[14:15] }),
.sram(mux_tree_tapbuf_size16_0_sram[0:4]),
.sram_inv(mux_tree_tapbuf_size16_0_sram_inv[0:4]),
.sram_inv(mux_top_track_4_undriven_sram_inv[0:4]),
.out(chany_top_out[2])
);
@ -365,7 +357,7 @@ module sb_1__1_
(
.in({ chany_top_in[1], chany_top_in[5], chany_top_in[14], right_bottom_grid_pin_34_[0], right_bottom_grid_pin_35_[0], right_bottom_grid_pin_36_[0], right_bottom_grid_pin_37_[0], right_bottom_grid_pin_38_[0], right_bottom_grid_pin_39_[0], right_bottom_grid_pin_40_[0], right_bottom_grid_pin_41_[0], chany_bottom_in[5], chany_bottom_in[7], chany_bottom_in[14], chanx_left_in[5], chanx_left_in[14] }),
.sram(mux_tree_tapbuf_size16_1_sram[0:4]),
.sram_inv(mux_tree_tapbuf_size16_1_sram_inv[0:4]),
.sram_inv(mux_right_track_4_undriven_sram_inv[0:4]),
.out(chanx_right_out[2])
);
@ -375,7 +367,7 @@ module sb_1__1_
(
.in({ chany_top_in[5], chany_top_in[14], chanx_right_in[5], chanx_right_in[7], chanx_right_in[14], bottom_left_grid_pin_42_[0], bottom_left_grid_pin_43_[0], bottom_left_grid_pin_44_[0], bottom_left_grid_pin_45_[0], bottom_left_grid_pin_46_[0], bottom_left_grid_pin_47_[0], bottom_left_grid_pin_48_[0], bottom_left_grid_pin_49_[0], chanx_left_in[5], chanx_left_in[7], chanx_left_in[14] }),
.sram(mux_tree_tapbuf_size16_2_sram[0:4]),
.sram_inv(mux_tree_tapbuf_size16_2_sram_inv[0:4]),
.sram_inv(mux_bottom_track_5_undriven_sram_inv[0:4]),
.out(chany_bottom_out[2])
);
@ -385,7 +377,7 @@ module sb_1__1_
(
.in({ chany_top_in[5], chany_top_in[14:15], chanx_right_in[5], chanx_right_in[14], chany_bottom_in[1], chany_bottom_in[5], chany_bottom_in[14], left_bottom_grid_pin_34_[0], left_bottom_grid_pin_35_[0], left_bottom_grid_pin_36_[0], left_bottom_grid_pin_37_[0], left_bottom_grid_pin_38_[0], left_bottom_grid_pin_39_[0], left_bottom_grid_pin_40_[0], left_bottom_grid_pin_41_[0] }),
.sram(mux_tree_tapbuf_size16_3_sram[0:4]),
.sram_inv(mux_tree_tapbuf_size16_3_sram_inv[0:4]),
.sram_inv(mux_left_track_5_undriven_sram_inv[0:4]),
.out(chanx_left_out[2])
);
@ -396,8 +388,7 @@ module sb_1__1_
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size12_mem_1_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size16_mem_0_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size16_0_sram[0:4]),
.mem_outb(mux_tree_tapbuf_size16_0_sram_inv[0:4])
.mem_out(mux_tree_tapbuf_size16_0_sram[0:4])
);
@ -407,8 +398,7 @@ module sb_1__1_
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size12_mem_3_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size16_mem_1_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size16_1_sram[0:4]),
.mem_outb(mux_tree_tapbuf_size16_1_sram_inv[0:4])
.mem_out(mux_tree_tapbuf_size16_1_sram[0:4])
);
@ -418,8 +408,7 @@ module sb_1__1_
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size12_mem_5_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size16_mem_2_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size16_2_sram[0:4]),
.mem_outb(mux_tree_tapbuf_size16_2_sram_inv[0:4])
.mem_out(mux_tree_tapbuf_size16_2_sram[0:4])
);
@ -429,8 +418,7 @@ module sb_1__1_
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size12_mem_7_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size16_mem_3_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size16_3_sram[0:4]),
.mem_outb(mux_tree_tapbuf_size16_3_sram_inv[0:4])
.mem_out(mux_tree_tapbuf_size16_3_sram[0:4])
);
@ -439,7 +427,7 @@ module sb_1__1_
(
.in({ top_left_grid_pin_42_[0], top_left_grid_pin_46_[0], chanx_right_in[6], chanx_right_in[11], chanx_right_in[16], chany_bottom_in[6], chany_bottom_in[16], chanx_left_in[6], chanx_left_in[11], chanx_left_in[16] }),
.sram(mux_tree_tapbuf_size10_0_sram[0:3]),
.sram_inv(mux_tree_tapbuf_size10_0_sram_inv[0:3]),
.sram_inv(mux_top_track_8_undriven_sram_inv[0:3]),
.out(chany_top_out[4])
);
@ -449,7 +437,7 @@ module sb_1__1_
(
.in({ top_left_grid_pin_43_[0], top_left_grid_pin_47_[0], chanx_right_in[8], chanx_right_in[15], chanx_right_in[17], chany_bottom_in[8], chany_bottom_in[17], chanx_left_in[7:8], chanx_left_in[17] }),
.sram(mux_tree_tapbuf_size10_1_sram[0:3]),
.sram_inv(mux_tree_tapbuf_size10_1_sram_inv[0:3]),
.sram_inv(mux_top_track_16_undriven_sram_inv[0:3]),
.out(chany_top_out[8])
);
@ -459,7 +447,7 @@ module sb_1__1_
(
.in({ top_left_grid_pin_44_[0], top_left_grid_pin_48_[0], chanx_right_in[9], chanx_right_in[18:19], chany_bottom_in[9], chany_bottom_in[18], chanx_left_in[3], chanx_left_in[9], chanx_left_in[18] }),
.sram(mux_tree_tapbuf_size10_2_sram[0:3]),
.sram_inv(mux_tree_tapbuf_size10_2_sram_inv[0:3]),
.sram_inv(mux_top_track_24_undriven_sram_inv[0:3]),
.out(chany_top_out[12])
);
@ -469,7 +457,7 @@ module sb_1__1_
(
.in({ chany_top_in[3], chany_top_in[6], chany_top_in[16], right_bottom_grid_pin_34_[0], right_bottom_grid_pin_38_[0], chany_bottom_in[3], chany_bottom_in[6], chany_bottom_in[16], chanx_left_in[6], chanx_left_in[16] }),
.sram(mux_tree_tapbuf_size10_3_sram[0:3]),
.sram_inv(mux_tree_tapbuf_size10_3_sram_inv[0:3]),
.sram_inv(mux_right_track_8_undriven_sram_inv[0:3]),
.out(chanx_right_out[4])
);
@ -479,7 +467,7 @@ module sb_1__1_
(
.in({ chany_top_in[7:8], chany_top_in[17], right_bottom_grid_pin_35_[0], right_bottom_grid_pin_39_[0], chany_bottom_in[1], chany_bottom_in[8], chany_bottom_in[17], chanx_left_in[8], chanx_left_in[17] }),
.sram(mux_tree_tapbuf_size10_4_sram[0:3]),
.sram_inv(mux_tree_tapbuf_size10_4_sram_inv[0:3]),
.sram_inv(mux_right_track_16_undriven_sram_inv[0:3]),
.out(chanx_right_out[8])
);
@ -489,7 +477,7 @@ module sb_1__1_
(
.in({ chany_top_in[9], chany_top_in[11], chany_top_in[18], right_bottom_grid_pin_36_[0], right_bottom_grid_pin_40_[0], chany_bottom_in[0], chany_bottom_in[9], chany_bottom_in[18], chanx_left_in[9], chanx_left_in[18] }),
.sram(mux_tree_tapbuf_size10_5_sram[0:3]),
.sram_inv(mux_tree_tapbuf_size10_5_sram_inv[0:3]),
.sram_inv(mux_right_track_24_undriven_sram_inv[0:3]),
.out(chanx_right_out[12])
);
@ -499,7 +487,7 @@ module sb_1__1_
(
.in({ chany_top_in[6], chany_top_in[16], chanx_right_in[3], chanx_right_in[6], chanx_right_in[16], bottom_left_grid_pin_42_[0], bottom_left_grid_pin_46_[0], chanx_left_in[6], chanx_left_in[11], chanx_left_in[16] }),
.sram(mux_tree_tapbuf_size10_6_sram[0:3]),
.sram_inv(mux_tree_tapbuf_size10_6_sram_inv[0:3]),
.sram_inv(mux_bottom_track_9_undriven_sram_inv[0:3]),
.out(chany_bottom_out[4])
);
@ -509,7 +497,7 @@ module sb_1__1_
(
.in({ chany_top_in[8], chany_top_in[17], chanx_right_in[1], chanx_right_in[8], chanx_right_in[17], bottom_left_grid_pin_43_[0], bottom_left_grid_pin_47_[0], chanx_left_in[8], chanx_left_in[15], chanx_left_in[17] }),
.sram(mux_tree_tapbuf_size10_7_sram[0:3]),
.sram_inv(mux_tree_tapbuf_size10_7_sram_inv[0:3]),
.sram_inv(mux_bottom_track_17_undriven_sram_inv[0:3]),
.out(chany_bottom_out[8])
);
@ -519,7 +507,7 @@ module sb_1__1_
(
.in({ chany_top_in[9], chany_top_in[18], chanx_right_in[0], chanx_right_in[9], chanx_right_in[18], bottom_left_grid_pin_44_[0], bottom_left_grid_pin_48_[0], chanx_left_in[9], chanx_left_in[18:19] }),
.sram(mux_tree_tapbuf_size10_8_sram[0:3]),
.sram_inv(mux_tree_tapbuf_size10_8_sram_inv[0:3]),
.sram_inv(mux_bottom_track_25_undriven_sram_inv[0:3]),
.out(chany_bottom_out[12])
);
@ -529,7 +517,7 @@ module sb_1__1_
(
.in({ chany_top_in[6], chany_top_in[11], chany_top_in[16], chanx_right_in[6], chanx_right_in[16], chany_bottom_in[3], chany_bottom_in[6], chany_bottom_in[16], left_bottom_grid_pin_34_[0], left_bottom_grid_pin_38_[0] }),
.sram(mux_tree_tapbuf_size10_9_sram[0:3]),
.sram_inv(mux_tree_tapbuf_size10_9_sram_inv[0:3]),
.sram_inv(mux_left_track_9_undriven_sram_inv[0:3]),
.out(chanx_left_out[4])
);
@ -539,7 +527,7 @@ module sb_1__1_
(
.in({ chany_top_in[7:8], chany_top_in[17], chanx_right_in[8], chanx_right_in[17], chany_bottom_in[7:8], chany_bottom_in[17], left_bottom_grid_pin_35_[0], left_bottom_grid_pin_39_[0] }),
.sram(mux_tree_tapbuf_size10_10_sram[0:3]),
.sram_inv(mux_tree_tapbuf_size10_10_sram_inv[0:3]),
.sram_inv(mux_left_track_17_undriven_sram_inv[0:3]),
.out(chanx_left_out[8])
);
@ -549,7 +537,7 @@ module sb_1__1_
(
.in({ chany_top_in[3], chany_top_in[9], chany_top_in[18], chanx_right_in[9], chanx_right_in[18], chany_bottom_in[9], chany_bottom_in[11], chany_bottom_in[18], left_bottom_grid_pin_36_[0], left_bottom_grid_pin_40_[0] }),
.sram(mux_tree_tapbuf_size10_11_sram[0:3]),
.sram_inv(mux_tree_tapbuf_size10_11_sram_inv[0:3]),
.sram_inv(mux_left_track_25_undriven_sram_inv[0:3]),
.out(chanx_left_out[12])
);
@ -560,8 +548,7 @@ module sb_1__1_
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size16_mem_0_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size10_mem_0_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size10_0_sram[0:3]),
.mem_outb(mux_tree_tapbuf_size10_0_sram_inv[0:3])
.mem_out(mux_tree_tapbuf_size10_0_sram[0:3])
);
@ -571,8 +558,7 @@ module sb_1__1_
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size10_mem_0_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size10_mem_1_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size10_1_sram[0:3]),
.mem_outb(mux_tree_tapbuf_size10_1_sram_inv[0:3])
.mem_out(mux_tree_tapbuf_size10_1_sram[0:3])
);
@ -582,8 +568,7 @@ module sb_1__1_
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size10_mem_1_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size10_mem_2_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size10_2_sram[0:3]),
.mem_outb(mux_tree_tapbuf_size10_2_sram_inv[0:3])
.mem_out(mux_tree_tapbuf_size10_2_sram[0:3])
);
@ -593,8 +578,7 @@ module sb_1__1_
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size16_mem_1_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size10_mem_3_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size10_3_sram[0:3]),
.mem_outb(mux_tree_tapbuf_size10_3_sram_inv[0:3])
.mem_out(mux_tree_tapbuf_size10_3_sram[0:3])
);
@ -604,8 +588,7 @@ module sb_1__1_
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size10_mem_3_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size10_mem_4_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size10_4_sram[0:3]),
.mem_outb(mux_tree_tapbuf_size10_4_sram_inv[0:3])
.mem_out(mux_tree_tapbuf_size10_4_sram[0:3])
);
@ -615,8 +598,7 @@ module sb_1__1_
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size10_mem_4_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size10_mem_5_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size10_5_sram[0:3]),
.mem_outb(mux_tree_tapbuf_size10_5_sram_inv[0:3])
.mem_out(mux_tree_tapbuf_size10_5_sram[0:3])
);
@ -626,8 +608,7 @@ module sb_1__1_
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size16_mem_2_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size10_mem_6_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size10_6_sram[0:3]),
.mem_outb(mux_tree_tapbuf_size10_6_sram_inv[0:3])
.mem_out(mux_tree_tapbuf_size10_6_sram[0:3])
);
@ -637,8 +618,7 @@ module sb_1__1_
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size10_mem_6_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size10_mem_7_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size10_7_sram[0:3]),
.mem_outb(mux_tree_tapbuf_size10_7_sram_inv[0:3])
.mem_out(mux_tree_tapbuf_size10_7_sram[0:3])
);
@ -648,8 +628,7 @@ module sb_1__1_
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size10_mem_7_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size10_mem_8_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size10_8_sram[0:3]),
.mem_outb(mux_tree_tapbuf_size10_8_sram_inv[0:3])
.mem_out(mux_tree_tapbuf_size10_8_sram[0:3])
);
@ -659,8 +638,7 @@ module sb_1__1_
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size16_mem_3_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size10_mem_9_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size10_9_sram[0:3]),
.mem_outb(mux_tree_tapbuf_size10_9_sram_inv[0:3])
.mem_out(mux_tree_tapbuf_size10_9_sram[0:3])
);
@ -670,8 +648,7 @@ module sb_1__1_
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size10_mem_9_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size10_mem_10_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size10_10_sram[0:3]),
.mem_outb(mux_tree_tapbuf_size10_10_sram_inv[0:3])
.mem_out(mux_tree_tapbuf_size10_10_sram[0:3])
);
@ -681,8 +658,7 @@ module sb_1__1_
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size10_mem_10_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size10_mem_11_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size10_11_sram[0:3]),
.mem_outb(mux_tree_tapbuf_size10_11_sram_inv[0:3])
.mem_out(mux_tree_tapbuf_size10_11_sram[0:3])
);
@ -691,7 +667,7 @@ module sb_1__1_
(
.in({ top_left_grid_pin_45_[0], top_left_grid_pin_49_[0], chanx_right_in[0], chanx_right_in[10], chany_bottom_in[10], chanx_left_in[1], chanx_left_in[10] }),
.sram(mux_tree_tapbuf_size7_0_sram[0:2]),
.sram_inv(mux_tree_tapbuf_size7_0_sram_inv[0:2]),
.sram_inv(mux_top_track_32_undriven_sram_inv[0:2]),
.out(chany_top_out[16])
);
@ -701,7 +677,7 @@ module sb_1__1_
(
.in({ chany_top_in[10], chany_top_in[15], right_bottom_grid_pin_37_[0], right_bottom_grid_pin_41_[0], chany_bottom_in[10], chany_bottom_in[19], chanx_left_in[10] }),
.sram(mux_tree_tapbuf_size7_1_sram[0:2]),
.sram_inv(mux_tree_tapbuf_size7_1_sram_inv[0:2]),
.sram_inv(mux_right_track_32_undriven_sram_inv[0:2]),
.out(chanx_right_out[16])
);
@ -711,7 +687,7 @@ module sb_1__1_
(
.in({ chany_top_in[10], chanx_right_in[10], chanx_right_in[19], bottom_left_grid_pin_45_[0], bottom_left_grid_pin_49_[0], chanx_left_in[0], chanx_left_in[10] }),
.sram(mux_tree_tapbuf_size7_2_sram[0:2]),
.sram_inv(mux_tree_tapbuf_size7_2_sram_inv[0:2]),
.sram_inv(mux_bottom_track_33_undriven_sram_inv[0:2]),
.out(chany_bottom_out[16])
);
@ -721,7 +697,7 @@ module sb_1__1_
(
.in({ chany_top_in[1], chany_top_in[10], chanx_right_in[10], chany_bottom_in[10], chany_bottom_in[15], left_bottom_grid_pin_37_[0], left_bottom_grid_pin_41_[0] }),
.sram(mux_tree_tapbuf_size7_3_sram[0:2]),
.sram_inv(mux_tree_tapbuf_size7_3_sram_inv[0:2]),
.sram_inv(mux_left_track_33_undriven_sram_inv[0:2]),
.out(chanx_left_out[16])
);
@ -732,8 +708,7 @@ module sb_1__1_
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size10_mem_2_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size7_mem_0_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size7_0_sram[0:2]),
.mem_outb(mux_tree_tapbuf_size7_0_sram_inv[0:2])
.mem_out(mux_tree_tapbuf_size7_0_sram[0:2])
);
@ -743,8 +718,7 @@ module sb_1__1_
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size10_mem_5_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size7_mem_1_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size7_1_sram[0:2]),
.mem_outb(mux_tree_tapbuf_size7_1_sram_inv[0:2])
.mem_out(mux_tree_tapbuf_size7_1_sram[0:2])
);
@ -754,8 +728,7 @@ module sb_1__1_
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size10_mem_8_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size7_mem_2_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size7_2_sram[0:2]),
.mem_outb(mux_tree_tapbuf_size7_2_sram_inv[0:2])
.mem_out(mux_tree_tapbuf_size7_2_sram[0:2])
);
@ -765,8 +738,7 @@ module sb_1__1_
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size10_mem_11_ccff_tail[0]),
.ccff_tail(ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size7_3_sram[0:2]),
.mem_outb(mux_tree_tapbuf_size7_3_sram_inv[0:2])
.mem_out(mux_tree_tapbuf_size7_3_sram[0:2])
);

196
FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/routing/sb_1__2_.v
View File

@ -42,30 +42,48 @@ module sb_1__2_
output SC_OUT_TOP;
output SC_OUT_BOT;
wire [0:2] mux_bottom_track_11_undriven_sram_inv;
wire [0:1] mux_bottom_track_13_undriven_sram_inv;
wire [0:1] mux_bottom_track_15_undriven_sram_inv;
wire [0:1] mux_bottom_track_17_undriven_sram_inv;
wire [0:1] mux_bottom_track_19_undriven_sram_inv;
wire [0:2] mux_bottom_track_1_undriven_sram_inv;
wire [0:1] mux_bottom_track_21_undriven_sram_inv;
wire [0:1] mux_bottom_track_23_undriven_sram_inv;
wire [0:2] mux_bottom_track_25_undriven_sram_inv;
wire [0:1] mux_bottom_track_27_undriven_sram_inv;
wire [0:2] mux_bottom_track_3_undriven_sram_inv;
wire [0:2] mux_bottom_track_5_undriven_sram_inv;
wire [0:2] mux_bottom_track_7_undriven_sram_inv;
wire [0:2] mux_bottom_track_9_undriven_sram_inv;
wire [0:2] mux_left_track_17_undriven_sram_inv;
wire [0:3] mux_left_track_1_undriven_sram_inv;
wire [0:2] mux_left_track_25_undriven_sram_inv;
wire [0:2] mux_left_track_33_undriven_sram_inv;
wire [0:3] mux_left_track_3_undriven_sram_inv;
wire [0:3] mux_left_track_5_undriven_sram_inv;
wire [0:3] mux_left_track_9_undriven_sram_inv;
wire [0:3] mux_right_track_0_undriven_sram_inv;
wire [0:2] mux_right_track_16_undriven_sram_inv;
wire [0:2] mux_right_track_24_undriven_sram_inv;
wire [0:3] mux_right_track_2_undriven_sram_inv;
wire [0:2] mux_right_track_32_undriven_sram_inv;
wire [0:3] mux_right_track_4_undriven_sram_inv;
wire [0:3] mux_right_track_8_undriven_sram_inv;
wire [0:3] mux_tree_tapbuf_size10_0_sram;
wire [0:3] mux_tree_tapbuf_size10_0_sram_inv;
wire [0:0] mux_tree_tapbuf_size10_mem_0_ccff_tail;
wire [0:3] mux_tree_tapbuf_size14_0_sram;
wire [0:3] mux_tree_tapbuf_size14_0_sram_inv;
wire [0:3] mux_tree_tapbuf_size14_1_sram;
wire [0:3] mux_tree_tapbuf_size14_1_sram_inv;
wire [0:0] mux_tree_tapbuf_size14_mem_0_ccff_tail;
wire [0:0] mux_tree_tapbuf_size14_mem_1_ccff_tail;
wire [0:1] mux_tree_tapbuf_size2_0_sram;
wire [0:1] mux_tree_tapbuf_size2_0_sram_inv;
wire [0:0] mux_tree_tapbuf_size2_mem_0_ccff_tail;
wire [0:1] mux_tree_tapbuf_size3_0_sram;
wire [0:1] mux_tree_tapbuf_size3_0_sram_inv;
wire [0:1] mux_tree_tapbuf_size3_1_sram;
wire [0:1] mux_tree_tapbuf_size3_1_sram_inv;
wire [0:1] mux_tree_tapbuf_size3_2_sram;
wire [0:1] mux_tree_tapbuf_size3_2_sram_inv;
wire [0:1] mux_tree_tapbuf_size3_3_sram;
wire [0:1] mux_tree_tapbuf_size3_3_sram_inv;
wire [0:1] mux_tree_tapbuf_size3_4_sram;
wire [0:1] mux_tree_tapbuf_size3_4_sram_inv;
wire [0:1] mux_tree_tapbuf_size3_5_sram;
wire [0:1] mux_tree_tapbuf_size3_5_sram_inv;
wire [0:0] mux_tree_tapbuf_size3_mem_0_ccff_tail;
wire [0:0] mux_tree_tapbuf_size3_mem_1_ccff_tail;
wire [0:0] mux_tree_tapbuf_size3_mem_2_ccff_tail;
@ -73,35 +91,22 @@ module sb_1__2_
wire [0:0] mux_tree_tapbuf_size3_mem_4_ccff_tail;
wire [0:0] mux_tree_tapbuf_size3_mem_5_ccff_tail;
wire [0:2] mux_tree_tapbuf_size4_0_sram;
wire [0:2] mux_tree_tapbuf_size4_0_sram_inv;
wire [0:2] mux_tree_tapbuf_size4_1_sram;
wire [0:2] mux_tree_tapbuf_size4_1_sram_inv;
wire [0:2] mux_tree_tapbuf_size4_2_sram;
wire [0:2] mux_tree_tapbuf_size4_2_sram_inv;
wire [0:0] mux_tree_tapbuf_size4_mem_0_ccff_tail;
wire [0:0] mux_tree_tapbuf_size4_mem_1_ccff_tail;
wire [0:0] mux_tree_tapbuf_size4_mem_2_ccff_tail;
wire [0:2] mux_tree_tapbuf_size5_0_sram;
wire [0:2] mux_tree_tapbuf_size5_0_sram_inv;
wire [0:0] mux_tree_tapbuf_size5_mem_0_ccff_tail;
wire [0:2] mux_tree_tapbuf_size6_0_sram;
wire [0:2] mux_tree_tapbuf_size6_0_sram_inv;
wire [0:2] mux_tree_tapbuf_size7_0_sram;
wire [0:2] mux_tree_tapbuf_size7_0_sram_inv;
wire [0:2] mux_tree_tapbuf_size7_1_sram;
wire [0:2] mux_tree_tapbuf_size7_1_sram_inv;
wire [0:2] mux_tree_tapbuf_size7_2_sram;
wire [0:2] mux_tree_tapbuf_size7_2_sram_inv;
wire [0:2] mux_tree_tapbuf_size7_3_sram;
wire [0:2] mux_tree_tapbuf_size7_3_sram_inv;
wire [0:2] mux_tree_tapbuf_size7_4_sram;
wire [0:2] mux_tree_tapbuf_size7_4_sram_inv;
wire [0:2] mux_tree_tapbuf_size7_5_sram;
wire [0:2] mux_tree_tapbuf_size7_5_sram_inv;
wire [0:2] mux_tree_tapbuf_size7_6_sram;
wire [0:2] mux_tree_tapbuf_size7_6_sram_inv;
wire [0:2] mux_tree_tapbuf_size7_7_sram;
wire [0:2] mux_tree_tapbuf_size7_7_sram_inv;
wire [0:0] mux_tree_tapbuf_size7_mem_0_ccff_tail;
wire [0:0] mux_tree_tapbuf_size7_mem_1_ccff_tail;
wire [0:0] mux_tree_tapbuf_size7_mem_2_ccff_tail;
@ -111,17 +116,12 @@ module sb_1__2_
wire [0:0] mux_tree_tapbuf_size7_mem_6_ccff_tail;
wire [0:0] mux_tree_tapbuf_size7_mem_7_ccff_tail;
wire [0:3] mux_tree_tapbuf_size8_0_sram;
wire [0:3] mux_tree_tapbuf_size8_0_sram_inv;
wire [0:3] mux_tree_tapbuf_size8_1_sram;
wire [0:3] mux_tree_tapbuf_size8_1_sram_inv;
wire [0:0] mux_tree_tapbuf_size8_mem_0_ccff_tail;
wire [0:0] mux_tree_tapbuf_size8_mem_1_ccff_tail;
wire [0:3] mux_tree_tapbuf_size9_0_sram;
wire [0:3] mux_tree_tapbuf_size9_0_sram_inv;
wire [0:3] mux_tree_tapbuf_size9_1_sram;
wire [0:3] mux_tree_tapbuf_size9_1_sram_inv;
wire [0:3] mux_tree_tapbuf_size9_2_sram;
wire [0:3] mux_tree_tapbuf_size9_2_sram_inv;
wire [0:0] mux_tree_tapbuf_size9_mem_0_ccff_tail;
wire [0:0] mux_tree_tapbuf_size9_mem_1_ccff_tail;
wire [0:0] mux_tree_tapbuf_size9_mem_2_ccff_tail;
@ -165,7 +165,7 @@ module sb_1__2_
(
.in({ right_top_grid_pin_1_[0], right_bottom_grid_pin_35_[0], right_bottom_grid_pin_37_[0], right_bottom_grid_pin_39_[0], right_bottom_grid_pin_41_[0], chany_bottom_in[5], chany_bottom_in[12], chany_bottom_in[19], chanx_left_in[2], chanx_left_in[12] }),
.sram(mux_tree_tapbuf_size10_0_sram[0:3]),
.sram_inv(mux_tree_tapbuf_size10_0_sram_inv[0:3]),
.sram_inv(mux_right_track_0_undriven_sram_inv[0:3]),
.out(chanx_right_out[0])
);
@ -176,8 +176,7 @@ module sb_1__2_
.prog_clk(prog_clk[0]),
.ccff_head(ccff_head[0]),
.ccff_tail(mux_tree_tapbuf_size10_mem_0_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size10_0_sram[0:3]),
.mem_outb(mux_tree_tapbuf_size10_0_sram_inv[0:3])
.mem_out(mux_tree_tapbuf_size10_0_sram[0:3])
);
@ -186,7 +185,7 @@ module sb_1__2_
(
.in({ right_bottom_grid_pin_34_[0], right_bottom_grid_pin_36_[0], right_bottom_grid_pin_38_[0], right_bottom_grid_pin_40_[0], chany_bottom_in[4], chany_bottom_in[11], chany_bottom_in[18], chanx_left_in[4], chanx_left_in[13] }),
.sram(mux_tree_tapbuf_size9_0_sram[0:3]),
.sram_inv(mux_tree_tapbuf_size9_0_sram_inv[0:3]),
.sram_inv(mux_right_track_2_undriven_sram_inv[0:3]),
.out(chanx_right_out[1])
);
@ -196,7 +195,7 @@ module sb_1__2_
(
.in({ chanx_right_in[2], chanx_right_in[12], chany_bottom_in[6], chany_bottom_in[13], left_top_grid_pin_1_[0], left_bottom_grid_pin_35_[0], left_bottom_grid_pin_37_[0], left_bottom_grid_pin_39_[0], left_bottom_grid_pin_41_[0] }),
.sram(mux_tree_tapbuf_size9_1_sram[0:3]),
.sram_inv(mux_tree_tapbuf_size9_1_sram_inv[0:3]),
.sram_inv(mux_left_track_1_undriven_sram_inv[0:3]),
.out(chanx_left_out[0])
);
@ -206,7 +205,7 @@ module sb_1__2_
(
.in({ chanx_right_in[4], chanx_right_in[13], chany_bottom_in[0], chany_bottom_in[7], chany_bottom_in[14], left_bottom_grid_pin_34_[0], left_bottom_grid_pin_36_[0], left_bottom_grid_pin_38_[0], left_bottom_grid_pin_40_[0] }),
.sram(mux_tree_tapbuf_size9_2_sram[0:3]),
.sram_inv(mux_tree_tapbuf_size9_2_sram_inv[0:3]),
.sram_inv(mux_left_track_3_undriven_sram_inv[0:3]),
.out(chanx_left_out[1])
);
@ -217,8 +216,7 @@ module sb_1__2_
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size10_mem_0_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size9_mem_0_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size9_0_sram[0:3]),
.mem_outb(mux_tree_tapbuf_size9_0_sram_inv[0:3])
.mem_out(mux_tree_tapbuf_size9_0_sram[0:3])
);
@ -228,8 +226,7 @@ module sb_1__2_
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size2_mem_0_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size9_mem_1_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size9_1_sram[0:3]),
.mem_outb(mux_tree_tapbuf_size9_1_sram_inv[0:3])
.mem_out(mux_tree_tapbuf_size9_1_sram[0:3])
);
@ -239,8 +236,7 @@ module sb_1__2_
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size9_mem_1_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size9_mem_2_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size9_2_sram[0:3]),
.mem_outb(mux_tree_tapbuf_size9_2_sram_inv[0:3])
.mem_out(mux_tree_tapbuf_size9_2_sram[0:3])
);
@ -249,7 +245,7 @@ module sb_1__2_
(
.in({ right_top_grid_pin_1_[0], right_bottom_grid_pin_34_[0], right_bottom_grid_pin_35_[0], right_bottom_grid_pin_36_[0], right_bottom_grid_pin_37_[0], right_bottom_grid_pin_38_[0], right_bottom_grid_pin_39_[0], right_bottom_grid_pin_40_[0], right_bottom_grid_pin_41_[0], chany_bottom_in[3], chany_bottom_in[10], chany_bottom_in[17], chanx_left_in[5], chanx_left_in[14] }),
.sram(mux_tree_tapbuf_size14_0_sram[0:3]),
.sram_inv(mux_tree_tapbuf_size14_0_sram_inv[0:3]),
.sram_inv(mux_right_track_4_undriven_sram_inv[0:3]),
.out(chanx_right_out[2])
);
@ -259,7 +255,7 @@ module sb_1__2_
(
.in({ chanx_right_in[5], chanx_right_in[14], chany_bottom_in[1], chany_bottom_in[8], chany_bottom_in[15], left_top_grid_pin_1_[0], left_bottom_grid_pin_34_[0], left_bottom_grid_pin_35_[0], left_bottom_grid_pin_36_[0], left_bottom_grid_pin_37_[0], left_bottom_grid_pin_38_[0], left_bottom_grid_pin_39_[0], left_bottom_grid_pin_40_[0], left_bottom_grid_pin_41_[0] }),
.sram(mux_tree_tapbuf_size14_1_sram[0:3]),
.sram_inv(mux_tree_tapbuf_size14_1_sram_inv[0:3]),
.sram_inv(mux_left_track_5_undriven_sram_inv[0:3]),
.out(chanx_left_out[2])
);
@ -270,8 +266,7 @@ module sb_1__2_
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size9_mem_0_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size14_mem_0_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size14_0_sram[0:3]),
.mem_outb(mux_tree_tapbuf_size14_0_sram_inv[0:3])
.mem_out(mux_tree_tapbuf_size14_0_sram[0:3])
);
@ -281,8 +276,7 @@ module sb_1__2_
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size9_mem_2_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size14_mem_1_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size14_1_sram[0:3]),
.mem_outb(mux_tree_tapbuf_size14_1_sram_inv[0:3])
.mem_out(mux_tree_tapbuf_size14_1_sram[0:3])
);
@ -291,7 +285,7 @@ module sb_1__2_
(
.in({ right_top_grid_pin_1_[0], right_bottom_grid_pin_37_[0], right_bottom_grid_pin_41_[0], chany_bottom_in[2], chany_bottom_in[9], chany_bottom_in[16], chanx_left_in[6], chanx_left_in[16] }),
.sram(mux_tree_tapbuf_size8_0_sram[0:3]),
.sram_inv(mux_tree_tapbuf_size8_0_sram_inv[0:3]),
.sram_inv(mux_right_track_8_undriven_sram_inv[0:3]),
.out(chanx_right_out[4])
);
@ -301,7 +295,7 @@ module sb_1__2_
(
.in({ chanx_right_in[6], chanx_right_in[16], chany_bottom_in[2], chany_bottom_in[9], chany_bottom_in[16], left_top_grid_pin_1_[0], left_bottom_grid_pin_37_[0], left_bottom_grid_pin_41_[0] }),
.sram(mux_tree_tapbuf_size8_1_sram[0:3]),
.sram_inv(mux_tree_tapbuf_size8_1_sram_inv[0:3]),
.sram_inv(mux_left_track_9_undriven_sram_inv[0:3]),
.out(chanx_left_out[4])
);
@ -312,8 +306,7 @@ module sb_1__2_
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size14_mem_0_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size8_mem_0_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size8_0_sram[0:3]),
.mem_outb(mux_tree_tapbuf_size8_0_sram_inv[0:3])
.mem_out(mux_tree_tapbuf_size8_0_sram[0:3])
);
@ -323,8 +316,7 @@ module sb_1__2_
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size14_mem_1_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size8_mem_1_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size8_1_sram[0:3]),
.mem_outb(mux_tree_tapbuf_size8_1_sram_inv[0:3])
.mem_out(mux_tree_tapbuf_size8_1_sram[0:3])
);
@ -333,7 +325,7 @@ module sb_1__2_
(
.in({ right_bottom_grid_pin_34_[0], right_bottom_grid_pin_38_[0], chany_bottom_in[1], chany_bottom_in[8], chany_bottom_in[15], chanx_left_in[8], chanx_left_in[17] }),
.sram(mux_tree_tapbuf_size7_0_sram[0:2]),
.sram_inv(mux_tree_tapbuf_size7_0_sram_inv[0:2]),
.sram_inv(mux_right_track_16_undriven_sram_inv[0:2]),
.out(chanx_right_out[8])
);
@ -343,7 +335,7 @@ module sb_1__2_
(
.in({ right_bottom_grid_pin_35_[0], right_bottom_grid_pin_39_[0], chany_bottom_in[0], chany_bottom_in[7], chany_bottom_in[14], chanx_left_in[9], chanx_left_in[18] }),
.sram(mux_tree_tapbuf_size7_1_sram[0:2]),
.sram_inv(mux_tree_tapbuf_size7_1_sram_inv[0:2]),
.sram_inv(mux_right_track_24_undriven_sram_inv[0:2]),
.out(chanx_right_out[12])
);
@ -353,7 +345,7 @@ module sb_1__2_
(
.in({ chanx_right_in[2], bottom_left_grid_pin_42_[0], bottom_left_grid_pin_44_[0], bottom_left_grid_pin_46_[0], bottom_left_grid_pin_48_[0], chanx_left_in[1:2] }),
.sram(mux_tree_tapbuf_size7_2_sram[0:2]),
.sram_inv(mux_tree_tapbuf_size7_2_sram_inv[0:2]),
.sram_inv(mux_bottom_track_1_undriven_sram_inv[0:2]),
.out(chany_bottom_out[0])
);
@ -363,7 +355,7 @@ module sb_1__2_
(
.in({ chanx_right_in[4], bottom_left_grid_pin_43_[0], bottom_left_grid_pin_45_[0], bottom_left_grid_pin_47_[0], bottom_left_grid_pin_49_[0], chanx_left_in[3:4] }),
.sram(mux_tree_tapbuf_size7_3_sram[0:2]),
.sram_inv(mux_tree_tapbuf_size7_3_sram_inv[0:2]),
.sram_inv(mux_bottom_track_3_undriven_sram_inv[0:2]),
.out(chany_bottom_out[1])
);
@ -373,7 +365,7 @@ module sb_1__2_
(
.in({ chanx_right_in[5], bottom_left_grid_pin_42_[0], bottom_left_grid_pin_44_[0], bottom_left_grid_pin_46_[0], bottom_left_grid_pin_48_[0], chanx_left_in[5], chanx_left_in[7] }),
.sram(mux_tree_tapbuf_size7_4_sram[0:2]),
.sram_inv(mux_tree_tapbuf_size7_4_sram_inv[0:2]),
.sram_inv(mux_bottom_track_5_undriven_sram_inv[0:2]),
.out(chany_bottom_out[2])
);
@ -383,7 +375,7 @@ module sb_1__2_
(
.in({ chanx_right_in[6], bottom_left_grid_pin_43_[0], bottom_left_grid_pin_45_[0], bottom_left_grid_pin_47_[0], bottom_left_grid_pin_49_[0], chanx_left_in[6], chanx_left_in[11] }),
.sram(mux_tree_tapbuf_size7_5_sram[0:2]),
.sram_inv(mux_tree_tapbuf_size7_5_sram_inv[0:2]),
.sram_inv(mux_bottom_track_7_undriven_sram_inv[0:2]),
.out(chany_bottom_out[3])
);
@ -393,7 +385,7 @@ module sb_1__2_
(
.in({ chanx_right_in[8], chanx_right_in[17], chany_bottom_in[3], chany_bottom_in[10], chany_bottom_in[17], left_bottom_grid_pin_34_[0], left_bottom_grid_pin_38_[0] }),
.sram(mux_tree_tapbuf_size7_6_sram[0:2]),
.sram_inv(mux_tree_tapbuf_size7_6_sram_inv[0:2]),
.sram_inv(mux_left_track_17_undriven_sram_inv[0:2]),
.out(chanx_left_out[8])
);
@ -403,7 +395,7 @@ module sb_1__2_
(
.in({ chanx_right_in[9], chanx_right_in[18], chany_bottom_in[4], chany_bottom_in[11], chany_bottom_in[18], left_bottom_grid_pin_35_[0], left_bottom_grid_pin_39_[0] }),
.sram(mux_tree_tapbuf_size7_7_sram[0:2]),
.sram_inv(mux_tree_tapbuf_size7_7_sram_inv[0:2]),
.sram_inv(mux_left_track_25_undriven_sram_inv[0:2]),
.out(chanx_left_out[12])
);
@ -414,8 +406,7 @@ module sb_1__2_
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size8_mem_0_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size7_mem_0_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size7_0_sram[0:2]),
.mem_outb(mux_tree_tapbuf_size7_0_sram_inv[0:2])
.mem_out(mux_tree_tapbuf_size7_0_sram[0:2])
);
@ -425,8 +416,7 @@ module sb_1__2_
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size7_mem_0_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size7_mem_1_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size7_1_sram[0:2]),
.mem_outb(mux_tree_tapbuf_size7_1_sram_inv[0:2])
.mem_out(mux_tree_tapbuf_size7_1_sram[0:2])
);
@ -436,8 +426,7 @@ module sb_1__2_
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size5_mem_0_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size7_mem_2_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size7_2_sram[0:2]),
.mem_outb(mux_tree_tapbuf_size7_2_sram_inv[0:2])
.mem_out(mux_tree_tapbuf_size7_2_sram[0:2])
);
@ -447,8 +436,7 @@ module sb_1__2_
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size7_mem_2_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size7_mem_3_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size7_3_sram[0:2]),
.mem_outb(mux_tree_tapbuf_size7_3_sram_inv[0:2])
.mem_out(mux_tree_tapbuf_size7_3_sram[0:2])
);
@ -458,8 +446,7 @@ module sb_1__2_
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size7_mem_3_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size7_mem_4_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size7_4_sram[0:2]),
.mem_outb(mux_tree_tapbuf_size7_4_sram_inv[0:2])
.mem_out(mux_tree_tapbuf_size7_4_sram[0:2])
);
@ -469,8 +456,7 @@ module sb_1__2_
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size7_mem_4_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size7_mem_5_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size7_5_sram[0:2]),
.mem_outb(mux_tree_tapbuf_size7_5_sram_inv[0:2])
.mem_out(mux_tree_tapbuf_size7_5_sram[0:2])
);
@ -480,8 +466,7 @@ module sb_1__2_
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size8_mem_1_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size7_mem_6_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size7_6_sram[0:2]),
.mem_outb(mux_tree_tapbuf_size7_6_sram_inv[0:2])
.mem_out(mux_tree_tapbuf_size7_6_sram[0:2])
);
@ -491,8 +476,7 @@ module sb_1__2_
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size7_mem_6_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size7_mem_7_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size7_7_sram[0:2]),
.mem_outb(mux_tree_tapbuf_size7_7_sram_inv[0:2])
.mem_out(mux_tree_tapbuf_size7_7_sram[0:2])
);
@ -501,7 +485,7 @@ module sb_1__2_
(
.in({ right_bottom_grid_pin_36_[0], right_bottom_grid_pin_40_[0], chany_bottom_in[6], chany_bottom_in[13], chanx_left_in[10] }),
.sram(mux_tree_tapbuf_size5_0_sram[0:2]),
.sram_inv(mux_tree_tapbuf_size5_0_sram_inv[0:2]),
.sram_inv(mux_right_track_32_undriven_sram_inv[0:2]),
.out(chanx_right_out[16])
);
@ -512,8 +496,7 @@ module sb_1__2_
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size7_mem_1_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size5_mem_0_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size5_0_sram[0:2]),
.mem_outb(mux_tree_tapbuf_size5_0_sram_inv[0:2])
.mem_out(mux_tree_tapbuf_size5_0_sram[0:2])
);
@ -522,7 +505,7 @@ module sb_1__2_
(
.in({ chanx_right_in[8], bottom_left_grid_pin_42_[0], chanx_left_in[8], chanx_left_in[15] }),
.sram(mux_tree_tapbuf_size4_0_sram[0:2]),
.sram_inv(mux_tree_tapbuf_size4_0_sram_inv[0:2]),
.sram_inv(mux_bottom_track_9_undriven_sram_inv[0:2]),
.out(chany_bottom_out[4])
);
@ -532,7 +515,7 @@ module sb_1__2_
(
.in({ chanx_right_in[9], bottom_left_grid_pin_43_[0], chanx_left_in[9], chanx_left_in[19] }),
.sram(mux_tree_tapbuf_size4_1_sram[0:2]),
.sram_inv(mux_tree_tapbuf_size4_1_sram_inv[0:2]),
.sram_inv(mux_bottom_track_11_undriven_sram_inv[0:2]),
.out(chany_bottom_out[5])
);
@ -542,7 +525,7 @@ module sb_1__2_
(
.in({ chanx_right_in[18:19], bottom_left_grid_pin_42_[0], chanx_left_in[18] }),
.sram(mux_tree_tapbuf_size4_2_sram[0:2]),
.sram_inv(mux_tree_tapbuf_size4_2_sram_inv[0:2]),
.sram_inv(mux_bottom_track_25_undriven_sram_inv[0:2]),
.out(chany_bottom_out[12])
);
@ -553,8 +536,7 @@ module sb_1__2_
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size7_mem_5_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size4_mem_0_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size4_0_sram[0:2]),
.mem_outb(mux_tree_tapbuf_size4_0_sram_inv[0:2])
.mem_out(mux_tree_tapbuf_size4_0_sram[0:2])
);
@ -564,8 +546,7 @@ module sb_1__2_
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size4_mem_0_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size4_mem_1_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size4_1_sram[0:2]),
.mem_outb(mux_tree_tapbuf_size4_1_sram_inv[0:2])
.mem_out(mux_tree_tapbuf_size4_1_sram[0:2])
);
@ -575,8 +556,7 @@ module sb_1__2_
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size3_mem_5_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size4_mem_2_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size4_2_sram[0:2]),
.mem_outb(mux_tree_tapbuf_size4_2_sram_inv[0:2])
.mem_out(mux_tree_tapbuf_size4_2_sram[0:2])
);
@ -585,7 +565,7 @@ module sb_1__2_
(
.in({ chanx_right_in[10], bottom_left_grid_pin_44_[0], chanx_left_in[10] }),
.sram(mux_tree_tapbuf_size3_0_sram[0:1]),
.sram_inv(mux_tree_tapbuf_size3_0_sram_inv[0:1]),
.sram_inv(mux_bottom_track_13_undriven_sram_inv[0:1]),
.out(chany_bottom_out[6])
);
@ -595,7 +575,7 @@ module sb_1__2_
(
.in({ chanx_right_in[12], bottom_left_grid_pin_45_[0], chanx_left_in[12] }),
.sram(mux_tree_tapbuf_size3_1_sram[0:1]),
.sram_inv(mux_tree_tapbuf_size3_1_sram_inv[0:1]),
.sram_inv(mux_bottom_track_15_undriven_sram_inv[0:1]),
.out(chany_bottom_out[7])
);
@ -605,7 +585,7 @@ module sb_1__2_
(
.in({ chanx_right_in[13], bottom_left_grid_pin_46_[0], chanx_left_in[13] }),
.sram(mux_tree_tapbuf_size3_2_sram[0:1]),
.sram_inv(mux_tree_tapbuf_size3_2_sram_inv[0:1]),
.sram_inv(mux_bottom_track_17_undriven_sram_inv[0:1]),
.out(chany_bottom_out[8])
);
@ -615,7 +595,7 @@ module sb_1__2_
(
.in({ chanx_right_in[14], bottom_left_grid_pin_47_[0], chanx_left_in[14] }),
.sram(mux_tree_tapbuf_size3_3_sram[0:1]),
.sram_inv(mux_tree_tapbuf_size3_3_sram_inv[0:1]),
.sram_inv(mux_bottom_track_19_undriven_sram_inv[0:1]),
.out(chany_bottom_out[9])
);
@ -625,7 +605,7 @@ module sb_1__2_
(
.in({ chanx_right_in[16], bottom_left_grid_pin_48_[0], chanx_left_in[16] }),
.sram(mux_tree_tapbuf_size3_4_sram[0:1]),
.sram_inv(mux_tree_tapbuf_size3_4_sram_inv[0:1]),
.sram_inv(mux_bottom_track_21_undriven_sram_inv[0:1]),
.out(chany_bottom_out[10])
);
@ -635,7 +615,7 @@ module sb_1__2_
(
.in({ chanx_right_in[17], bottom_left_grid_pin_49_[0], chanx_left_in[17] }),
.sram(mux_tree_tapbuf_size3_5_sram[0:1]),
.sram_inv(mux_tree_tapbuf_size3_5_sram_inv[0:1]),
.sram_inv(mux_bottom_track_23_undriven_sram_inv[0:1]),
.out(chany_bottom_out[11])
);
@ -646,8 +626,7 @@ module sb_1__2_
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size4_mem_1_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size3_mem_0_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size3_0_sram[0:1]),
.mem_outb(mux_tree_tapbuf_size3_0_sram_inv[0:1])
.mem_out(mux_tree_tapbuf_size3_0_sram[0:1])
);
@ -657,8 +636,7 @@ module sb_1__2_
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size3_mem_0_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size3_mem_1_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size3_1_sram[0:1]),
.mem_outb(mux_tree_tapbuf_size3_1_sram_inv[0:1])
.mem_out(mux_tree_tapbuf_size3_1_sram[0:1])
);
@ -668,8 +646,7 @@ module sb_1__2_
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size3_mem_1_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size3_mem_2_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size3_2_sram[0:1]),
.mem_outb(mux_tree_tapbuf_size3_2_sram_inv[0:1])
.mem_out(mux_tree_tapbuf_size3_2_sram[0:1])
);
@ -679,8 +656,7 @@ module sb_1__2_
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size3_mem_2_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size3_mem_3_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size3_3_sram[0:1]),
.mem_outb(mux_tree_tapbuf_size3_3_sram_inv[0:1])
.mem_out(mux_tree_tapbuf_size3_3_sram[0:1])
);
@ -690,8 +666,7 @@ module sb_1__2_
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size3_mem_3_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size3_mem_4_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size3_4_sram[0:1]),
.mem_outb(mux_tree_tapbuf_size3_4_sram_inv[0:1])
.mem_out(mux_tree_tapbuf_size3_4_sram[0:1])
);
@ -701,8 +676,7 @@ module sb_1__2_
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size3_mem_4_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size3_mem_5_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size3_5_sram[0:1]),
.mem_outb(mux_tree_tapbuf_size3_5_sram_inv[0:1])
.mem_out(mux_tree_tapbuf_size3_5_sram[0:1])
);
@ -711,7 +685,7 @@ module sb_1__2_
(
.in({ chanx_right_in[15], bottom_left_grid_pin_43_[0] }),
.sram(mux_tree_tapbuf_size2_0_sram[0:1]),
.sram_inv(mux_tree_tapbuf_size2_0_sram_inv[0:1]),
.sram_inv(mux_bottom_track_27_undriven_sram_inv[0:1]),
.out(chany_bottom_out[13])
);
@ -722,8 +696,7 @@ module sb_1__2_
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size4_mem_2_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size2_mem_0_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size2_0_sram[0:1]),
.mem_outb(mux_tree_tapbuf_size2_0_sram_inv[0:1])
.mem_out(mux_tree_tapbuf_size2_0_sram[0:1])
);
@ -732,7 +705,7 @@ module sb_1__2_
(
.in({ chanx_right_in[10], chany_bottom_in[5], chany_bottom_in[12], chany_bottom_in[19], left_bottom_grid_pin_36_[0], left_bottom_grid_pin_40_[0] }),
.sram(mux_tree_tapbuf_size6_0_sram[0:2]),
.sram_inv(mux_tree_tapbuf_size6_0_sram_inv[0:2]),
.sram_inv(mux_left_track_33_undriven_sram_inv[0:2]),
.out(chanx_left_out[16])
);
@ -743,8 +716,7 @@ module sb_1__2_
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size7_mem_7_ccff_tail[0]),
.ccff_tail(ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size6_0_sram[0:2]),
.mem_outb(mux_tree_tapbuf_size6_0_sram_inv[0:2])
.mem_out(mux_tree_tapbuf_size6_0_sram[0:2])
);

210
FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/routing/sb_2__0_.v
View File

@ -25,46 +25,56 @@ module sb_2__0_
output [0:19] chanx_left_out;
output [0:0] ccff_tail;
wire [0:1] mux_left_track_11_undriven_sram_inv;
wire [0:1] mux_left_track_13_undriven_sram_inv;
wire [0:1] mux_left_track_15_undriven_sram_inv;
wire [0:1] mux_left_track_17_undriven_sram_inv;
wire [0:1] mux_left_track_19_undriven_sram_inv;
wire [0:2] mux_left_track_1_undriven_sram_inv;
wire [0:1] mux_left_track_25_undriven_sram_inv;
wire [0:1] mux_left_track_27_undriven_sram_inv;
wire [0:1] mux_left_track_29_undriven_sram_inv;
wire [0:1] mux_left_track_31_undriven_sram_inv;
wire [0:1] mux_left_track_33_undriven_sram_inv;
wire [0:1] mux_left_track_35_undriven_sram_inv;
wire [0:2] mux_left_track_3_undriven_sram_inv;
wire [0:2] mux_left_track_5_undriven_sram_inv;
wire [0:2] mux_left_track_7_undriven_sram_inv;
wire [0:1] mux_left_track_9_undriven_sram_inv;
wire [0:2] mux_top_track_0_undriven_sram_inv;
wire [0:1] mux_top_track_10_undriven_sram_inv;
wire [0:1] mux_top_track_12_undriven_sram_inv;
wire [0:1] mux_top_track_14_undriven_sram_inv;
wire [0:1] mux_top_track_16_undriven_sram_inv;
wire [0:1] mux_top_track_18_undriven_sram_inv;
wire [0:1] mux_top_track_20_undriven_sram_inv;
wire [0:1] mux_top_track_22_undriven_sram_inv;
wire [0:1] mux_top_track_24_undriven_sram_inv;
wire [0:1] mux_top_track_26_undriven_sram_inv;
wire [0:2] mux_top_track_2_undriven_sram_inv;
wire [0:2] mux_top_track_4_undriven_sram_inv;
wire [0:2] mux_top_track_6_undriven_sram_inv;
wire [0:1] mux_top_track_8_undriven_sram_inv;
wire [0:1] mux_tree_tapbuf_size2_0_sram;
wire [0:1] mux_tree_tapbuf_size2_0_sram_inv;
wire [0:1] mux_tree_tapbuf_size2_10_sram;
wire [0:1] mux_tree_tapbuf_size2_10_sram_inv;
wire [0:1] mux_tree_tapbuf_size2_11_sram;
wire [0:1] mux_tree_tapbuf_size2_11_sram_inv;
wire [0:1] mux_tree_tapbuf_size2_12_sram;
wire [0:1] mux_tree_tapbuf_size2_12_sram_inv;
wire [0:1] mux_tree_tapbuf_size2_13_sram;
wire [0:1] mux_tree_tapbuf_size2_13_sram_inv;
wire [0:1] mux_tree_tapbuf_size2_14_sram;
wire [0:1] mux_tree_tapbuf_size2_14_sram_inv;
wire [0:1] mux_tree_tapbuf_size2_15_sram;
wire [0:1] mux_tree_tapbuf_size2_15_sram_inv;
wire [0:1] mux_tree_tapbuf_size2_16_sram;
wire [0:1] mux_tree_tapbuf_size2_16_sram_inv;
wire [0:1] mux_tree_tapbuf_size2_17_sram;
wire [0:1] mux_tree_tapbuf_size2_17_sram_inv;
wire [0:1] mux_tree_tapbuf_size2_18_sram;
wire [0:1] mux_tree_tapbuf_size2_18_sram_inv;
wire [0:1] mux_tree_tapbuf_size2_19_sram;
wire [0:1] mux_tree_tapbuf_size2_19_sram_inv;
wire [0:1] mux_tree_tapbuf_size2_1_sram;
wire [0:1] mux_tree_tapbuf_size2_1_sram_inv;
wire [0:1] mux_tree_tapbuf_size2_2_sram;
wire [0:1] mux_tree_tapbuf_size2_2_sram_inv;
wire [0:1] mux_tree_tapbuf_size2_3_sram;
wire [0:1] mux_tree_tapbuf_size2_3_sram_inv;
wire [0:1] mux_tree_tapbuf_size2_4_sram;
wire [0:1] mux_tree_tapbuf_size2_4_sram_inv;
wire [0:1] mux_tree_tapbuf_size2_5_sram;
wire [0:1] mux_tree_tapbuf_size2_5_sram_inv;
wire [0:1] mux_tree_tapbuf_size2_6_sram;
wire [0:1] mux_tree_tapbuf_size2_6_sram_inv;
wire [0:1] mux_tree_tapbuf_size2_7_sram;
wire [0:1] mux_tree_tapbuf_size2_7_sram_inv;
wire [0:1] mux_tree_tapbuf_size2_8_sram;
wire [0:1] mux_tree_tapbuf_size2_8_sram_inv;
wire [0:1] mux_tree_tapbuf_size2_9_sram;
wire [0:1] mux_tree_tapbuf_size2_9_sram_inv;
wire [0:0] mux_tree_tapbuf_size2_mem_0_ccff_tail;
wire [0:0] mux_tree_tapbuf_size2_mem_10_ccff_tail;
wire [0:0] mux_tree_tapbuf_size2_mem_11_ccff_tail;
@ -85,33 +95,23 @@ module sb_2__0_
wire [0:0] mux_tree_tapbuf_size2_mem_8_ccff_tail;
wire [0:0] mux_tree_tapbuf_size2_mem_9_ccff_tail;
wire [0:1] mux_tree_tapbuf_size3_0_sram;
wire [0:1] mux_tree_tapbuf_size3_0_sram_inv;
wire [0:1] mux_tree_tapbuf_size3_1_sram;
wire [0:1] mux_tree_tapbuf_size3_1_sram_inv;
wire [0:0] mux_tree_tapbuf_size3_mem_0_ccff_tail;
wire [0:0] mux_tree_tapbuf_size3_mem_1_ccff_tail;
wire [0:2] mux_tree_tapbuf_size4_0_sram;
wire [0:2] mux_tree_tapbuf_size4_0_sram_inv;
wire [0:2] mux_tree_tapbuf_size4_1_sram;
wire [0:2] mux_tree_tapbuf_size4_1_sram_inv;
wire [0:2] mux_tree_tapbuf_size4_2_sram;
wire [0:2] mux_tree_tapbuf_size4_2_sram_inv;
wire [0:2] mux_tree_tapbuf_size4_3_sram;
wire [0:2] mux_tree_tapbuf_size4_3_sram_inv;
wire [0:0] mux_tree_tapbuf_size4_mem_0_ccff_tail;
wire [0:0] mux_tree_tapbuf_size4_mem_1_ccff_tail;
wire [0:0] mux_tree_tapbuf_size4_mem_2_ccff_tail;
wire [0:0] mux_tree_tapbuf_size4_mem_3_ccff_tail;
wire [0:2] mux_tree_tapbuf_size5_0_sram;
wire [0:2] mux_tree_tapbuf_size5_0_sram_inv;
wire [0:2] mux_tree_tapbuf_size5_1_sram;
wire [0:2] mux_tree_tapbuf_size5_1_sram_inv;
wire [0:0] mux_tree_tapbuf_size5_mem_0_ccff_tail;
wire [0:0] mux_tree_tapbuf_size5_mem_1_ccff_tail;
wire [0:2] mux_tree_tapbuf_size6_0_sram;
wire [0:2] mux_tree_tapbuf_size6_0_sram_inv;
wire [0:2] mux_tree_tapbuf_size6_1_sram;
wire [0:2] mux_tree_tapbuf_size6_1_sram_inv;
wire [0:0] mux_tree_tapbuf_size6_mem_0_ccff_tail;
wire [0:0] mux_tree_tapbuf_size6_mem_1_ccff_tail;
assign chanx_left_out[19] = chany_top_in[1];
@ -130,7 +130,7 @@ module sb_2__0_
(
.in({ top_left_grid_pin_42_[0], top_left_grid_pin_44_[0], top_left_grid_pin_46_[0], top_left_grid_pin_48_[0], top_right_grid_pin_1_[0], chanx_left_in[0] }),
.sram(mux_tree_tapbuf_size6_0_sram[0:2]),
.sram_inv(mux_tree_tapbuf_size6_0_sram_inv[0:2]),
.sram_inv(mux_top_track_0_undriven_sram_inv[0:2]),
.out(chany_top_out[0])
);
@ -140,7 +140,7 @@ module sb_2__0_
(
.in({ top_left_grid_pin_42_[0], top_left_grid_pin_44_[0], top_left_grid_pin_46_[0], top_left_grid_pin_48_[0], top_right_grid_pin_1_[0], chanx_left_in[18] }),
.sram(mux_tree_tapbuf_size6_1_sram[0:2]),
.sram_inv(mux_tree_tapbuf_size6_1_sram_inv[0:2]),
.sram_inv(mux_top_track_4_undriven_sram_inv[0:2]),
.out(chany_top_out[2])
);
@ -151,8 +151,7 @@ module sb_2__0_
.prog_clk(prog_clk[0]),
.ccff_head(ccff_head[0]),
.ccff_tail(mux_tree_tapbuf_size6_mem_0_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size6_0_sram[0:2]),
.mem_outb(mux_tree_tapbuf_size6_0_sram_inv[0:2])
.mem_out(mux_tree_tapbuf_size6_0_sram[0:2])
);
@ -162,8 +161,7 @@ module sb_2__0_
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size5_mem_0_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size6_mem_1_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size6_1_sram[0:2]),
.mem_outb(mux_tree_tapbuf_size6_1_sram_inv[0:2])
.mem_out(mux_tree_tapbuf_size6_1_sram[0:2])
);
@ -172,7 +170,7 @@ module sb_2__0_
(
.in({ top_left_grid_pin_43_[0], top_left_grid_pin_45_[0], top_left_grid_pin_47_[0], top_left_grid_pin_49_[0], chanx_left_in[19] }),
.sram(mux_tree_tapbuf_size5_0_sram[0:2]),
.sram_inv(mux_tree_tapbuf_size5_0_sram_inv[0:2]),
.sram_inv(mux_top_track_2_undriven_sram_inv[0:2]),
.out(chany_top_out[1])
);
@ -182,7 +180,7 @@ module sb_2__0_
(
.in({ top_left_grid_pin_43_[0], top_left_grid_pin_45_[0], top_left_grid_pin_47_[0], top_left_grid_pin_49_[0], chanx_left_in[17] }),
.sram(mux_tree_tapbuf_size5_1_sram[0:2]),
.sram_inv(mux_tree_tapbuf_size5_1_sram_inv[0:2]),
.sram_inv(mux_top_track_6_undriven_sram_inv[0:2]),
.out(chany_top_out[3])
);
@ -193,8 +191,7 @@ module sb_2__0_
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size6_mem_0_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size5_mem_0_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size5_0_sram[0:2]),
.mem_outb(mux_tree_tapbuf_size5_0_sram_inv[0:2])
.mem_out(mux_tree_tapbuf_size5_0_sram[0:2])
);
@ -204,8 +201,7 @@ module sb_2__0_
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size6_mem_1_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size5_mem_1_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size5_1_sram[0:2]),
.mem_outb(mux_tree_tapbuf_size5_1_sram_inv[0:2])
.mem_out(mux_tree_tapbuf_size5_1_sram[0:2])
);
@ -214,7 +210,7 @@ module sb_2__0_
(
.in({ top_left_grid_pin_42_[0], top_right_grid_pin_1_[0], chanx_left_in[16] }),
.sram(mux_tree_tapbuf_size3_0_sram[0:1]),
.sram_inv(mux_tree_tapbuf_size3_0_sram_inv[0:1]),
.sram_inv(mux_top_track_8_undriven_sram_inv[0:1]),
.out(chany_top_out[4])
);
@ -224,7 +220,7 @@ module sb_2__0_
(
.in({ top_left_grid_pin_42_[0], top_right_grid_pin_1_[0], chanx_left_in[8] }),
.sram(mux_tree_tapbuf_size3_1_sram[0:1]),
.sram_inv(mux_tree_tapbuf_size3_1_sram_inv[0:1]),
.sram_inv(mux_top_track_24_undriven_sram_inv[0:1]),
.out(chany_top_out[12])
);
@ -235,8 +231,7 @@ module sb_2__0_
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size5_mem_1_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size3_mem_0_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size3_0_sram[0:1]),
.mem_outb(mux_tree_tapbuf_size3_0_sram_inv[0:1])
.mem_out(mux_tree_tapbuf_size3_0_sram[0:1])
);
@ -246,8 +241,7 @@ module sb_2__0_
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size2_mem_6_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size3_mem_1_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size3_1_sram[0:1]),
.mem_outb(mux_tree_tapbuf_size3_1_sram_inv[0:1])
.mem_out(mux_tree_tapbuf_size3_1_sram[0:1])
);
@ -256,7 +250,7 @@ module sb_2__0_
(
.in({ top_left_grid_pin_43_[0], chanx_left_in[15] }),
.sram(mux_tree_tapbuf_size2_0_sram[0:1]),
.sram_inv(mux_tree_tapbuf_size2_0_sram_inv[0:1]),
.sram_inv(mux_top_track_10_undriven_sram_inv[0:1]),
.out(chany_top_out[5])
);
@ -266,7 +260,7 @@ module sb_2__0_
(
.in({ top_left_grid_pin_44_[0], chanx_left_in[14] }),
.sram(mux_tree_tapbuf_size2_1_sram[0:1]),
.sram_inv(mux_tree_tapbuf_size2_1_sram_inv[0:1]),
.sram_inv(mux_top_track_12_undriven_sram_inv[0:1]),
.out(chany_top_out[6])
);
@ -276,7 +270,7 @@ module sb_2__0_
(
.in({ top_left_grid_pin_45_[0], chanx_left_in[13] }),
.sram(mux_tree_tapbuf_size2_2_sram[0:1]),
.sram_inv(mux_tree_tapbuf_size2_2_sram_inv[0:1]),
.sram_inv(mux_top_track_14_undriven_sram_inv[0:1]),
.out(chany_top_out[7])
);
@ -286,7 +280,7 @@ module sb_2__0_
(
.in({ top_left_grid_pin_46_[0], chanx_left_in[12] }),
.sram(mux_tree_tapbuf_size2_3_sram[0:1]),
.sram_inv(mux_tree_tapbuf_size2_3_sram_inv[0:1]),
.sram_inv(mux_top_track_16_undriven_sram_inv[0:1]),
.out(chany_top_out[8])
);
@ -296,7 +290,7 @@ module sb_2__0_
(
.in({ top_left_grid_pin_47_[0], chanx_left_in[11] }),
.sram(mux_tree_tapbuf_size2_4_sram[0:1]),
.sram_inv(mux_tree_tapbuf_size2_4_sram_inv[0:1]),
.sram_inv(mux_top_track_18_undriven_sram_inv[0:1]),
.out(chany_top_out[9])
);
@ -306,7 +300,7 @@ module sb_2__0_
(
.in({ top_left_grid_pin_48_[0], chanx_left_in[10] }),
.sram(mux_tree_tapbuf_size2_5_sram[0:1]),
.sram_inv(mux_tree_tapbuf_size2_5_sram_inv[0:1]),
.sram_inv(mux_top_track_20_undriven_sram_inv[0:1]),
.out(chany_top_out[10])
);
@ -316,7 +310,7 @@ module sb_2__0_
(
.in({ top_left_grid_pin_49_[0], chanx_left_in[9] }),
.sram(mux_tree_tapbuf_size2_6_sram[0:1]),
.sram_inv(mux_tree_tapbuf_size2_6_sram_inv[0:1]),
.sram_inv(mux_top_track_22_undriven_sram_inv[0:1]),
.out(chany_top_out[11])
);
@ -326,7 +320,7 @@ module sb_2__0_
(
.in({ top_left_grid_pin_43_[0], chanx_left_in[7] }),
.sram(mux_tree_tapbuf_size2_7_sram[0:1]),
.sram_inv(mux_tree_tapbuf_size2_7_sram_inv[0:1]),
.sram_inv(mux_top_track_26_undriven_sram_inv[0:1]),
.out(chany_top_out[13])
);
@ -336,7 +330,7 @@ module sb_2__0_
(
.in({ chany_top_in[16], left_bottom_grid_pin_1_[0] }),
.sram(mux_tree_tapbuf_size2_8_sram[0:1]),
.sram_inv(mux_tree_tapbuf_size2_8_sram_inv[0:1]),
.sram_inv(mux_left_track_9_undriven_sram_inv[0:1]),
.out(chanx_left_out[4])
);
@ -346,7 +340,7 @@ module sb_2__0_
(
.in({ chany_top_in[15], left_bottom_grid_pin_3_[0] }),
.sram(mux_tree_tapbuf_size2_9_sram[0:1]),
.sram_inv(mux_tree_tapbuf_size2_9_sram_inv[0:1]),
.sram_inv(mux_left_track_11_undriven_sram_inv[0:1]),
.out(chanx_left_out[5])
);
@ -356,7 +350,7 @@ module sb_2__0_
(
.in({ chany_top_in[14], left_bottom_grid_pin_5_[0] }),
.sram(mux_tree_tapbuf_size2_10_sram[0:1]),
.sram_inv(mux_tree_tapbuf_size2_10_sram_inv[0:1]),
.sram_inv(mux_left_track_13_undriven_sram_inv[0:1]),
.out(chanx_left_out[6])
);
@ -366,7 +360,7 @@ module sb_2__0_
(
.in({ chany_top_in[13], left_bottom_grid_pin_7_[0] }),
.sram(mux_tree_tapbuf_size2_11_sram[0:1]),
.sram_inv(mux_tree_tapbuf_size2_11_sram_inv[0:1]),
.sram_inv(mux_left_track_15_undriven_sram_inv[0:1]),
.out(chanx_left_out[7])
);
@ -376,7 +370,7 @@ module sb_2__0_
(
.in({ chany_top_in[12], left_bottom_grid_pin_9_[0] }),
.sram(mux_tree_tapbuf_size2_12_sram[0:1]),
.sram_inv(mux_tree_tapbuf_size2_12_sram_inv[0:1]),
.sram_inv(mux_left_track_17_undriven_sram_inv[0:1]),
.out(chanx_left_out[8])
);
@ -386,7 +380,7 @@ module sb_2__0_
(
.in({ chany_top_in[11], left_bottom_grid_pin_11_[0] }),
.sram(mux_tree_tapbuf_size2_13_sram[0:1]),
.sram_inv(mux_tree_tapbuf_size2_13_sram_inv[0:1]),
.sram_inv(mux_left_track_19_undriven_sram_inv[0:1]),
.out(chanx_left_out[9])
);
@ -396,7 +390,7 @@ module sb_2__0_
(
.in({ chany_top_in[8], left_bottom_grid_pin_1_[0] }),
.sram(mux_tree_tapbuf_size2_14_sram[0:1]),
.sram_inv(mux_tree_tapbuf_size2_14_sram_inv[0:1]),
.sram_inv(mux_left_track_25_undriven_sram_inv[0:1]),
.out(chanx_left_out[12])
);
@ -406,7 +400,7 @@ module sb_2__0_
(
.in({ chany_top_in[7], left_bottom_grid_pin_3_[0] }),
.sram(mux_tree_tapbuf_size2_15_sram[0:1]),
.sram_inv(mux_tree_tapbuf_size2_15_sram_inv[0:1]),
.sram_inv(mux_left_track_27_undriven_sram_inv[0:1]),
.out(chanx_left_out[13])
);
@ -416,7 +410,7 @@ module sb_2__0_
(
.in({ chany_top_in[6], left_bottom_grid_pin_5_[0] }),
.sram(mux_tree_tapbuf_size2_16_sram[0:1]),
.sram_inv(mux_tree_tapbuf_size2_16_sram_inv[0:1]),
.sram_inv(mux_left_track_29_undriven_sram_inv[0:1]),
.out(chanx_left_out[14])
);
@ -426,7 +420,7 @@ module sb_2__0_
(
.in({ chany_top_in[5], left_bottom_grid_pin_7_[0] }),
.sram(mux_tree_tapbuf_size2_17_sram[0:1]),
.sram_inv(mux_tree_tapbuf_size2_17_sram_inv[0:1]),
.sram_inv(mux_left_track_31_undriven_sram_inv[0:1]),
.out(chanx_left_out[15])
);
@ -436,7 +430,7 @@ module sb_2__0_
(
.in({ chany_top_in[4], left_bottom_grid_pin_9_[0] }),
.sram(mux_tree_tapbuf_size2_18_sram[0:1]),
.sram_inv(mux_tree_tapbuf_size2_18_sram_inv[0:1]),
.sram_inv(mux_left_track_33_undriven_sram_inv[0:1]),
.out(chanx_left_out[16])
);
@ -446,7 +440,7 @@ module sb_2__0_
(
.in({ chany_top_in[3], left_bottom_grid_pin_11_[0] }),
.sram(mux_tree_tapbuf_size2_19_sram[0:1]),
.sram_inv(mux_tree_tapbuf_size2_19_sram_inv[0:1]),
.sram_inv(mux_left_track_35_undriven_sram_inv[0:1]),
.out(chanx_left_out[17])
);
@ -457,8 +451,7 @@ module sb_2__0_
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size3_mem_0_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size2_mem_0_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size2_0_sram[0:1]),
.mem_outb(mux_tree_tapbuf_size2_0_sram_inv[0:1])
.mem_out(mux_tree_tapbuf_size2_0_sram[0:1])
);
@ -468,8 +461,7 @@ module sb_2__0_
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size2_mem_0_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size2_mem_1_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size2_1_sram[0:1]),
.mem_outb(mux_tree_tapbuf_size2_1_sram_inv[0:1])
.mem_out(mux_tree_tapbuf_size2_1_sram[0:1])
);
@ -479,8 +471,7 @@ module sb_2__0_
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size2_mem_1_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size2_mem_2_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size2_2_sram[0:1]),
.mem_outb(mux_tree_tapbuf_size2_2_sram_inv[0:1])
.mem_out(mux_tree_tapbuf_size2_2_sram[0:1])
);
@ -490,8 +481,7 @@ module sb_2__0_
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size2_mem_2_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size2_mem_3_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size2_3_sram[0:1]),
.mem_outb(mux_tree_tapbuf_size2_3_sram_inv[0:1])
.mem_out(mux_tree_tapbuf_size2_3_sram[0:1])
);
@ -501,8 +491,7 @@ module sb_2__0_
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size2_mem_3_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size2_mem_4_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size2_4_sram[0:1]),
.mem_outb(mux_tree_tapbuf_size2_4_sram_inv[0:1])
.mem_out(mux_tree_tapbuf_size2_4_sram[0:1])
);
@ -512,8 +501,7 @@ module sb_2__0_
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size2_mem_4_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size2_mem_5_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size2_5_sram[0:1]),
.mem_outb(mux_tree_tapbuf_size2_5_sram_inv[0:1])
.mem_out(mux_tree_tapbuf_size2_5_sram[0:1])
);
@ -523,8 +511,7 @@ module sb_2__0_
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size2_mem_5_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size2_mem_6_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size2_6_sram[0:1]),
.mem_outb(mux_tree_tapbuf_size2_6_sram_inv[0:1])
.mem_out(mux_tree_tapbuf_size2_6_sram[0:1])
);
@ -534,8 +521,7 @@ module sb_2__0_
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size3_mem_1_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size2_mem_7_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size2_7_sram[0:1]),
.mem_outb(mux_tree_tapbuf_size2_7_sram_inv[0:1])
.mem_out(mux_tree_tapbuf_size2_7_sram[0:1])
);
@ -545,8 +531,7 @@ module sb_2__0_
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size4_mem_3_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size2_mem_8_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size2_8_sram[0:1]),
.mem_outb(mux_tree_tapbuf_size2_8_sram_inv[0:1])
.mem_out(mux_tree_tapbuf_size2_8_sram[0:1])
);
@ -556,8 +541,7 @@ module sb_2__0_
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size2_mem_8_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size2_mem_9_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size2_9_sram[0:1]),
.mem_outb(mux_tree_tapbuf_size2_9_sram_inv[0:1])
.mem_out(mux_tree_tapbuf_size2_9_sram[0:1])
);
@ -567,8 +551,7 @@ module sb_2__0_
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size2_mem_9_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size2_mem_10_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size2_10_sram[0:1]),
.mem_outb(mux_tree_tapbuf_size2_10_sram_inv[0:1])
.mem_out(mux_tree_tapbuf_size2_10_sram[0:1])
);
@ -578,8 +561,7 @@ module sb_2__0_
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size2_mem_10_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size2_mem_11_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size2_11_sram[0:1]),
.mem_outb(mux_tree_tapbuf_size2_11_sram_inv[0:1])
.mem_out(mux_tree_tapbuf_size2_11_sram[0:1])
);
@ -589,8 +571,7 @@ module sb_2__0_
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size2_mem_11_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size2_mem_12_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size2_12_sram[0:1]),
.mem_outb(mux_tree_tapbuf_size2_12_sram_inv[0:1])
.mem_out(mux_tree_tapbuf_size2_12_sram[0:1])
);
@ -600,8 +581,7 @@ module sb_2__0_
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size2_mem_12_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size2_mem_13_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size2_13_sram[0:1]),
.mem_outb(mux_tree_tapbuf_size2_13_sram_inv[0:1])
.mem_out(mux_tree_tapbuf_size2_13_sram[0:1])
);
@ -611,8 +591,7 @@ module sb_2__0_
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size2_mem_13_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size2_mem_14_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size2_14_sram[0:1]),
.mem_outb(mux_tree_tapbuf_size2_14_sram_inv[0:1])
.mem_out(mux_tree_tapbuf_size2_14_sram[0:1])
);
@ -622,8 +601,7 @@ module sb_2__0_
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size2_mem_14_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size2_mem_15_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size2_15_sram[0:1]),
.mem_outb(mux_tree_tapbuf_size2_15_sram_inv[0:1])
.mem_out(mux_tree_tapbuf_size2_15_sram[0:1])
);
@ -633,8 +611,7 @@ module sb_2__0_
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size2_mem_15_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size2_mem_16_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size2_16_sram[0:1]),
.mem_outb(mux_tree_tapbuf_size2_16_sram_inv[0:1])
.mem_out(mux_tree_tapbuf_size2_16_sram[0:1])
);
@ -644,8 +621,7 @@ module sb_2__0_
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size2_mem_16_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size2_mem_17_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size2_17_sram[0:1]),
.mem_outb(mux_tree_tapbuf_size2_17_sram_inv[0:1])
.mem_out(mux_tree_tapbuf_size2_17_sram[0:1])
);
@ -655,8 +631,7 @@ module sb_2__0_
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size2_mem_17_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size2_mem_18_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size2_18_sram[0:1]),
.mem_outb(mux_tree_tapbuf_size2_18_sram_inv[0:1])
.mem_out(mux_tree_tapbuf_size2_18_sram[0:1])
);
@ -666,8 +641,7 @@ module sb_2__0_
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size2_mem_18_ccff_tail[0]),
.ccff_tail(ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size2_19_sram[0:1]),
.mem_outb(mux_tree_tapbuf_size2_19_sram_inv[0:1])
.mem_out(mux_tree_tapbuf_size2_19_sram[0:1])
);
@ -676,7 +650,7 @@ module sb_2__0_
(
.in({ chany_top_in[0], left_bottom_grid_pin_1_[0], left_bottom_grid_pin_5_[0], left_bottom_grid_pin_9_[0] }),
.sram(mux_tree_tapbuf_size4_0_sram[0:2]),
.sram_inv(mux_tree_tapbuf_size4_0_sram_inv[0:2]),
.sram_inv(mux_left_track_1_undriven_sram_inv[0:2]),
.out(chanx_left_out[0])
);
@ -686,7 +660,7 @@ module sb_2__0_
(
.in({ chany_top_in[19], left_bottom_grid_pin_3_[0], left_bottom_grid_pin_7_[0], left_bottom_grid_pin_11_[0] }),
.sram(mux_tree_tapbuf_size4_1_sram[0:2]),
.sram_inv(mux_tree_tapbuf_size4_1_sram_inv[0:2]),
.sram_inv(mux_left_track_3_undriven_sram_inv[0:2]),
.out(chanx_left_out[1])
);
@ -696,7 +670,7 @@ module sb_2__0_
(
.in({ chany_top_in[18], left_bottom_grid_pin_1_[0], left_bottom_grid_pin_5_[0], left_bottom_grid_pin_9_[0] }),
.sram(mux_tree_tapbuf_size4_2_sram[0:2]),
.sram_inv(mux_tree_tapbuf_size4_2_sram_inv[0:2]),
.sram_inv(mux_left_track_5_undriven_sram_inv[0:2]),
.out(chanx_left_out[2])
);
@ -706,7 +680,7 @@ module sb_2__0_
(
.in({ chany_top_in[17], left_bottom_grid_pin_3_[0], left_bottom_grid_pin_7_[0], left_bottom_grid_pin_11_[0] }),
.sram(mux_tree_tapbuf_size4_3_sram[0:2]),
.sram_inv(mux_tree_tapbuf_size4_3_sram_inv[0:2]),
.sram_inv(mux_left_track_7_undriven_sram_inv[0:2]),
.out(chanx_left_out[3])
);
@ -717,8 +691,7 @@ module sb_2__0_
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size2_mem_7_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size4_mem_0_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size4_0_sram[0:2]),
.mem_outb(mux_tree_tapbuf_size4_0_sram_inv[0:2])
.mem_out(mux_tree_tapbuf_size4_0_sram[0:2])
);
@ -728,8 +701,7 @@ module sb_2__0_
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size4_mem_0_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size4_mem_1_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size4_1_sram[0:2]),
.mem_outb(mux_tree_tapbuf_size4_1_sram_inv[0:2])
.mem_out(mux_tree_tapbuf_size4_1_sram[0:2])
);
@ -739,8 +711,7 @@ module sb_2__0_
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size4_mem_1_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size4_mem_2_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size4_2_sram[0:2]),
.mem_outb(mux_tree_tapbuf_size4_2_sram_inv[0:2])
.mem_out(mux_tree_tapbuf_size4_2_sram[0:2])
);
@ -750,8 +721,7 @@ module sb_2__0_
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size4_mem_2_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size4_mem_3_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size4_3_sram[0:2]),
.mem_outb(mux_tree_tapbuf_size4_3_sram_inv[0:2])
.mem_out(mux_tree_tapbuf_size4_3_sram[0:2])
);

231
FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/routing/sb_2__1_.v
View File

@ -38,85 +38,89 @@ module sb_2__1_
output [0:19] chanx_left_out;
output [0:0] ccff_tail;
wire [0:2] mux_bottom_track_17_undriven_sram_inv;
wire [0:3] mux_bottom_track_1_undriven_sram_inv;
wire [0:2] mux_bottom_track_25_undriven_sram_inv;
wire [0:2] mux_bottom_track_33_undriven_sram_inv;
wire [0:3] mux_bottom_track_3_undriven_sram_inv;
wire [0:3] mux_bottom_track_5_undriven_sram_inv;
wire [0:3] mux_bottom_track_9_undriven_sram_inv;
wire [0:2] mux_left_track_11_undriven_sram_inv;
wire [0:2] mux_left_track_13_undriven_sram_inv;
wire [0:2] mux_left_track_15_undriven_sram_inv;
wire [0:1] mux_left_track_17_undriven_sram_inv;
wire [0:1] mux_left_track_19_undriven_sram_inv;
wire [0:2] mux_left_track_1_undriven_sram_inv;
wire [0:1] mux_left_track_21_undriven_sram_inv;
wire [0:1] mux_left_track_23_undriven_sram_inv;
wire [0:1] mux_left_track_25_undriven_sram_inv;
wire [0:1] mux_left_track_29_undriven_sram_inv;
wire [0:1] mux_left_track_31_undriven_sram_inv;
wire [0:1] mux_left_track_33_undriven_sram_inv;
wire [0:1] mux_left_track_35_undriven_sram_inv;
wire [0:1] mux_left_track_37_undriven_sram_inv;
wire [0:1] mux_left_track_39_undriven_sram_inv;
wire [0:2] mux_left_track_3_undriven_sram_inv;
wire [0:2] mux_left_track_5_undriven_sram_inv;
wire [0:2] mux_left_track_7_undriven_sram_inv;
wire [0:2] mux_left_track_9_undriven_sram_inv;
wire [0:3] mux_top_track_0_undriven_sram_inv;
wire [0:2] mux_top_track_16_undriven_sram_inv;
wire [0:2] mux_top_track_24_undriven_sram_inv;
wire [0:3] mux_top_track_2_undriven_sram_inv;
wire [0:2] mux_top_track_32_undriven_sram_inv;
wire [0:3] mux_top_track_4_undriven_sram_inv;
wire [0:3] mux_top_track_8_undriven_sram_inv;
wire [0:3] mux_tree_tapbuf_size10_0_sram;
wire [0:3] mux_tree_tapbuf_size10_0_sram_inv;
wire [0:3] mux_tree_tapbuf_size10_1_sram;
wire [0:3] mux_tree_tapbuf_size10_1_sram_inv;
wire [0:0] mux_tree_tapbuf_size10_mem_0_ccff_tail;
wire [0:0] mux_tree_tapbuf_size10_mem_1_ccff_tail;
wire [0:3] mux_tree_tapbuf_size14_0_sram;
wire [0:3] mux_tree_tapbuf_size14_0_sram_inv;
wire [0:3] mux_tree_tapbuf_size14_1_sram;
wire [0:3] mux_tree_tapbuf_size14_1_sram_inv;
wire [0:0] mux_tree_tapbuf_size14_mem_0_ccff_tail;
wire [0:0] mux_tree_tapbuf_size14_mem_1_ccff_tail;
wire [0:1] mux_tree_tapbuf_size2_0_sram;
wire [0:1] mux_tree_tapbuf_size2_0_sram_inv;
wire [0:1] mux_tree_tapbuf_size2_1_sram;
wire [0:1] mux_tree_tapbuf_size2_1_sram_inv;
wire [0:1] mux_tree_tapbuf_size2_2_sram;
wire [0:1] mux_tree_tapbuf_size2_2_sram_inv;
wire [0:1] mux_tree_tapbuf_size2_3_sram;
wire [0:1] mux_tree_tapbuf_size2_3_sram_inv;
wire [0:1] mux_tree_tapbuf_size2_4_sram;
wire [0:1] mux_tree_tapbuf_size2_4_sram_inv;
wire [0:1] mux_tree_tapbuf_size2_5_sram;
wire [0:1] mux_tree_tapbuf_size2_5_sram_inv;
wire [0:0] mux_tree_tapbuf_size2_mem_0_ccff_tail;
wire [0:0] mux_tree_tapbuf_size2_mem_1_ccff_tail;
wire [0:0] mux_tree_tapbuf_size2_mem_2_ccff_tail;
wire [0:0] mux_tree_tapbuf_size2_mem_3_ccff_tail;
wire [0:0] mux_tree_tapbuf_size2_mem_4_ccff_tail;
wire [0:1] mux_tree_tapbuf_size3_0_sram;
wire [0:1] mux_tree_tapbuf_size3_0_sram_inv;
wire [0:1] mux_tree_tapbuf_size3_1_sram;
wire [0:1] mux_tree_tapbuf_size3_1_sram_inv;
wire [0:1] mux_tree_tapbuf_size3_2_sram;
wire [0:1] mux_tree_tapbuf_size3_2_sram_inv;
wire [0:1] mux_tree_tapbuf_size3_3_sram;
wire [0:1] mux_tree_tapbuf_size3_3_sram_inv;
wire [0:1] mux_tree_tapbuf_size3_4_sram;
wire [0:1] mux_tree_tapbuf_size3_4_sram_inv;
wire [0:0] mux_tree_tapbuf_size3_mem_0_ccff_tail;
wire [0:0] mux_tree_tapbuf_size3_mem_1_ccff_tail;
wire [0:0] mux_tree_tapbuf_size3_mem_2_ccff_tail;
wire [0:0] mux_tree_tapbuf_size3_mem_3_ccff_tail;
wire [0:0] mux_tree_tapbuf_size3_mem_4_ccff_tail;
wire [0:2] mux_tree_tapbuf_size4_0_sram;
wire [0:2] mux_tree_tapbuf_size4_0_sram_inv;
wire [0:2] mux_tree_tapbuf_size4_1_sram;
wire [0:2] mux_tree_tapbuf_size4_1_sram_inv;
wire [0:2] mux_tree_tapbuf_size4_2_sram;
wire [0:2] mux_tree_tapbuf_size4_2_sram_inv;
wire [0:2] mux_tree_tapbuf_size4_3_sram;
wire [0:2] mux_tree_tapbuf_size4_3_sram_inv;
wire [0:0] mux_tree_tapbuf_size4_mem_0_ccff_tail;
wire [0:0] mux_tree_tapbuf_size4_mem_1_ccff_tail;
wire [0:0] mux_tree_tapbuf_size4_mem_2_ccff_tail;
wire [0:0] mux_tree_tapbuf_size4_mem_3_ccff_tail;
wire [0:2] mux_tree_tapbuf_size6_0_sram;
wire [0:2] mux_tree_tapbuf_size6_0_sram_inv;
wire [0:2] mux_tree_tapbuf_size6_1_sram;
wire [0:2] mux_tree_tapbuf_size6_1_sram_inv;
wire [0:2] mux_tree_tapbuf_size6_2_sram;
wire [0:2] mux_tree_tapbuf_size6_2_sram_inv;
wire [0:0] mux_tree_tapbuf_size6_mem_0_ccff_tail;
wire [0:0] mux_tree_tapbuf_size6_mem_1_ccff_tail;
wire [0:0] mux_tree_tapbuf_size6_mem_2_ccff_tail;
wire [0:2] mux_tree_tapbuf_size7_0_sram;
wire [0:2] mux_tree_tapbuf_size7_0_sram_inv;
wire [0:2] mux_tree_tapbuf_size7_1_sram;
wire [0:2] mux_tree_tapbuf_size7_1_sram_inv;
wire [0:2] mux_tree_tapbuf_size7_2_sram;
wire [0:2] mux_tree_tapbuf_size7_2_sram_inv;
wire [0:2] mux_tree_tapbuf_size7_3_sram;
wire [0:2] mux_tree_tapbuf_size7_3_sram_inv;
wire [0:2] mux_tree_tapbuf_size7_4_sram;
wire [0:2] mux_tree_tapbuf_size7_4_sram_inv;
wire [0:2] mux_tree_tapbuf_size7_5_sram;
wire [0:2] mux_tree_tapbuf_size7_5_sram_inv;
wire [0:2] mux_tree_tapbuf_size7_6_sram;
wire [0:2] mux_tree_tapbuf_size7_6_sram_inv;
wire [0:0] mux_tree_tapbuf_size7_mem_0_ccff_tail;
wire [0:0] mux_tree_tapbuf_size7_mem_1_ccff_tail;
wire [0:0] mux_tree_tapbuf_size7_mem_2_ccff_tail;
@ -125,16 +129,12 @@ module sb_2__1_
wire [0:0] mux_tree_tapbuf_size7_mem_5_ccff_tail;
wire [0:0] mux_tree_tapbuf_size7_mem_6_ccff_tail;
wire [0:3] mux_tree_tapbuf_size8_0_sram;
wire [0:3] mux_tree_tapbuf_size8_0_sram_inv;
wire [0:3] mux_tree_tapbuf_size8_1_sram;
wire [0:3] mux_tree_tapbuf_size8_1_sram_inv;
wire [0:3] mux_tree_tapbuf_size8_2_sram;
wire [0:3] mux_tree_tapbuf_size8_2_sram_inv;
wire [0:0] mux_tree_tapbuf_size8_mem_0_ccff_tail;
wire [0:0] mux_tree_tapbuf_size8_mem_1_ccff_tail;
wire [0:0] mux_tree_tapbuf_size8_mem_2_ccff_tail;
wire [0:3] mux_tree_tapbuf_size9_0_sram;
wire [0:3] mux_tree_tapbuf_size9_0_sram_inv;
wire [0:0] mux_tree_tapbuf_size9_mem_0_ccff_tail;
assign chany_bottom_out[3] = chany_top_in[2];
assign chany_bottom_out[5] = chany_top_in[4];
@ -169,7 +169,7 @@ module sb_2__1_
(
.in({ top_left_grid_pin_42_[0], top_left_grid_pin_44_[0], top_left_grid_pin_46_[0], top_left_grid_pin_48_[0], top_right_grid_pin_1_[0], chany_bottom_in[2], chany_bottom_in[12], chanx_left_in[0], chanx_left_in[7], chanx_left_in[14] }),
.sram(mux_tree_tapbuf_size10_0_sram[0:3]),
.sram_inv(mux_tree_tapbuf_size10_0_sram_inv[0:3]),
.sram_inv(mux_top_track_0_undriven_sram_inv[0:3]),
.out(chany_top_out[0])
);
@ -179,7 +179,7 @@ module sb_2__1_
(
.in({ chany_top_in[2], chany_top_in[12], bottom_right_grid_pin_1_[0], bottom_left_grid_pin_43_[0], bottom_left_grid_pin_45_[0], bottom_left_grid_pin_47_[0], bottom_left_grid_pin_49_[0], chanx_left_in[1], chanx_left_in[8], chanx_left_in[15] }),
.sram(mux_tree_tapbuf_size10_1_sram[0:3]),
.sram_inv(mux_tree_tapbuf_size10_1_sram_inv[0:3]),
.sram_inv(mux_bottom_track_1_undriven_sram_inv[0:3]),
.out(chany_bottom_out[0])
);
@ -190,8 +190,7 @@ module sb_2__1_
.prog_clk(prog_clk[0]),
.ccff_head(ccff_head[0]),
.ccff_tail(mux_tree_tapbuf_size10_mem_0_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size10_0_sram[0:3]),
.mem_outb(mux_tree_tapbuf_size10_0_sram_inv[0:3])
.mem_out(mux_tree_tapbuf_size10_0_sram[0:3])
);
@ -201,8 +200,7 @@ module sb_2__1_
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size6_mem_0_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size10_mem_1_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size10_1_sram[0:3]),
.mem_outb(mux_tree_tapbuf_size10_1_sram_inv[0:3])
.mem_out(mux_tree_tapbuf_size10_1_sram[0:3])
);
@ -211,7 +209,7 @@ module sb_2__1_
(
.in({ top_left_grid_pin_43_[0], top_left_grid_pin_45_[0], top_left_grid_pin_47_[0], top_left_grid_pin_49_[0], chany_bottom_in[4], chany_bottom_in[13], chanx_left_in[6], chanx_left_in[13] }),
.sram(mux_tree_tapbuf_size8_0_sram[0:3]),
.sram_inv(mux_tree_tapbuf_size8_0_sram_inv[0:3]),
.sram_inv(mux_top_track_2_undriven_sram_inv[0:3]),
.out(chany_top_out[1])
);
@ -221,7 +219,7 @@ module sb_2__1_
(
.in({ top_left_grid_pin_42_[0], top_left_grid_pin_46_[0], top_right_grid_pin_1_[0], chany_bottom_in[6], chany_bottom_in[16], chanx_left_in[4], chanx_left_in[11], chanx_left_in[18] }),
.sram(mux_tree_tapbuf_size8_1_sram[0:3]),
.sram_inv(mux_tree_tapbuf_size8_1_sram_inv[0:3]),
.sram_inv(mux_top_track_8_undriven_sram_inv[0:3]),
.out(chany_top_out[4])
);
@ -231,7 +229,7 @@ module sb_2__1_
(
.in({ chany_top_in[6], chany_top_in[16], bottom_right_grid_pin_1_[0], bottom_left_grid_pin_45_[0], bottom_left_grid_pin_49_[0], chanx_left_in[4], chanx_left_in[11], chanx_left_in[18] }),
.sram(mux_tree_tapbuf_size8_2_sram[0:3]),
.sram_inv(mux_tree_tapbuf_size8_2_sram_inv[0:3]),
.sram_inv(mux_bottom_track_9_undriven_sram_inv[0:3]),
.out(chany_bottom_out[4])
);
@ -242,8 +240,7 @@ module sb_2__1_
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size10_mem_0_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size8_mem_0_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size8_0_sram[0:3]),
.mem_outb(mux_tree_tapbuf_size8_0_sram_inv[0:3])
.mem_out(mux_tree_tapbuf_size8_0_sram[0:3])
);
@ -253,8 +250,7 @@ module sb_2__1_
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size14_mem_0_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size8_mem_1_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size8_1_sram[0:3]),
.mem_outb(mux_tree_tapbuf_size8_1_sram_inv[0:3])
.mem_out(mux_tree_tapbuf_size8_1_sram[0:3])
);
@ -264,8 +260,7 @@ module sb_2__1_
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size14_mem_1_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size8_mem_2_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size8_2_sram[0:3]),
.mem_outb(mux_tree_tapbuf_size8_2_sram_inv[0:3])
.mem_out(mux_tree_tapbuf_size8_2_sram[0:3])
);
@ -274,7 +269,7 @@ module sb_2__1_
(
.in({ top_left_grid_pin_42_[0], top_left_grid_pin_43_[0], top_left_grid_pin_44_[0], top_left_grid_pin_45_[0], top_left_grid_pin_46_[0], top_left_grid_pin_47_[0], top_left_grid_pin_48_[0], top_left_grid_pin_49_[0], top_right_grid_pin_1_[0], chany_bottom_in[5], chany_bottom_in[14], chanx_left_in[5], chanx_left_in[12], chanx_left_in[19] }),
.sram(mux_tree_tapbuf_size14_0_sram[0:3]),
.sram_inv(mux_tree_tapbuf_size14_0_sram_inv[0:3]),
.sram_inv(mux_top_track_4_undriven_sram_inv[0:3]),
.out(chany_top_out[2])
);
@ -284,7 +279,7 @@ module sb_2__1_
(
.in({ chany_top_in[5], chany_top_in[14], bottom_right_grid_pin_1_[0], bottom_left_grid_pin_42_[0], bottom_left_grid_pin_43_[0], bottom_left_grid_pin_44_[0], bottom_left_grid_pin_45_[0], bottom_left_grid_pin_46_[0], bottom_left_grid_pin_47_[0], bottom_left_grid_pin_48_[0], bottom_left_grid_pin_49_[0], chanx_left_in[3], chanx_left_in[10], chanx_left_in[17] }),
.sram(mux_tree_tapbuf_size14_1_sram[0:3]),
.sram_inv(mux_tree_tapbuf_size14_1_sram_inv[0:3]),
.sram_inv(mux_bottom_track_5_undriven_sram_inv[0:3]),
.out(chany_bottom_out[2])
);
@ -295,8 +290,7 @@ module sb_2__1_
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size8_mem_0_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size14_mem_0_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size14_0_sram[0:3]),
.mem_outb(mux_tree_tapbuf_size14_0_sram_inv[0:3])
.mem_out(mux_tree_tapbuf_size14_0_sram[0:3])
);
@ -306,8 +300,7 @@ module sb_2__1_
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size9_mem_0_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size14_mem_1_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size14_1_sram[0:3]),
.mem_outb(mux_tree_tapbuf_size14_1_sram_inv[0:3])
.mem_out(mux_tree_tapbuf_size14_1_sram[0:3])
);
@ -316,7 +309,7 @@ module sb_2__1_
(
.in({ top_left_grid_pin_43_[0], top_left_grid_pin_47_[0], chany_bottom_in[8], chany_bottom_in[17], chanx_left_in[3], chanx_left_in[10], chanx_left_in[17] }),
.sram(mux_tree_tapbuf_size7_0_sram[0:2]),
.sram_inv(mux_tree_tapbuf_size7_0_sram_inv[0:2]),
.sram_inv(mux_top_track_16_undriven_sram_inv[0:2]),
.out(chany_top_out[8])
);
@ -326,7 +319,7 @@ module sb_2__1_
(
.in({ top_left_grid_pin_44_[0], top_left_grid_pin_48_[0], chany_bottom_in[9], chany_bottom_in[18], chanx_left_in[2], chanx_left_in[9], chanx_left_in[16] }),
.sram(mux_tree_tapbuf_size7_1_sram[0:2]),
.sram_inv(mux_tree_tapbuf_size7_1_sram_inv[0:2]),
.sram_inv(mux_top_track_24_undriven_sram_inv[0:2]),
.out(chany_top_out[12])
);
@ -336,7 +329,7 @@ module sb_2__1_
(
.in({ chany_top_in[8], chany_top_in[17], bottom_left_grid_pin_42_[0], bottom_left_grid_pin_46_[0], chanx_left_in[5], chanx_left_in[12], chanx_left_in[19] }),
.sram(mux_tree_tapbuf_size7_2_sram[0:2]),
.sram_inv(mux_tree_tapbuf_size7_2_sram_inv[0:2]),
.sram_inv(mux_bottom_track_17_undriven_sram_inv[0:2]),
.out(chany_bottom_out[8])
);
@ -346,7 +339,7 @@ module sb_2__1_
(
.in({ chany_top_in[0], chany_top_in[2], chany_bottom_in[2], left_bottom_grid_pin_34_[0], left_bottom_grid_pin_36_[0], left_bottom_grid_pin_38_[0], left_bottom_grid_pin_40_[0] }),
.sram(mux_tree_tapbuf_size7_3_sram[0:2]),
.sram_inv(mux_tree_tapbuf_size7_3_sram_inv[0:2]),
.sram_inv(mux_left_track_1_undriven_sram_inv[0:2]),
.out(chanx_left_out[0])
);
@ -356,7 +349,7 @@ module sb_2__1_
(
.in({ chany_top_in[4], chany_bottom_in[0], chany_bottom_in[4], left_bottom_grid_pin_35_[0], left_bottom_grid_pin_37_[0], left_bottom_grid_pin_39_[0], left_bottom_grid_pin_41_[0] }),
.sram(mux_tree_tapbuf_size7_4_sram[0:2]),
.sram_inv(mux_tree_tapbuf_size7_4_sram_inv[0:2]),
.sram_inv(mux_left_track_3_undriven_sram_inv[0:2]),
.out(chanx_left_out[1])
);
@ -366,7 +359,7 @@ module sb_2__1_
(
.in({ chany_top_in[5], chany_bottom_in[1], chany_bottom_in[5], left_bottom_grid_pin_34_[0], left_bottom_grid_pin_36_[0], left_bottom_grid_pin_38_[0], left_bottom_grid_pin_40_[0] }),
.sram(mux_tree_tapbuf_size7_5_sram[0:2]),
.sram_inv(mux_tree_tapbuf_size7_5_sram_inv[0:2]),
.sram_inv(mux_left_track_5_undriven_sram_inv[0:2]),
.out(chanx_left_out[2])
);
@ -376,7 +369,7 @@ module sb_2__1_
(
.in({ chany_top_in[6], chany_bottom_in[3], chany_bottom_in[6], left_bottom_grid_pin_35_[0], left_bottom_grid_pin_37_[0], left_bottom_grid_pin_39_[0], left_bottom_grid_pin_41_[0] }),
.sram(mux_tree_tapbuf_size7_6_sram[0:2]),
.sram_inv(mux_tree_tapbuf_size7_6_sram_inv[0:2]),
.sram_inv(mux_left_track_7_undriven_sram_inv[0:2]),
.out(chanx_left_out[3])
);
@ -387,8 +380,7 @@ module sb_2__1_
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size8_mem_1_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size7_mem_0_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size7_0_sram[0:2]),
.mem_outb(mux_tree_tapbuf_size7_0_sram_inv[0:2])
.mem_out(mux_tree_tapbuf_size7_0_sram[0:2])
);
@ -398,8 +390,7 @@ module sb_2__1_
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size7_mem_0_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size7_mem_1_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size7_1_sram[0:2]),
.mem_outb(mux_tree_tapbuf_size7_1_sram_inv[0:2])
.mem_out(mux_tree_tapbuf_size7_1_sram[0:2])
);
@ -409,8 +400,7 @@ module sb_2__1_
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size8_mem_2_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size7_mem_2_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size7_2_sram[0:2]),
.mem_outb(mux_tree_tapbuf_size7_2_sram_inv[0:2])
.mem_out(mux_tree_tapbuf_size7_2_sram[0:2])
);
@ -420,8 +410,7 @@ module sb_2__1_
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size6_mem_2_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size7_mem_3_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size7_3_sram[0:2]),
.mem_outb(mux_tree_tapbuf_size7_3_sram_inv[0:2])
.mem_out(mux_tree_tapbuf_size7_3_sram[0:2])
);
@ -431,8 +420,7 @@ module sb_2__1_
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size7_mem_3_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size7_mem_4_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size7_4_sram[0:2]),
.mem_outb(mux_tree_tapbuf_size7_4_sram_inv[0:2])
.mem_out(mux_tree_tapbuf_size7_4_sram[0:2])
);
@ -442,8 +430,7 @@ module sb_2__1_
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size7_mem_4_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size7_mem_5_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size7_5_sram[0:2]),
.mem_outb(mux_tree_tapbuf_size7_5_sram_inv[0:2])
.mem_out(mux_tree_tapbuf_size7_5_sram[0:2])
);
@ -453,8 +440,7 @@ module sb_2__1_
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size7_mem_5_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size7_mem_6_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size7_6_sram[0:2]),
.mem_outb(mux_tree_tapbuf_size7_6_sram_inv[0:2])
.mem_out(mux_tree_tapbuf_size7_6_sram[0:2])
);
@ -463,7 +449,7 @@ module sb_2__1_
(
.in({ top_left_grid_pin_45_[0], top_left_grid_pin_49_[0], chany_bottom_in[10], chanx_left_in[1], chanx_left_in[8], chanx_left_in[15] }),
.sram(mux_tree_tapbuf_size6_0_sram[0:2]),
.sram_inv(mux_tree_tapbuf_size6_0_sram_inv[0:2]),
.sram_inv(mux_top_track_32_undriven_sram_inv[0:2]),
.out(chany_top_out[16])
);
@ -473,7 +459,7 @@ module sb_2__1_
(
.in({ chany_top_in[9], chany_top_in[18], bottom_left_grid_pin_43_[0], bottom_left_grid_pin_47_[0], chanx_left_in[6], chanx_left_in[13] }),
.sram(mux_tree_tapbuf_size6_1_sram[0:2]),
.sram_inv(mux_tree_tapbuf_size6_1_sram_inv[0:2]),
.sram_inv(mux_bottom_track_25_undriven_sram_inv[0:2]),
.out(chany_bottom_out[12])
);
@ -483,7 +469,7 @@ module sb_2__1_
(
.in({ chany_top_in[10], bottom_left_grid_pin_44_[0], bottom_left_grid_pin_48_[0], chanx_left_in[0], chanx_left_in[7], chanx_left_in[14] }),
.sram(mux_tree_tapbuf_size6_2_sram[0:2]),
.sram_inv(mux_tree_tapbuf_size6_2_sram_inv[0:2]),
.sram_inv(mux_bottom_track_33_undriven_sram_inv[0:2]),
.out(chany_bottom_out[16])
);
@ -494,8 +480,7 @@ module sb_2__1_
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size7_mem_1_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size6_mem_0_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size6_0_sram[0:2]),
.mem_outb(mux_tree_tapbuf_size6_0_sram_inv[0:2])
.mem_out(mux_tree_tapbuf_size6_0_sram[0:2])
);
@ -505,8 +490,7 @@ module sb_2__1_
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size7_mem_2_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size6_mem_1_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size6_1_sram[0:2]),
.mem_outb(mux_tree_tapbuf_size6_1_sram_inv[0:2])
.mem_out(mux_tree_tapbuf_size6_1_sram[0:2])
);
@ -516,8 +500,7 @@ module sb_2__1_
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size6_mem_1_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size6_mem_2_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size6_2_sram[0:2]),
.mem_outb(mux_tree_tapbuf_size6_2_sram_inv[0:2])
.mem_out(mux_tree_tapbuf_size6_2_sram[0:2])
);
@ -526,7 +509,7 @@ module sb_2__1_
(
.in({ chany_top_in[4], chany_top_in[13], bottom_left_grid_pin_42_[0], bottom_left_grid_pin_44_[0], bottom_left_grid_pin_46_[0], bottom_left_grid_pin_48_[0], chanx_left_in[2], chanx_left_in[9], chanx_left_in[16] }),
.sram(mux_tree_tapbuf_size9_0_sram[0:3]),
.sram_inv(mux_tree_tapbuf_size9_0_sram_inv[0:3]),
.sram_inv(mux_bottom_track_3_undriven_sram_inv[0:3]),
.out(chany_bottom_out[1])
);
@ -537,8 +520,7 @@ module sb_2__1_
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size10_mem_1_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size9_mem_0_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size9_0_sram[0:3]),
.mem_outb(mux_tree_tapbuf_size9_0_sram_inv[0:3])
.mem_out(mux_tree_tapbuf_size9_0_sram[0:3])
);
@ -547,7 +529,7 @@ module sb_2__1_
(
.in({ chany_top_in[8], chany_bottom_in[7:8], left_bottom_grid_pin_34_[0] }),
.sram(mux_tree_tapbuf_size4_0_sram[0:2]),
.sram_inv(mux_tree_tapbuf_size4_0_sram_inv[0:2]),
.sram_inv(mux_left_track_9_undriven_sram_inv[0:2]),
.out(chanx_left_out[4])
);
@ -557,7 +539,7 @@ module sb_2__1_
(
.in({ chany_top_in[9], chany_bottom_in[9], chany_bottom_in[11], left_bottom_grid_pin_35_[0] }),
.sram(mux_tree_tapbuf_size4_1_sram[0:2]),
.sram_inv(mux_tree_tapbuf_size4_1_sram_inv[0:2]),
.sram_inv(mux_left_track_11_undriven_sram_inv[0:2]),
.out(chanx_left_out[5])
);
@ -567,7 +549,7 @@ module sb_2__1_
(
.in({ chany_top_in[10], chany_bottom_in[10], chany_bottom_in[15], left_bottom_grid_pin_36_[0] }),
.sram(mux_tree_tapbuf_size4_2_sram[0:2]),
.sram_inv(mux_tree_tapbuf_size4_2_sram_inv[0:2]),
.sram_inv(mux_left_track_13_undriven_sram_inv[0:2]),
.out(chanx_left_out[6])
);
@ -577,7 +559,7 @@ module sb_2__1_
(
.in({ chany_top_in[12], chany_bottom_in[12], chany_bottom_in[19], left_bottom_grid_pin_37_[0] }),
.sram(mux_tree_tapbuf_size4_3_sram[0:2]),
.sram_inv(mux_tree_tapbuf_size4_3_sram_inv[0:2]),
.sram_inv(mux_left_track_15_undriven_sram_inv[0:2]),
.out(chanx_left_out[7])
);
@ -588,8 +570,7 @@ module sb_2__1_
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size7_mem_6_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size4_mem_0_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size4_0_sram[0:2]),
.mem_outb(mux_tree_tapbuf_size4_0_sram_inv[0:2])
.mem_out(mux_tree_tapbuf_size4_0_sram[0:2])
);
@ -599,8 +580,7 @@ module sb_2__1_
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size4_mem_0_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size4_mem_1_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size4_1_sram[0:2]),
.mem_outb(mux_tree_tapbuf_size4_1_sram_inv[0:2])
.mem_out(mux_tree_tapbuf_size4_1_sram[0:2])
);
@ -610,8 +590,7 @@ module sb_2__1_
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size4_mem_1_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size4_mem_2_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size4_2_sram[0:2]),
.mem_outb(mux_tree_tapbuf_size4_2_sram_inv[0:2])
.mem_out(mux_tree_tapbuf_size4_2_sram[0:2])
);
@ -621,8 +600,7 @@ module sb_2__1_
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size4_mem_2_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size4_mem_3_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size4_3_sram[0:2]),
.mem_outb(mux_tree_tapbuf_size4_3_sram_inv[0:2])
.mem_out(mux_tree_tapbuf_size4_3_sram[0:2])
);
@ -631,7 +609,7 @@ module sb_2__1_
(
.in({ chany_top_in[13], chany_bottom_in[13], left_bottom_grid_pin_38_[0] }),
.sram(mux_tree_tapbuf_size3_0_sram[0:1]),
.sram_inv(mux_tree_tapbuf_size3_0_sram_inv[0:1]),
.sram_inv(mux_left_track_17_undriven_sram_inv[0:1]),
.out(chanx_left_out[8])
);
@ -641,7 +619,7 @@ module sb_2__1_
(
.in({ chany_top_in[14], chany_bottom_in[14], left_bottom_grid_pin_39_[0] }),
.sram(mux_tree_tapbuf_size3_1_sram[0:1]),
.sram_inv(mux_tree_tapbuf_size3_1_sram_inv[0:1]),
.sram_inv(mux_left_track_19_undriven_sram_inv[0:1]),
.out(chanx_left_out[9])
);
@ -651,7 +629,7 @@ module sb_2__1_
(
.in({ chany_top_in[16], chany_bottom_in[16], left_bottom_grid_pin_40_[0] }),
.sram(mux_tree_tapbuf_size3_2_sram[0:1]),
.sram_inv(mux_tree_tapbuf_size3_2_sram_inv[0:1]),
.sram_inv(mux_left_track_21_undriven_sram_inv[0:1]),
.out(chanx_left_out[10])
);
@ -661,7 +639,7 @@ module sb_2__1_
(
.in({ chany_top_in[17], chany_bottom_in[17], left_bottom_grid_pin_41_[0] }),
.sram(mux_tree_tapbuf_size3_3_sram[0:1]),
.sram_inv(mux_tree_tapbuf_size3_3_sram_inv[0:1]),
.sram_inv(mux_left_track_23_undriven_sram_inv[0:1]),
.out(chanx_left_out[11])
);
@ -671,7 +649,7 @@ module sb_2__1_
(
.in({ chany_top_in[18], chany_bottom_in[18], left_bottom_grid_pin_34_[0] }),
.sram(mux_tree_tapbuf_size3_4_sram[0:1]),
.sram_inv(mux_tree_tapbuf_size3_4_sram_inv[0:1]),
.sram_inv(mux_left_track_25_undriven_sram_inv[0:1]),
.out(chanx_left_out[12])
);
@ -682,8 +660,7 @@ module sb_2__1_
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size4_mem_3_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size3_mem_0_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size3_0_sram[0:1]),
.mem_outb(mux_tree_tapbuf_size3_0_sram_inv[0:1])
.mem_out(mux_tree_tapbuf_size3_0_sram[0:1])
);
@ -693,8 +670,7 @@ module sb_2__1_
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size3_mem_0_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size3_mem_1_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size3_1_sram[0:1]),
.mem_outb(mux_tree_tapbuf_size3_1_sram_inv[0:1])
.mem_out(mux_tree_tapbuf_size3_1_sram[0:1])
);
@ -704,8 +680,7 @@ module sb_2__1_
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size3_mem_1_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size3_mem_2_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size3_2_sram[0:1]),
.mem_outb(mux_tree_tapbuf_size3_2_sram_inv[0:1])
.mem_out(mux_tree_tapbuf_size3_2_sram[0:1])
);
@ -715,8 +690,7 @@ module sb_2__1_
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size3_mem_2_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size3_mem_3_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size3_3_sram[0:1]),
.mem_outb(mux_tree_tapbuf_size3_3_sram_inv[0:1])
.mem_out(mux_tree_tapbuf_size3_3_sram[0:1])
);
@ -726,8 +700,7 @@ module sb_2__1_
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size3_mem_3_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size3_mem_4_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size3_4_sram[0:1]),
.mem_outb(mux_tree_tapbuf_size3_4_sram_inv[0:1])
.mem_out(mux_tree_tapbuf_size3_4_sram[0:1])
);
@ -736,7 +709,7 @@ module sb_2__1_
(
.in({ chany_top_in[19], left_bottom_grid_pin_36_[0] }),
.sram(mux_tree_tapbuf_size2_0_sram[0:1]),
.sram_inv(mux_tree_tapbuf_size2_0_sram_inv[0:1]),
.sram_inv(mux_left_track_29_undriven_sram_inv[0:1]),
.out(chanx_left_out[14])
);
@ -746,7 +719,7 @@ module sb_2__1_
(
.in({ chany_top_in[15], left_bottom_grid_pin_37_[0] }),
.sram(mux_tree_tapbuf_size2_1_sram[0:1]),
.sram_inv(mux_tree_tapbuf_size2_1_sram_inv[0:1]),
.sram_inv(mux_left_track_31_undriven_sram_inv[0:1]),
.out(chanx_left_out[15])
);
@ -756,7 +729,7 @@ module sb_2__1_
(
.in({ chany_top_in[11], left_bottom_grid_pin_38_[0] }),
.sram(mux_tree_tapbuf_size2_2_sram[0:1]),
.sram_inv(mux_tree_tapbuf_size2_2_sram_inv[0:1]),
.sram_inv(mux_left_track_33_undriven_sram_inv[0:1]),
.out(chanx_left_out[16])
);
@ -766,7 +739,7 @@ module sb_2__1_
(
.in({ chany_top_in[7], left_bottom_grid_pin_39_[0] }),
.sram(mux_tree_tapbuf_size2_3_sram[0:1]),
.sram_inv(mux_tree_tapbuf_size2_3_sram_inv[0:1]),
.sram_inv(mux_left_track_35_undriven_sram_inv[0:1]),
.out(chanx_left_out[17])
);
@ -776,7 +749,7 @@ module sb_2__1_
(
.in({ chany_top_in[3], left_bottom_grid_pin_40_[0] }),
.sram(mux_tree_tapbuf_size2_4_sram[0:1]),
.sram_inv(mux_tree_tapbuf_size2_4_sram_inv[0:1]),
.sram_inv(mux_left_track_37_undriven_sram_inv[0:1]),
.out(chanx_left_out[18])
);
@ -786,7 +759,7 @@ module sb_2__1_
(
.in({ chany_top_in[1], left_bottom_grid_pin_41_[0] }),
.sram(mux_tree_tapbuf_size2_5_sram[0:1]),
.sram_inv(mux_tree_tapbuf_size2_5_sram_inv[0:1]),
.sram_inv(mux_left_track_39_undriven_sram_inv[0:1]),
.out(chanx_left_out[19])
);
@ -797,8 +770,7 @@ module sb_2__1_
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size3_mem_4_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size2_mem_0_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size2_0_sram[0:1]),
.mem_outb(mux_tree_tapbuf_size2_0_sram_inv[0:1])
.mem_out(mux_tree_tapbuf_size2_0_sram[0:1])
);
@ -808,8 +780,7 @@ module sb_2__1_
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size2_mem_0_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size2_mem_1_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size2_1_sram[0:1]),
.mem_outb(mux_tree_tapbuf_size2_1_sram_inv[0:1])
.mem_out(mux_tree_tapbuf_size2_1_sram[0:1])
);
@ -819,8 +790,7 @@ module sb_2__1_
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size2_mem_1_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size2_mem_2_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size2_2_sram[0:1]),
.mem_outb(mux_tree_tapbuf_size2_2_sram_inv[0:1])
.mem_out(mux_tree_tapbuf_size2_2_sram[0:1])
);
@ -830,8 +800,7 @@ module sb_2__1_
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size2_mem_2_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size2_mem_3_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size2_3_sram[0:1]),
.mem_outb(mux_tree_tapbuf_size2_3_sram_inv[0:1])
.mem_out(mux_tree_tapbuf_size2_3_sram[0:1])
);
@ -841,8 +810,7 @@ module sb_2__1_
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size2_mem_3_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size2_mem_4_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size2_4_sram[0:1]),
.mem_outb(mux_tree_tapbuf_size2_4_sram_inv[0:1])
.mem_out(mux_tree_tapbuf_size2_4_sram[0:1])
);
@ -852,8 +820,7 @@ module sb_2__1_
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size2_mem_4_ccff_tail[0]),
.ccff_tail(ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size2_5_sram[0:1]),
.mem_outb(mux_tree_tapbuf_size2_5_sram_inv[0:1])
.mem_out(mux_tree_tapbuf_size2_5_sram[0:1])
);

245
FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/routing/sb_2__2_.v
View File

@ -32,54 +32,65 @@ module sb_2__2_
output SC_OUT_TOP;
output SC_OUT_BOT;
wire [0:1] mux_bottom_track_11_undriven_sram_inv;
wire [0:1] mux_bottom_track_13_undriven_sram_inv;
wire [0:1] mux_bottom_track_15_undriven_sram_inv;
wire [0:1] mux_bottom_track_17_undriven_sram_inv;
wire [0:1] mux_bottom_track_19_undriven_sram_inv;
wire [0:2] mux_bottom_track_1_undriven_sram_inv;
wire [0:1] mux_bottom_track_21_undriven_sram_inv;
wire [0:1] mux_bottom_track_23_undriven_sram_inv;
wire [0:1] mux_bottom_track_25_undriven_sram_inv;
wire [0:1] mux_bottom_track_27_undriven_sram_inv;
wire [0:1] mux_bottom_track_29_undriven_sram_inv;
wire [0:2] mux_bottom_track_3_undriven_sram_inv;
wire [0:2] mux_bottom_track_5_undriven_sram_inv;
wire [0:2] mux_bottom_track_7_undriven_sram_inv;
wire [0:1] mux_bottom_track_9_undriven_sram_inv;
wire [0:1] mux_left_track_11_undriven_sram_inv;
wire [0:1] mux_left_track_13_undriven_sram_inv;
wire [0:1] mux_left_track_15_undriven_sram_inv;
wire [0:1] mux_left_track_17_undriven_sram_inv;
wire [0:1] mux_left_track_19_undriven_sram_inv;
wire [0:2] mux_left_track_1_undriven_sram_inv;
wire [0:1] mux_left_track_21_undriven_sram_inv;
wire [0:1] mux_left_track_23_undriven_sram_inv;
wire [0:1] mux_left_track_25_undriven_sram_inv;
wire [0:1] mux_left_track_27_undriven_sram_inv;
wire [0:1] mux_left_track_29_undriven_sram_inv;
wire [0:1] mux_left_track_31_undriven_sram_inv;
wire [0:1] mux_left_track_33_undriven_sram_inv;
wire [0:1] mux_left_track_35_undriven_sram_inv;
wire [0:1] mux_left_track_37_undriven_sram_inv;
wire [0:1] mux_left_track_39_undriven_sram_inv;
wire [0:2] mux_left_track_3_undriven_sram_inv;
wire [0:2] mux_left_track_5_undriven_sram_inv;
wire [0:2] mux_left_track_7_undriven_sram_inv;
wire [0:1] mux_left_track_9_undriven_sram_inv;
wire [0:1] mux_tree_tapbuf_size2_0_sram;
wire [0:1] mux_tree_tapbuf_size2_0_sram_inv;
wire [0:1] mux_tree_tapbuf_size2_10_sram;
wire [0:1] mux_tree_tapbuf_size2_10_sram_inv;
wire [0:1] mux_tree_tapbuf_size2_11_sram;
wire [0:1] mux_tree_tapbuf_size2_11_sram_inv;
wire [0:1] mux_tree_tapbuf_size2_12_sram;
wire [0:1] mux_tree_tapbuf_size2_12_sram_inv;
wire [0:1] mux_tree_tapbuf_size2_13_sram;
wire [0:1] mux_tree_tapbuf_size2_13_sram_inv;
wire [0:1] mux_tree_tapbuf_size2_14_sram;
wire [0:1] mux_tree_tapbuf_size2_14_sram_inv;
wire [0:1] mux_tree_tapbuf_size2_15_sram;
wire [0:1] mux_tree_tapbuf_size2_15_sram_inv;
wire [0:1] mux_tree_tapbuf_size2_16_sram;
wire [0:1] mux_tree_tapbuf_size2_16_sram_inv;
wire [0:1] mux_tree_tapbuf_size2_17_sram;
wire [0:1] mux_tree_tapbuf_size2_17_sram_inv;
wire [0:1] mux_tree_tapbuf_size2_18_sram;
wire [0:1] mux_tree_tapbuf_size2_18_sram_inv;
wire [0:1] mux_tree_tapbuf_size2_19_sram;
wire [0:1] mux_tree_tapbuf_size2_19_sram_inv;
wire [0:1] mux_tree_tapbuf_size2_1_sram;
wire [0:1] mux_tree_tapbuf_size2_1_sram_inv;
wire [0:1] mux_tree_tapbuf_size2_20_sram;
wire [0:1] mux_tree_tapbuf_size2_20_sram_inv;
wire [0:1] mux_tree_tapbuf_size2_21_sram;
wire [0:1] mux_tree_tapbuf_size2_21_sram_inv;
wire [0:1] mux_tree_tapbuf_size2_22_sram;
wire [0:1] mux_tree_tapbuf_size2_22_sram_inv;
wire [0:1] mux_tree_tapbuf_size2_23_sram;
wire [0:1] mux_tree_tapbuf_size2_23_sram_inv;
wire [0:1] mux_tree_tapbuf_size2_2_sram;
wire [0:1] mux_tree_tapbuf_size2_2_sram_inv;
wire [0:1] mux_tree_tapbuf_size2_3_sram;
wire [0:1] mux_tree_tapbuf_size2_3_sram_inv;
wire [0:1] mux_tree_tapbuf_size2_4_sram;
wire [0:1] mux_tree_tapbuf_size2_4_sram_inv;
wire [0:1] mux_tree_tapbuf_size2_5_sram;
wire [0:1] mux_tree_tapbuf_size2_5_sram_inv;
wire [0:1] mux_tree_tapbuf_size2_6_sram;
wire [0:1] mux_tree_tapbuf_size2_6_sram_inv;
wire [0:1] mux_tree_tapbuf_size2_7_sram;
wire [0:1] mux_tree_tapbuf_size2_7_sram_inv;
wire [0:1] mux_tree_tapbuf_size2_8_sram;
wire [0:1] mux_tree_tapbuf_size2_8_sram_inv;
wire [0:1] mux_tree_tapbuf_size2_9_sram;
wire [0:1] mux_tree_tapbuf_size2_9_sram_inv;
wire [0:0] mux_tree_tapbuf_size2_mem_0_ccff_tail;
wire [0:0] mux_tree_tapbuf_size2_mem_10_ccff_tail;
wire [0:0] mux_tree_tapbuf_size2_mem_11_ccff_tail;
@ -104,34 +115,23 @@ module sb_2__2_
wire [0:0] mux_tree_tapbuf_size2_mem_8_ccff_tail;
wire [0:0] mux_tree_tapbuf_size2_mem_9_ccff_tail;
wire [0:1] mux_tree_tapbuf_size3_0_sram;
wire [0:1] mux_tree_tapbuf_size3_0_sram_inv;
wire [0:1] mux_tree_tapbuf_size3_1_sram;
wire [0:1] mux_tree_tapbuf_size3_1_sram_inv;
wire [0:1] mux_tree_tapbuf_size3_2_sram;
wire [0:1] mux_tree_tapbuf_size3_2_sram_inv;
wire [0:0] mux_tree_tapbuf_size3_mem_0_ccff_tail;
wire [0:0] mux_tree_tapbuf_size3_mem_1_ccff_tail;
wire [0:0] mux_tree_tapbuf_size3_mem_2_ccff_tail;
wire [0:2] mux_tree_tapbuf_size5_0_sram;
wire [0:2] mux_tree_tapbuf_size5_0_sram_inv;
wire [0:2] mux_tree_tapbuf_size5_1_sram;
wire [0:2] mux_tree_tapbuf_size5_1_sram_inv;
wire [0:2] mux_tree_tapbuf_size5_2_sram;
wire [0:2] mux_tree_tapbuf_size5_2_sram_inv;
wire [0:2] mux_tree_tapbuf_size5_3_sram;
wire [0:2] mux_tree_tapbuf_size5_3_sram_inv;
wire [0:0] mux_tree_tapbuf_size5_mem_0_ccff_tail;
wire [0:0] mux_tree_tapbuf_size5_mem_1_ccff_tail;
wire [0:0] mux_tree_tapbuf_size5_mem_2_ccff_tail;
wire [0:0] mux_tree_tapbuf_size5_mem_3_ccff_tail;
wire [0:2] mux_tree_tapbuf_size6_0_sram;
wire [0:2] mux_tree_tapbuf_size6_0_sram_inv;
wire [0:2] mux_tree_tapbuf_size6_1_sram;
wire [0:2] mux_tree_tapbuf_size6_1_sram_inv;
wire [0:2] mux_tree_tapbuf_size6_2_sram;
wire [0:2] mux_tree_tapbuf_size6_2_sram_inv;
wire [0:2] mux_tree_tapbuf_size6_3_sram;
wire [0:2] mux_tree_tapbuf_size6_3_sram_inv;
wire [0:0] mux_tree_tapbuf_size6_mem_0_ccff_tail;
wire [0:0] mux_tree_tapbuf_size6_mem_1_ccff_tail;
wire [0:0] mux_tree_tapbuf_size6_mem_2_ccff_tail;
@ -149,7 +149,7 @@ module sb_2__2_
(
.in({ bottom_right_grid_pin_1_[0], bottom_left_grid_pin_43_[0], bottom_left_grid_pin_45_[0], bottom_left_grid_pin_47_[0], bottom_left_grid_pin_49_[0], chanx_left_in[1] }),
.sram(mux_tree_tapbuf_size6_0_sram[0:2]),
.sram_inv(mux_tree_tapbuf_size6_0_sram_inv[0:2]),
.sram_inv(mux_bottom_track_1_undriven_sram_inv[0:2]),
.out(chany_bottom_out[0])
);
@ -159,7 +159,7 @@ module sb_2__2_
(
.in({ bottom_right_grid_pin_1_[0], bottom_left_grid_pin_43_[0], bottom_left_grid_pin_45_[0], bottom_left_grid_pin_47_[0], bottom_left_grid_pin_49_[0], chanx_left_in[3] }),
.sram(mux_tree_tapbuf_size6_1_sram[0:2]),
.sram_inv(mux_tree_tapbuf_size6_1_sram_inv[0:2]),
.sram_inv(mux_bottom_track_5_undriven_sram_inv[0:2]),
.out(chany_bottom_out[2])
);
@ -169,7 +169,7 @@ module sb_2__2_
(
.in({ chany_bottom_in[19], left_top_grid_pin_1_[0], left_bottom_grid_pin_35_[0], left_bottom_grid_pin_37_[0], left_bottom_grid_pin_39_[0], left_bottom_grid_pin_41_[0] }),
.sram(mux_tree_tapbuf_size6_2_sram[0:2]),
.sram_inv(mux_tree_tapbuf_size6_2_sram_inv[0:2]),
.sram_inv(mux_left_track_1_undriven_sram_inv[0:2]),
.out(chanx_left_out[0])
);
@ -179,7 +179,7 @@ module sb_2__2_
(
.in({ chany_bottom_in[1], left_top_grid_pin_1_[0], left_bottom_grid_pin_35_[0], left_bottom_grid_pin_37_[0], left_bottom_grid_pin_39_[0], left_bottom_grid_pin_41_[0] }),
.sram(mux_tree_tapbuf_size6_3_sram[0:2]),
.sram_inv(mux_tree_tapbuf_size6_3_sram_inv[0:2]),
.sram_inv(mux_left_track_5_undriven_sram_inv[0:2]),
.out(chanx_left_out[2])
);
@ -190,8 +190,7 @@ module sb_2__2_
.prog_clk(prog_clk[0]),
.ccff_head(ccff_head[0]),
.ccff_tail(mux_tree_tapbuf_size6_mem_0_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size6_0_sram[0:2]),
.mem_outb(mux_tree_tapbuf_size6_0_sram_inv[0:2])
.mem_out(mux_tree_tapbuf_size6_0_sram[0:2])
);
@ -201,8 +200,7 @@ module sb_2__2_
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size5_mem_0_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size6_mem_1_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size6_1_sram[0:2]),
.mem_outb(mux_tree_tapbuf_size6_1_sram_inv[0:2])
.mem_out(mux_tree_tapbuf_size6_1_sram[0:2])
);
@ -212,8 +210,7 @@ module sb_2__2_
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size2_mem_9_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size6_mem_2_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size6_2_sram[0:2]),
.mem_outb(mux_tree_tapbuf_size6_2_sram_inv[0:2])
.mem_out(mux_tree_tapbuf_size6_2_sram[0:2])
);
@ -223,8 +220,7 @@ module sb_2__2_
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size5_mem_2_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size6_mem_3_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size6_3_sram[0:2]),
.mem_outb(mux_tree_tapbuf_size6_3_sram_inv[0:2])
.mem_out(mux_tree_tapbuf_size6_3_sram[0:2])
);
@ -233,7 +229,7 @@ module sb_2__2_
(
.in({ bottom_left_grid_pin_42_[0], bottom_left_grid_pin_44_[0], bottom_left_grid_pin_46_[0], bottom_left_grid_pin_48_[0], chanx_left_in[2] }),
.sram(mux_tree_tapbuf_size5_0_sram[0:2]),
.sram_inv(mux_tree_tapbuf_size5_0_sram_inv[0:2]),
.sram_inv(mux_bottom_track_3_undriven_sram_inv[0:2]),
.out(chany_bottom_out[1])
);
@ -243,7 +239,7 @@ module sb_2__2_
(
.in({ bottom_left_grid_pin_42_[0], bottom_left_grid_pin_44_[0], bottom_left_grid_pin_46_[0], bottom_left_grid_pin_48_[0], chanx_left_in[4] }),
.sram(mux_tree_tapbuf_size5_1_sram[0:2]),
.sram_inv(mux_tree_tapbuf_size5_1_sram_inv[0:2]),
.sram_inv(mux_bottom_track_7_undriven_sram_inv[0:2]),
.out(chany_bottom_out[3])
);
@ -253,7 +249,7 @@ module sb_2__2_
(
.in({ chany_bottom_in[0], left_bottom_grid_pin_34_[0], left_bottom_grid_pin_36_[0], left_bottom_grid_pin_38_[0], left_bottom_grid_pin_40_[0] }),
.sram(mux_tree_tapbuf_size5_2_sram[0:2]),
.sram_inv(mux_tree_tapbuf_size5_2_sram_inv[0:2]),
.sram_inv(mux_left_track_3_undriven_sram_inv[0:2]),
.out(chanx_left_out[1])
);
@ -263,7 +259,7 @@ module sb_2__2_
(
.in({ chany_bottom_in[2], left_bottom_grid_pin_34_[0], left_bottom_grid_pin_36_[0], left_bottom_grid_pin_38_[0], left_bottom_grid_pin_40_[0] }),
.sram(mux_tree_tapbuf_size5_3_sram[0:2]),
.sram_inv(mux_tree_tapbuf_size5_3_sram_inv[0:2]),
.sram_inv(mux_left_track_7_undriven_sram_inv[0:2]),
.out(chanx_left_out[3])
);
@ -274,8 +270,7 @@ module sb_2__2_
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size6_mem_0_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size5_mem_0_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size5_0_sram[0:2]),
.mem_outb(mux_tree_tapbuf_size5_0_sram_inv[0:2])
.mem_out(mux_tree_tapbuf_size5_0_sram[0:2])
);
@ -285,8 +280,7 @@ module sb_2__2_
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size6_mem_1_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size5_mem_1_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size5_1_sram[0:2]),
.mem_outb(mux_tree_tapbuf_size5_1_sram_inv[0:2])
.mem_out(mux_tree_tapbuf_size5_1_sram[0:2])
);
@ -296,8 +290,7 @@ module sb_2__2_
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size6_mem_2_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size5_mem_2_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size5_2_sram[0:2]),
.mem_outb(mux_tree_tapbuf_size5_2_sram_inv[0:2])
.mem_out(mux_tree_tapbuf_size5_2_sram[0:2])
);
@ -307,8 +300,7 @@ module sb_2__2_
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size6_mem_3_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size5_mem_3_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size5_3_sram[0:2]),
.mem_outb(mux_tree_tapbuf_size5_3_sram_inv[0:2])
.mem_out(mux_tree_tapbuf_size5_3_sram[0:2])
);
@ -317,7 +309,7 @@ module sb_2__2_
(
.in({ bottom_right_grid_pin_1_[0], chanx_left_in[5] }),
.sram(mux_tree_tapbuf_size2_0_sram[0:1]),
.sram_inv(mux_tree_tapbuf_size2_0_sram_inv[0:1]),
.sram_inv(mux_bottom_track_9_undriven_sram_inv[0:1]),
.out(chany_bottom_out[4])
);
@ -327,7 +319,7 @@ module sb_2__2_
(
.in({ bottom_left_grid_pin_42_[0], chanx_left_in[6] }),
.sram(mux_tree_tapbuf_size2_1_sram[0:1]),
.sram_inv(mux_tree_tapbuf_size2_1_sram_inv[0:1]),
.sram_inv(mux_bottom_track_11_undriven_sram_inv[0:1]),
.out(chany_bottom_out[5])
);
@ -337,7 +329,7 @@ module sb_2__2_
(
.in({ bottom_left_grid_pin_43_[0], chanx_left_in[7] }),
.sram(mux_tree_tapbuf_size2_2_sram[0:1]),
.sram_inv(mux_tree_tapbuf_size2_2_sram_inv[0:1]),
.sram_inv(mux_bottom_track_13_undriven_sram_inv[0:1]),
.out(chany_bottom_out[6])
);
@ -347,7 +339,7 @@ module sb_2__2_
(
.in({ bottom_left_grid_pin_44_[0], chanx_left_in[8] }),
.sram(mux_tree_tapbuf_size2_3_sram[0:1]),
.sram_inv(mux_tree_tapbuf_size2_3_sram_inv[0:1]),
.sram_inv(mux_bottom_track_15_undriven_sram_inv[0:1]),
.out(chany_bottom_out[7])
);
@ -357,7 +349,7 @@ module sb_2__2_
(
.in({ bottom_left_grid_pin_45_[0], chanx_left_in[9] }),
.sram(mux_tree_tapbuf_size2_4_sram[0:1]),
.sram_inv(mux_tree_tapbuf_size2_4_sram_inv[0:1]),
.sram_inv(mux_bottom_track_17_undriven_sram_inv[0:1]),
.out(chany_bottom_out[8])
);
@ -367,7 +359,7 @@ module sb_2__2_
(
.in({ bottom_left_grid_pin_46_[0], chanx_left_in[10] }),
.sram(mux_tree_tapbuf_size2_5_sram[0:1]),
.sram_inv(mux_tree_tapbuf_size2_5_sram_inv[0:1]),
.sram_inv(mux_bottom_track_19_undriven_sram_inv[0:1]),
.out(chany_bottom_out[9])
);
@ -377,7 +369,7 @@ module sb_2__2_
(
.in({ bottom_left_grid_pin_47_[0], chanx_left_in[11] }),
.sram(mux_tree_tapbuf_size2_6_sram[0:1]),
.sram_inv(mux_tree_tapbuf_size2_6_sram_inv[0:1]),
.sram_inv(mux_bottom_track_21_undriven_sram_inv[0:1]),
.out(chany_bottom_out[10])
);
@ -387,7 +379,7 @@ module sb_2__2_
(
.in({ bottom_left_grid_pin_48_[0], chanx_left_in[12] }),
.sram(mux_tree_tapbuf_size2_7_sram[0:1]),
.sram_inv(mux_tree_tapbuf_size2_7_sram_inv[0:1]),
.sram_inv(mux_bottom_track_23_undriven_sram_inv[0:1]),
.out(chany_bottom_out[11])
);
@ -397,7 +389,7 @@ module sb_2__2_
(
.in({ bottom_left_grid_pin_42_[0], chanx_left_in[14] }),
.sram(mux_tree_tapbuf_size2_8_sram[0:1]),
.sram_inv(mux_tree_tapbuf_size2_8_sram_inv[0:1]),
.sram_inv(mux_bottom_track_27_undriven_sram_inv[0:1]),
.out(chany_bottom_out[13])
);
@ -407,7 +399,7 @@ module sb_2__2_
(
.in({ bottom_left_grid_pin_43_[0], chanx_left_in[15] }),
.sram(mux_tree_tapbuf_size2_9_sram[0:1]),
.sram_inv(mux_tree_tapbuf_size2_9_sram_inv[0:1]),
.sram_inv(mux_bottom_track_29_undriven_sram_inv[0:1]),
.out(chany_bottom_out[14])
);
@ -417,7 +409,7 @@ module sb_2__2_
(
.in({ chany_bottom_in[4], left_bottom_grid_pin_34_[0] }),
.sram(mux_tree_tapbuf_size2_10_sram[0:1]),
.sram_inv(mux_tree_tapbuf_size2_10_sram_inv[0:1]),
.sram_inv(mux_left_track_11_undriven_sram_inv[0:1]),
.out(chanx_left_out[5])
);
@ -427,7 +419,7 @@ module sb_2__2_
(
.in({ chany_bottom_in[5], left_bottom_grid_pin_35_[0] }),
.sram(mux_tree_tapbuf_size2_11_sram[0:1]),
.sram_inv(mux_tree_tapbuf_size2_11_sram_inv[0:1]),
.sram_inv(mux_left_track_13_undriven_sram_inv[0:1]),
.out(chanx_left_out[6])
);
@ -437,7 +429,7 @@ module sb_2__2_
(
.in({ chany_bottom_in[6], left_bottom_grid_pin_36_[0] }),
.sram(mux_tree_tapbuf_size2_12_sram[0:1]),
.sram_inv(mux_tree_tapbuf_size2_12_sram_inv[0:1]),
.sram_inv(mux_left_track_15_undriven_sram_inv[0:1]),
.out(chanx_left_out[7])
);
@ -447,7 +439,7 @@ module sb_2__2_
(
.in({ chany_bottom_in[7], left_bottom_grid_pin_37_[0] }),
.sram(mux_tree_tapbuf_size2_13_sram[0:1]),
.sram_inv(mux_tree_tapbuf_size2_13_sram_inv[0:1]),
.sram_inv(mux_left_track_17_undriven_sram_inv[0:1]),
.out(chanx_left_out[8])
);
@ -457,7 +449,7 @@ module sb_2__2_
(
.in({ chany_bottom_in[8], left_bottom_grid_pin_38_[0] }),
.sram(mux_tree_tapbuf_size2_14_sram[0:1]),
.sram_inv(mux_tree_tapbuf_size2_14_sram_inv[0:1]),
.sram_inv(mux_left_track_19_undriven_sram_inv[0:1]),
.out(chanx_left_out[9])
);
@ -467,7 +459,7 @@ module sb_2__2_
(
.in({ chany_bottom_in[9], left_bottom_grid_pin_39_[0] }),
.sram(mux_tree_tapbuf_size2_15_sram[0:1]),
.sram_inv(mux_tree_tapbuf_size2_15_sram_inv[0:1]),
.sram_inv(mux_left_track_21_undriven_sram_inv[0:1]),
.out(chanx_left_out[10])
);
@ -477,7 +469,7 @@ module sb_2__2_
(
.in({ chany_bottom_in[10], left_bottom_grid_pin_40_[0] }),
.sram(mux_tree_tapbuf_size2_16_sram[0:1]),
.sram_inv(mux_tree_tapbuf_size2_16_sram_inv[0:1]),
.sram_inv(mux_left_track_23_undriven_sram_inv[0:1]),
.out(chanx_left_out[11])
);
@ -487,7 +479,7 @@ module sb_2__2_
(
.in({ chany_bottom_in[12], left_bottom_grid_pin_34_[0] }),
.sram(mux_tree_tapbuf_size2_17_sram[0:1]),
.sram_inv(mux_tree_tapbuf_size2_17_sram_inv[0:1]),
.sram_inv(mux_left_track_27_undriven_sram_inv[0:1]),
.out(chanx_left_out[13])
);
@ -497,7 +489,7 @@ module sb_2__2_
(
.in({ chany_bottom_in[13], left_bottom_grid_pin_35_[0] }),
.sram(mux_tree_tapbuf_size2_18_sram[0:1]),
.sram_inv(mux_tree_tapbuf_size2_18_sram_inv[0:1]),
.sram_inv(mux_left_track_29_undriven_sram_inv[0:1]),
.out(chanx_left_out[14])
);
@ -507,7 +499,7 @@ module sb_2__2_
(
.in({ chany_bottom_in[14], left_bottom_grid_pin_36_[0] }),
.sram(mux_tree_tapbuf_size2_19_sram[0:1]),
.sram_inv(mux_tree_tapbuf_size2_19_sram_inv[0:1]),
.sram_inv(mux_left_track_31_undriven_sram_inv[0:1]),
.out(chanx_left_out[15])
);
@ -517,7 +509,7 @@ module sb_2__2_
(
.in({ chany_bottom_in[15], left_bottom_grid_pin_37_[0] }),
.sram(mux_tree_tapbuf_size2_20_sram[0:1]),
.sram_inv(mux_tree_tapbuf_size2_20_sram_inv[0:1]),
.sram_inv(mux_left_track_33_undriven_sram_inv[0:1]),
.out(chanx_left_out[16])
);
@ -527,7 +519,7 @@ module sb_2__2_
(
.in({ chany_bottom_in[16], left_bottom_grid_pin_38_[0] }),
.sram(mux_tree_tapbuf_size2_21_sram[0:1]),
.sram_inv(mux_tree_tapbuf_size2_21_sram_inv[0:1]),
.sram_inv(mux_left_track_35_undriven_sram_inv[0:1]),
.out(chanx_left_out[17])
);
@ -537,7 +529,7 @@ module sb_2__2_
(
.in({ chany_bottom_in[17], left_bottom_grid_pin_39_[0] }),
.sram(mux_tree_tapbuf_size2_22_sram[0:1]),
.sram_inv(mux_tree_tapbuf_size2_22_sram_inv[0:1]),
.sram_inv(mux_left_track_37_undriven_sram_inv[0:1]),
.out(chanx_left_out[18])
);
@ -547,7 +539,7 @@ module sb_2__2_
(
.in({ chany_bottom_in[18], left_bottom_grid_pin_40_[0] }),
.sram(mux_tree_tapbuf_size2_23_sram[0:1]),
.sram_inv(mux_tree_tapbuf_size2_23_sram_inv[0:1]),
.sram_inv(mux_left_track_39_undriven_sram_inv[0:1]),
.out(chanx_left_out[19])
);
@ -558,8 +550,7 @@ module sb_2__2_
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size5_mem_1_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size2_mem_0_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size2_0_sram[0:1]),
.mem_outb(mux_tree_tapbuf_size2_0_sram_inv[0:1])
.mem_out(mux_tree_tapbuf_size2_0_sram[0:1])
);
@ -569,8 +560,7 @@ module sb_2__2_
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size2_mem_0_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size2_mem_1_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size2_1_sram[0:1]),
.mem_outb(mux_tree_tapbuf_size2_1_sram_inv[0:1])
.mem_out(mux_tree_tapbuf_size2_1_sram[0:1])
);
@ -580,8 +570,7 @@ module sb_2__2_
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size2_mem_1_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size2_mem_2_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size2_2_sram[0:1]),
.mem_outb(mux_tree_tapbuf_size2_2_sram_inv[0:1])
.mem_out(mux_tree_tapbuf_size2_2_sram[0:1])
);
@ -591,8 +580,7 @@ module sb_2__2_
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size2_mem_2_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size2_mem_3_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size2_3_sram[0:1]),
.mem_outb(mux_tree_tapbuf_size2_3_sram_inv[0:1])
.mem_out(mux_tree_tapbuf_size2_3_sram[0:1])
);
@ -602,8 +590,7 @@ module sb_2__2_
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size2_mem_3_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size2_mem_4_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size2_4_sram[0:1]),
.mem_outb(mux_tree_tapbuf_size2_4_sram_inv[0:1])
.mem_out(mux_tree_tapbuf_size2_4_sram[0:1])
);
@ -613,8 +600,7 @@ module sb_2__2_
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size2_mem_4_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size2_mem_5_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size2_5_sram[0:1]),
.mem_outb(mux_tree_tapbuf_size2_5_sram_inv[0:1])
.mem_out(mux_tree_tapbuf_size2_5_sram[0:1])
);
@ -624,8 +610,7 @@ module sb_2__2_
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size2_mem_5_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size2_mem_6_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size2_6_sram[0:1]),
.mem_outb(mux_tree_tapbuf_size2_6_sram_inv[0:1])
.mem_out(mux_tree_tapbuf_size2_6_sram[0:1])
);
@ -635,8 +620,7 @@ module sb_2__2_
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size2_mem_6_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size2_mem_7_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size2_7_sram[0:1]),
.mem_outb(mux_tree_tapbuf_size2_7_sram_inv[0:1])
.mem_out(mux_tree_tapbuf_size2_7_sram[0:1])
);
@ -646,8 +630,7 @@ module sb_2__2_
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size3_mem_0_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size2_mem_8_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size2_8_sram[0:1]),
.mem_outb(mux_tree_tapbuf_size2_8_sram_inv[0:1])
.mem_out(mux_tree_tapbuf_size2_8_sram[0:1])
);
@ -657,8 +640,7 @@ module sb_2__2_
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size2_mem_8_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size2_mem_9_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size2_9_sram[0:1]),
.mem_outb(mux_tree_tapbuf_size2_9_sram_inv[0:1])
.mem_out(mux_tree_tapbuf_size2_9_sram[0:1])
);
@ -668,8 +650,7 @@ module sb_2__2_
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size3_mem_1_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size2_mem_10_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size2_10_sram[0:1]),
.mem_outb(mux_tree_tapbuf_size2_10_sram_inv[0:1])
.mem_out(mux_tree_tapbuf_size2_10_sram[0:1])
);
@ -679,8 +660,7 @@ module sb_2__2_
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size2_mem_10_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size2_mem_11_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size2_11_sram[0:1]),
.mem_outb(mux_tree_tapbuf_size2_11_sram_inv[0:1])
.mem_out(mux_tree_tapbuf_size2_11_sram[0:1])
);
@ -690,8 +670,7 @@ module sb_2__2_
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size2_mem_11_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size2_mem_12_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size2_12_sram[0:1]),
.mem_outb(mux_tree_tapbuf_size2_12_sram_inv[0:1])
.mem_out(mux_tree_tapbuf_size2_12_sram[0:1])
);
@ -701,8 +680,7 @@ module sb_2__2_
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size2_mem_12_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size2_mem_13_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size2_13_sram[0:1]),
.mem_outb(mux_tree_tapbuf_size2_13_sram_inv[0:1])
.mem_out(mux_tree_tapbuf_size2_13_sram[0:1])
);
@ -712,8 +690,7 @@ module sb_2__2_
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size2_mem_13_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size2_mem_14_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size2_14_sram[0:1]),
.mem_outb(mux_tree_tapbuf_size2_14_sram_inv[0:1])
.mem_out(mux_tree_tapbuf_size2_14_sram[0:1])
);
@ -723,8 +700,7 @@ module sb_2__2_
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size2_mem_14_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size2_mem_15_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size2_15_sram[0:1]),
.mem_outb(mux_tree_tapbuf_size2_15_sram_inv[0:1])
.mem_out(mux_tree_tapbuf_size2_15_sram[0:1])
);
@ -734,8 +710,7 @@ module sb_2__2_
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size2_mem_15_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size2_mem_16_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size2_16_sram[0:1]),
.mem_outb(mux_tree_tapbuf_size2_16_sram_inv[0:1])
.mem_out(mux_tree_tapbuf_size2_16_sram[0:1])
);
@ -745,8 +720,7 @@ module sb_2__2_
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size3_mem_2_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size2_mem_17_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size2_17_sram[0:1]),
.mem_outb(mux_tree_tapbuf_size2_17_sram_inv[0:1])
.mem_out(mux_tree_tapbuf_size2_17_sram[0:1])
);
@ -756,8 +730,7 @@ module sb_2__2_
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size2_mem_17_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size2_mem_18_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size2_18_sram[0:1]),
.mem_outb(mux_tree_tapbuf_size2_18_sram_inv[0:1])
.mem_out(mux_tree_tapbuf_size2_18_sram[0:1])
);
@ -767,8 +740,7 @@ module sb_2__2_
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size2_mem_18_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size2_mem_19_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size2_19_sram[0:1]),
.mem_outb(mux_tree_tapbuf_size2_19_sram_inv[0:1])
.mem_out(mux_tree_tapbuf_size2_19_sram[0:1])
);
@ -778,8 +750,7 @@ module sb_2__2_
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size2_mem_19_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size2_mem_20_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size2_20_sram[0:1]),
.mem_outb(mux_tree_tapbuf_size2_20_sram_inv[0:1])
.mem_out(mux_tree_tapbuf_size2_20_sram[0:1])
);
@ -789,8 +760,7 @@ module sb_2__2_
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size2_mem_20_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size2_mem_21_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size2_21_sram[0:1]),
.mem_outb(mux_tree_tapbuf_size2_21_sram_inv[0:1])
.mem_out(mux_tree_tapbuf_size2_21_sram[0:1])
);
@ -800,8 +770,7 @@ module sb_2__2_
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size2_mem_21_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size2_mem_22_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size2_22_sram[0:1]),
.mem_outb(mux_tree_tapbuf_size2_22_sram_inv[0:1])
.mem_out(mux_tree_tapbuf_size2_22_sram[0:1])
);
@ -811,8 +780,7 @@ module sb_2__2_
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size2_mem_22_ccff_tail[0]),
.ccff_tail(ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size2_23_sram[0:1]),
.mem_outb(mux_tree_tapbuf_size2_23_sram_inv[0:1])
.mem_out(mux_tree_tapbuf_size2_23_sram[0:1])
);
@ -821,7 +789,7 @@ module sb_2__2_
(
.in({ bottom_right_grid_pin_1_[0], bottom_left_grid_pin_49_[0], chanx_left_in[13] }),
.sram(mux_tree_tapbuf_size3_0_sram[0:1]),
.sram_inv(mux_tree_tapbuf_size3_0_sram_inv[0:1]),
.sram_inv(mux_bottom_track_25_undriven_sram_inv[0:1]),
.out(chany_bottom_out[12])
);
@ -831,7 +799,7 @@ module sb_2__2_
(
.in({ chany_bottom_in[3], left_top_grid_pin_1_[0], left_bottom_grid_pin_41_[0] }),
.sram(mux_tree_tapbuf_size3_1_sram[0:1]),
.sram_inv(mux_tree_tapbuf_size3_1_sram_inv[0:1]),
.sram_inv(mux_left_track_9_undriven_sram_inv[0:1]),
.out(chanx_left_out[4])
);
@ -841,7 +809,7 @@ module sb_2__2_
(
.in({ chany_bottom_in[11], left_top_grid_pin_1_[0], left_bottom_grid_pin_41_[0] }),
.sram(mux_tree_tapbuf_size3_2_sram[0:1]),
.sram_inv(mux_tree_tapbuf_size3_2_sram_inv[0:1]),
.sram_inv(mux_left_track_25_undriven_sram_inv[0:1]),
.out(chanx_left_out[12])
);
@ -852,8 +820,7 @@ module sb_2__2_
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size2_mem_7_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size3_mem_0_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size3_0_sram[0:1]),
.mem_outb(mux_tree_tapbuf_size3_0_sram_inv[0:1])
.mem_out(mux_tree_tapbuf_size3_0_sram[0:1])
);
@ -863,8 +830,7 @@ module sb_2__2_
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size5_mem_3_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size3_mem_1_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size3_1_sram[0:1]),
.mem_outb(mux_tree_tapbuf_size3_1_sram_inv[0:1])
.mem_out(mux_tree_tapbuf_size3_1_sram[0:1])
);
@ -874,8 +840,7 @@ module sb_2__2_
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size2_mem_16_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size3_mem_2_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size3_2_sram[0:1]),
.mem_outb(mux_tree_tapbuf_size3_2_sram_inv[0:1])
.mem_out(mux_tree_tapbuf_size3_2_sram[0:1])
);

409
FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/sub_module/memories.v
View File

@ -12,8 +12,7 @@
module mux_tree_tapbuf_size10_mem(prog_clk,
ccff_head,
ccff_tail,
mem_out,
mem_outb);
mem_out);
//
input [0:0] prog_clk;
//
@ -22,8 +21,6 @@ input [0:0] ccff_head;
output [0:0] ccff_tail;
//
output [0:3] mem_out;
//
output [0:3] mem_outb;
//
//
@ -40,29 +37,25 @@ output [0:3] mem_outb;
assign ccff_tail[0] = mem_out[3];
//
sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ (
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ (
.CLK(prog_clk[0]),
.D(ccff_head[0]),
.Q(mem_out[0]),
.Q_N(mem_outb[0]));
.Q(mem_out[0]));
sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ (
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ (
.CLK(prog_clk[0]),
.D(mem_out[0]),
.Q(mem_out[1]),
.Q_N(mem_outb[1]));
.Q(mem_out[1]));
sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ (
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ (
.CLK(prog_clk[0]),
.D(mem_out[1]),
.Q(mem_out[2]),
.Q_N(mem_outb[2]));
.Q(mem_out[2]));
sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ (
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ (
.CLK(prog_clk[0]),
.D(mem_out[2]),
.Q(mem_out[3]),
.Q_N(mem_outb[3]));
.Q(mem_out[3]));
endmodule
//
@ -73,8 +66,7 @@ endmodule
module mux_tree_tapbuf_size8_mem(prog_clk,
ccff_head,
ccff_tail,
mem_out,
mem_outb);
mem_out);
//
input [0:0] prog_clk;
//
@ -83,8 +75,6 @@ input [0:0] ccff_head;
output [0:0] ccff_tail;
//
output [0:3] mem_out;
//
output [0:3] mem_outb;
//
//
@ -101,29 +91,25 @@ output [0:3] mem_outb;
assign ccff_tail[0] = mem_out[3];
//
sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ (
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ (
.CLK(prog_clk[0]),
.D(ccff_head[0]),
.Q(mem_out[0]),
.Q_N(mem_outb[0]));
.Q(mem_out[0]));
sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ (
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ (
.CLK(prog_clk[0]),
.D(mem_out[0]),
.Q(mem_out[1]),
.Q_N(mem_outb[1]));
.Q(mem_out[1]));
sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ (
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ (
.CLK(prog_clk[0]),
.D(mem_out[1]),
.Q(mem_out[2]),
.Q_N(mem_outb[2]));
.Q(mem_out[2]));
sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ (
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ (
.CLK(prog_clk[0]),
.D(mem_out[2]),
.Q(mem_out[3]),
.Q_N(mem_outb[3]));
.Q(mem_out[3]));
endmodule
//
@ -134,8 +120,7 @@ endmodule
module mux_tree_tapbuf_size4_mem(prog_clk,
ccff_head,
ccff_tail,
mem_out,
mem_outb);
mem_out);
//
input [0:0] prog_clk;
//
@ -144,8 +129,6 @@ input [0:0] ccff_head;
output [0:0] ccff_tail;
//
output [0:2] mem_out;
//
output [0:2] mem_outb;
//
//
@ -162,23 +145,20 @@ output [0:2] mem_outb;
assign ccff_tail[0] = mem_out[2];
//
sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ (
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ (
.CLK(prog_clk[0]),
.D(ccff_head[0]),
.Q(mem_out[0]),
.Q_N(mem_outb[0]));
.Q(mem_out[0]));
sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ (
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ (
.CLK(prog_clk[0]),
.D(mem_out[0]),
.Q(mem_out[1]),
.Q_N(mem_outb[1]));
.Q(mem_out[1]));
sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ (
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ (
.CLK(prog_clk[0]),
.D(mem_out[1]),
.Q(mem_out[2]),
.Q_N(mem_outb[2]));
.Q(mem_out[2]));
endmodule
//
@ -189,8 +169,7 @@ endmodule
module mux_tree_tapbuf_size7_mem(prog_clk,
ccff_head,
ccff_tail,
mem_out,
mem_outb);
mem_out);
//
input [0:0] prog_clk;
//
@ -199,8 +178,6 @@ input [0:0] ccff_head;
output [0:0] ccff_tail;
//
output [0:2] mem_out;
//
output [0:2] mem_outb;
//
//
@ -217,23 +194,20 @@ output [0:2] mem_outb;
assign ccff_tail[0] = mem_out[2];
//
sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ (
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ (
.CLK(prog_clk[0]),
.D(ccff_head[0]),
.Q(mem_out[0]),
.Q_N(mem_outb[0]));
.Q(mem_out[0]));
sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ (
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ (
.CLK(prog_clk[0]),
.D(mem_out[0]),
.Q(mem_out[1]),
.Q_N(mem_outb[1]));
.Q(mem_out[1]));
sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ (
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ (
.CLK(prog_clk[0]),
.D(mem_out[1]),
.Q(mem_out[2]),
.Q_N(mem_outb[2]));
.Q(mem_out[2]));
endmodule
//
@ -244,8 +218,7 @@ endmodule
module mux_tree_tapbuf_size11_mem(prog_clk,
ccff_head,
ccff_tail,
mem_out,
mem_outb);
mem_out);
//
input [0:0] prog_clk;
//
@ -254,8 +227,6 @@ input [0:0] ccff_head;
output [0:0] ccff_tail;
//
output [0:3] mem_out;
//
output [0:3] mem_outb;
//
//
@ -272,29 +243,25 @@ output [0:3] mem_outb;
assign ccff_tail[0] = mem_out[3];
//
sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ (
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ (
.CLK(prog_clk[0]),
.D(ccff_head[0]),
.Q(mem_out[0]),
.Q_N(mem_outb[0]));
.Q(mem_out[0]));
sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ (
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ (
.CLK(prog_clk[0]),
.D(mem_out[0]),
.Q(mem_out[1]),
.Q_N(mem_outb[1]));
.Q(mem_out[1]));
sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ (
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ (
.CLK(prog_clk[0]),
.D(mem_out[1]),
.Q(mem_out[2]),
.Q_N(mem_outb[2]));
.Q(mem_out[2]));
sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ (
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ (
.CLK(prog_clk[0]),
.D(mem_out[2]),
.Q(mem_out[3]),
.Q_N(mem_outb[3]));
.Q(mem_out[3]));
endmodule
//
@ -305,8 +272,7 @@ endmodule
module mux_tree_tapbuf_size2_mem(prog_clk,
ccff_head,
ccff_tail,
mem_out,
mem_outb);
mem_out);
//
input [0:0] prog_clk;
//
@ -315,8 +281,6 @@ input [0:0] ccff_head;
output [0:0] ccff_tail;
//
output [0:1] mem_out;
//
output [0:1] mem_outb;
//
//
@ -333,17 +297,15 @@ output [0:1] mem_outb;
assign ccff_tail[0] = mem_out[1];
//
sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ (
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ (
.CLK(prog_clk[0]),
.D(ccff_head[0]),
.Q(mem_out[0]),
.Q_N(mem_outb[0]));
.Q(mem_out[0]));
sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ (
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ (
.CLK(prog_clk[0]),
.D(mem_out[0]),
.Q(mem_out[1]),
.Q_N(mem_outb[1]));
.Q(mem_out[1]));
endmodule
//
@ -354,8 +316,7 @@ endmodule
module mux_tree_tapbuf_size6_mem(prog_clk,
ccff_head,
ccff_tail,
mem_out,
mem_outb);
mem_out);
//
input [0:0] prog_clk;
//
@ -364,8 +325,6 @@ input [0:0] ccff_head;
output [0:0] ccff_tail;
//
output [0:2] mem_out;
//
output [0:2] mem_outb;
//
//
@ -382,23 +341,20 @@ output [0:2] mem_outb;
assign ccff_tail[0] = mem_out[2];
//
sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ (
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ (
.CLK(prog_clk[0]),
.D(ccff_head[0]),
.Q(mem_out[0]),
.Q_N(mem_outb[0]));
.Q(mem_out[0]));
sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ (
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ (
.CLK(prog_clk[0]),
.D(mem_out[0]),
.Q(mem_out[1]),
.Q_N(mem_outb[1]));
.Q(mem_out[1]));
sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ (
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ (
.CLK(prog_clk[0]),
.D(mem_out[1]),
.Q(mem_out[2]),
.Q_N(mem_outb[2]));
.Q(mem_out[2]));
endmodule
//
@ -409,8 +365,7 @@ endmodule
module mux_tree_tapbuf_size5_mem(prog_clk,
ccff_head,
ccff_tail,
mem_out,
mem_outb);
mem_out);
//
input [0:0] prog_clk;
//
@ -419,8 +374,6 @@ input [0:0] ccff_head;
output [0:0] ccff_tail;
//
output [0:2] mem_out;
//
output [0:2] mem_outb;
//
//
@ -437,23 +390,20 @@ output [0:2] mem_outb;
assign ccff_tail[0] = mem_out[2];
//
sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ (
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ (
.CLK(prog_clk[0]),
.D(ccff_head[0]),
.Q(mem_out[0]),
.Q_N(mem_outb[0]));
.Q(mem_out[0]));
sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ (
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ (
.CLK(prog_clk[0]),
.D(mem_out[0]),
.Q(mem_out[1]),
.Q_N(mem_outb[1]));
.Q(mem_out[1]));
sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ (
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ (
.CLK(prog_clk[0]),
.D(mem_out[1]),
.Q(mem_out[2]),
.Q_N(mem_outb[2]));
.Q(mem_out[2]));
endmodule
//
@ -464,8 +414,7 @@ endmodule
module mux_tree_tapbuf_size12_mem(prog_clk,
ccff_head,
ccff_tail,
mem_out,
mem_outb);
mem_out);
//
input [0:0] prog_clk;
//
@ -474,8 +423,6 @@ input [0:0] ccff_head;
output [0:0] ccff_tail;
//
output [0:3] mem_out;
//
output [0:3] mem_outb;
//
//
@ -492,29 +439,25 @@ output [0:3] mem_outb;
assign ccff_tail[0] = mem_out[3];
//
sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ (
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ (
.CLK(prog_clk[0]),
.D(ccff_head[0]),
.Q(mem_out[0]),
.Q_N(mem_outb[0]));
.Q(mem_out[0]));
sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ (
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ (
.CLK(prog_clk[0]),
.D(mem_out[0]),
.Q(mem_out[1]),
.Q_N(mem_outb[1]));
.Q(mem_out[1]));
sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ (
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ (
.CLK(prog_clk[0]),
.D(mem_out[1]),
.Q(mem_out[2]),
.Q_N(mem_outb[2]));
.Q(mem_out[2]));
sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ (
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ (
.CLK(prog_clk[0]),
.D(mem_out[2]),
.Q(mem_out[3]),
.Q_N(mem_outb[3]));
.Q(mem_out[3]));
endmodule
//
@ -525,8 +468,7 @@ endmodule
module mux_tree_tapbuf_size16_mem(prog_clk,
ccff_head,
ccff_tail,
mem_out,
mem_outb);
mem_out);
//
input [0:0] prog_clk;
//
@ -535,8 +477,6 @@ input [0:0] ccff_head;
output [0:0] ccff_tail;
//
output [0:4] mem_out;
//
output [0:4] mem_outb;
//
//
@ -553,35 +493,30 @@ output [0:4] mem_outb;
assign ccff_tail[0] = mem_out[4];
//
sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ (
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ (
.CLK(prog_clk[0]),
.D(ccff_head[0]),
.Q(mem_out[0]),
.Q_N(mem_outb[0]));
.Q(mem_out[0]));
sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ (
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ (
.CLK(prog_clk[0]),
.D(mem_out[0]),
.Q(mem_out[1]),
.Q_N(mem_outb[1]));
.Q(mem_out[1]));
sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ (
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ (
.CLK(prog_clk[0]),
.D(mem_out[1]),
.Q(mem_out[2]),
.Q_N(mem_outb[2]));
.Q(mem_out[2]));
sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ (
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ (
.CLK(prog_clk[0]),
.D(mem_out[2]),
.Q(mem_out[3]),
.Q_N(mem_outb[3]));
.Q(mem_out[3]));
sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_4_ (
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_4_ (
.CLK(prog_clk[0]),
.D(mem_out[3]),
.Q(mem_out[4]),
.Q_N(mem_outb[4]));
.Q(mem_out[4]));
endmodule
//
@ -592,8 +527,7 @@ endmodule
module mux_tree_tapbuf_size3_mem(prog_clk,
ccff_head,
ccff_tail,
mem_out,
mem_outb);
mem_out);
//
input [0:0] prog_clk;
//
@ -602,8 +536,6 @@ input [0:0] ccff_head;
output [0:0] ccff_tail;
//
output [0:1] mem_out;
//
output [0:1] mem_outb;
//
//
@ -620,17 +552,15 @@ output [0:1] mem_outb;
assign ccff_tail[0] = mem_out[1];
//
sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ (
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ (
.CLK(prog_clk[0]),
.D(ccff_head[0]),
.Q(mem_out[0]),
.Q_N(mem_outb[0]));
.Q(mem_out[0]));
sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ (
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ (
.CLK(prog_clk[0]),
.D(mem_out[0]),
.Q(mem_out[1]),
.Q_N(mem_outb[1]));
.Q(mem_out[1]));
endmodule
//
@ -641,8 +571,7 @@ endmodule
module mux_tree_tapbuf_size9_mem(prog_clk,
ccff_head,
ccff_tail,
mem_out,
mem_outb);
mem_out);
//
input [0:0] prog_clk;
//
@ -651,8 +580,6 @@ input [0:0] ccff_head;
output [0:0] ccff_tail;
//
output [0:3] mem_out;
//
output [0:3] mem_outb;
//
//
@ -669,29 +596,25 @@ output [0:3] mem_outb;
assign ccff_tail[0] = mem_out[3];
//
sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ (
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ (
.CLK(prog_clk[0]),
.D(ccff_head[0]),
.Q(mem_out[0]),
.Q_N(mem_outb[0]));
.Q(mem_out[0]));
sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ (
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ (
.CLK(prog_clk[0]),
.D(mem_out[0]),
.Q(mem_out[1]),
.Q_N(mem_outb[1]));
.Q(mem_out[1]));
sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ (
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ (
.CLK(prog_clk[0]),
.D(mem_out[1]),
.Q(mem_out[2]),
.Q_N(mem_outb[2]));
.Q(mem_out[2]));
sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ (
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ (
.CLK(prog_clk[0]),
.D(mem_out[2]),
.Q(mem_out[3]),
.Q_N(mem_outb[3]));
.Q(mem_out[3]));
endmodule
//
@ -702,8 +625,7 @@ endmodule
module mux_tree_tapbuf_size14_mem(prog_clk,
ccff_head,
ccff_tail,
mem_out,
mem_outb);
mem_out);
//
input [0:0] prog_clk;
//
@ -712,8 +634,6 @@ input [0:0] ccff_head;
output [0:0] ccff_tail;
//
output [0:3] mem_out;
//
output [0:3] mem_outb;
//
//
@ -730,29 +650,25 @@ output [0:3] mem_outb;
assign ccff_tail[0] = mem_out[3];
//
sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ (
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ (
.CLK(prog_clk[0]),
.D(ccff_head[0]),
.Q(mem_out[0]),
.Q_N(mem_outb[0]));
.Q(mem_out[0]));
sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ (
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ (
.CLK(prog_clk[0]),
.D(mem_out[0]),
.Q(mem_out[1]),
.Q_N(mem_outb[1]));
.Q(mem_out[1]));
sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ (
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ (
.CLK(prog_clk[0]),
.D(mem_out[1]),
.Q(mem_out[2]),
.Q_N(mem_outb[2]));
.Q(mem_out[2]));
sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ (
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ (
.CLK(prog_clk[0]),
.D(mem_out[2]),
.Q(mem_out[3]),
.Q_N(mem_outb[3]));
.Q(mem_out[3]));
endmodule
//
@ -763,8 +679,7 @@ endmodule
module mux_tree_size2_mem(prog_clk,
ccff_head,
ccff_tail,
mem_out,
mem_outb);
mem_out);
//
input [0:0] prog_clk;
//
@ -773,8 +688,6 @@ input [0:0] ccff_head;
output [0:0] ccff_tail;
//
output [0:1] mem_out;
//
output [0:1] mem_outb;
//
//
@ -791,17 +704,15 @@ output [0:1] mem_outb;
assign ccff_tail[0] = mem_out[1];
//
sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ (
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ (
.CLK(prog_clk[0]),
.D(ccff_head[0]),
.Q(mem_out[0]),
.Q_N(mem_outb[0]));
.Q(mem_out[0]));
sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ (
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ (
.CLK(prog_clk[0]),
.D(mem_out[0]),
.Q(mem_out[1]),
.Q_N(mem_outb[1]));
.Q(mem_out[1]));
endmodule
//
@ -809,11 +720,10 @@ endmodule
//
module frac_lut4_sky130_fd_sc_hd__dfxbp_1_mem(prog_clk,
module frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem(prog_clk,
ccff_head,
ccff_tail,
mem_out,
mem_outb);
mem_out);
//
input [0:0] prog_clk;
//
@ -822,8 +732,6 @@ input [0:0] ccff_head;
output [0:0] ccff_tail;
//
output [0:16] mem_out;
//
output [0:16] mem_outb;
//
//
@ -840,107 +748,90 @@ output [0:16] mem_outb;
assign ccff_tail[0] = mem_out[16];
//
sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ (
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ (
.CLK(prog_clk[0]),
.D(ccff_head[0]),
.Q(mem_out[0]),
.Q_N(mem_outb[0]));
.Q(mem_out[0]));
sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ (
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ (
.CLK(prog_clk[0]),
.D(mem_out[0]),
.Q(mem_out[1]),
.Q_N(mem_outb[1]));
.Q(mem_out[1]));
sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ (
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ (
.CLK(prog_clk[0]),
.D(mem_out[1]),
.Q(mem_out[2]),
.Q_N(mem_outb[2]));
.Q(mem_out[2]));
sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ (
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ (
.CLK(prog_clk[0]),
.D(mem_out[2]),
.Q(mem_out[3]),
.Q_N(mem_outb[3]));
.Q(mem_out[3]));
sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_4_ (
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_4_ (
.CLK(prog_clk[0]),
.D(mem_out[3]),
.Q(mem_out[4]),
.Q_N(mem_outb[4]));
.Q(mem_out[4]));
sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_5_ (
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_5_ (
.CLK(prog_clk[0]),
.D(mem_out[4]),
.Q(mem_out[5]),
.Q_N(mem_outb[5]));
.Q(mem_out[5]));
sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_6_ (
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_6_ (
.CLK(prog_clk[0]),
.D(mem_out[5]),
.Q(mem_out[6]),
.Q_N(mem_outb[6]));
.Q(mem_out[6]));
sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_7_ (
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_7_ (
.CLK(prog_clk[0]),
.D(mem_out[6]),
.Q(mem_out[7]),
.Q_N(mem_outb[7]));
.Q(mem_out[7]));
sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_8_ (
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_8_ (
.CLK(prog_clk[0]),
.D(mem_out[7]),
.Q(mem_out[8]),
.Q_N(mem_outb[8]));
.Q(mem_out[8]));
sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_9_ (
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_9_ (
.CLK(prog_clk[0]),
.D(mem_out[8]),
.Q(mem_out[9]),
.Q_N(mem_outb[9]));
.Q(mem_out[9]));
sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_10_ (
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_10_ (
.CLK(prog_clk[0]),
.D(mem_out[9]),
.Q(mem_out[10]),
.Q_N(mem_outb[10]));
.Q(mem_out[10]));
sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_11_ (
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_11_ (
.CLK(prog_clk[0]),
.D(mem_out[10]),
.Q(mem_out[11]),
.Q_N(mem_outb[11]));
.Q(mem_out[11]));
sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_12_ (
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_12_ (
.CLK(prog_clk[0]),
.D(mem_out[11]),
.Q(mem_out[12]),
.Q_N(mem_outb[12]));
.Q(mem_out[12]));
sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_13_ (
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_13_ (
.CLK(prog_clk[0]),
.D(mem_out[12]),
.Q(mem_out[13]),
.Q_N(mem_outb[13]));
.Q(mem_out[13]));
sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_14_ (
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_14_ (
.CLK(prog_clk[0]),
.D(mem_out[13]),
.Q(mem_out[14]),
.Q_N(mem_outb[14]));
.Q(mem_out[14]));
sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_15_ (
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_15_ (
.CLK(prog_clk[0]),
.D(mem_out[14]),
.Q(mem_out[15]),
.Q_N(mem_outb[15]));
.Q(mem_out[15]));
sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_16_ (
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_16_ (
.CLK(prog_clk[0]),
.D(mem_out[15]),
.Q(mem_out[16]),
.Q_N(mem_outb[16]));
.Q(mem_out[16]));
endmodule
//
@ -948,11 +839,10 @@ endmodule
//
module EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem(prog_clk,
module EMBEDDED_IO_sky130_fd_sc_hd__dfxtp_1_mem(prog_clk,
ccff_head,
ccff_tail,
mem_out,
mem_outb);
mem_out);
//
input [0:0] prog_clk;
//
@ -961,8 +851,6 @@ input [0:0] ccff_head;
output [0:0] ccff_tail;
//
output [0:0] mem_out;
//
output [0:0] mem_outb;
//
//
@ -979,11 +867,10 @@ output [0:0] mem_outb;
assign ccff_tail[0] = mem_out[0];
//
sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ (
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ (
.CLK(prog_clk[0]),
.D(ccff_head[0]),
.Q(mem_out[0]),
.Q_N(mem_outb[0]));
.Q(mem_out[0]));
endmodule
//

6
FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/top_autocheck_top_tb.v
View File

@ -813,10 +813,10 @@ initial
prog_cycle_task(1'b0);
prog_cycle_task(1'b0);
prog_cycle_task(1'b0);
prog_cycle_task(1'b0);
prog_cycle_task(1'b0);
prog_cycle_task(1'b0);
prog_cycle_task(1'b1);
prog_cycle_task(1'b0);
prog_cycle_task(1'b0);
prog_cycle_task(1'b0);
prog_cycle_task(1'b1);
prog_cycle_task(1'b0);
prog_cycle_task(1'b0);

1368
FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/top_top_formal_verification.v
View File

File diff suppressed because it is too large Load Diff

2
FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/TESTBENCH/top/fabric_bitstream.bit
View File

@ -1 +1 @@
000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000001100000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100010001000001000000000000000000000000000000000000000000000000001111000001110000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011111100100000000000000000000000011000000000000000000000000000000000000000000000000000000000000000000000000110111111000001100001000000000001100000000000000000000
000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000001100000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000110000001000001000000000000000000000000000000000000000000000000001111000001110000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011111100100000000000000000000000011000000000000000000000000000000000000000000000000000000000000000000000000110111111000001100001000000000001100000000000000000000

1126
FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/TESTBENCH/top/fabric_bitstream.xml
View File

File diff suppressed because it is too large Load Diff

206
FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/TESTBENCH/top/fabric_indepenent_bitstream.xml
View File

@ -2,7 +2,7 @@
- Architecture independent bitstream
- Author: Xifan TANG
- Organization: University of Utah
- Date: Sun Nov 8 17:53:56 2020
- Date: Mon Nov 9 18:01:58 2020
-->
<bitstream_block name="fpga_top" hierarchy_level="0">
@ -12,7 +12,7 @@
<bitstream_block name="logical_tile_clb_mode_default__fle_mode_physical__fabric_0" hierarchy_level="4">
<bitstream_block name="logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0" hierarchy_level="5">
<bitstream_block name="logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0" hierarchy_level="6">
<bitstream_block name="frac_lut4_sky130_fd_sc_hd__dfxbp_1_mem" hierarchy_level="7">
<bitstream_block name="frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem" hierarchy_level="7">
<hierarchy>
<instance level="0" name="fpga_top"/>
<instance level="1" name="grid_clb_1__1_"/>
@ -21,7 +21,7 @@
<instance level="4" name="logical_tile_clb_mode_default__fle_mode_physical__fabric_0"/>
<instance level="5" name="logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0"/>
<instance level="6" name="logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0"/>
<instance level="7" name="frac_lut4_sky130_fd_sc_hd__dfxbp_1_mem"/>
<instance level="7" name="frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem"/>
</hierarchy>
<bitstream>
<bit memory_port="mem_out[0]" value="0"/>
@ -120,7 +120,7 @@
<bitstream_block name="logical_tile_clb_mode_default__fle_mode_physical__fabric_0" hierarchy_level="4">
<bitstream_block name="logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0" hierarchy_level="5">
<bitstream_block name="logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0" hierarchy_level="6">
<bitstream_block name="frac_lut4_sky130_fd_sc_hd__dfxbp_1_mem" hierarchy_level="7">
<bitstream_block name="frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem" hierarchy_level="7">
<hierarchy>
<instance level="0" name="fpga_top"/>
<instance level="1" name="grid_clb_1__1_"/>
@ -129,7 +129,7 @@
<instance level="4" name="logical_tile_clb_mode_default__fle_mode_physical__fabric_0"/>
<instance level="5" name="logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0"/>
<instance level="6" name="logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0"/>
<instance level="7" name="frac_lut4_sky130_fd_sc_hd__dfxbp_1_mem"/>
<instance level="7" name="frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem"/>
</hierarchy>
<bitstream>
<bit memory_port="mem_out[0]" value="0"/>
@ -228,7 +228,7 @@
<bitstream_block name="logical_tile_clb_mode_default__fle_mode_physical__fabric_0" hierarchy_level="4">
<bitstream_block name="logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0" hierarchy_level="5">
<bitstream_block name="logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0" hierarchy_level="6">
<bitstream_block name="frac_lut4_sky130_fd_sc_hd__dfxbp_1_mem" hierarchy_level="7">
<bitstream_block name="frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem" hierarchy_level="7">
<hierarchy>
<instance level="0" name="fpga_top"/>
<instance level="1" name="grid_clb_1__1_"/>
@ -237,7 +237,7 @@
<instance level="4" name="logical_tile_clb_mode_default__fle_mode_physical__fabric_0"/>
<instance level="5" name="logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0"/>
<instance level="6" name="logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0"/>
<instance level="7" name="frac_lut4_sky130_fd_sc_hd__dfxbp_1_mem"/>
<instance level="7" name="frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem"/>
</hierarchy>
<bitstream>
<bit memory_port="mem_out[0]" value="0"/>
@ -336,7 +336,7 @@
<bitstream_block name="logical_tile_clb_mode_default__fle_mode_physical__fabric_0" hierarchy_level="4">
<bitstream_block name="logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0" hierarchy_level="5">
<bitstream_block name="logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0" hierarchy_level="6">
<bitstream_block name="frac_lut4_sky130_fd_sc_hd__dfxbp_1_mem" hierarchy_level="7">
<bitstream_block name="frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem" hierarchy_level="7">
<hierarchy>
<instance level="0" name="fpga_top"/>
<instance level="1" name="grid_clb_1__1_"/>
@ -345,7 +345,7 @@
<instance level="4" name="logical_tile_clb_mode_default__fle_mode_physical__fabric_0"/>
<instance level="5" name="logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0"/>
<instance level="6" name="logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0"/>
<instance level="7" name="frac_lut4_sky130_fd_sc_hd__dfxbp_1_mem"/>
<instance level="7" name="frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem"/>
</hierarchy>
<bitstream>
<bit memory_port="mem_out[0]" value="0"/>
@ -444,7 +444,7 @@
<bitstream_block name="logical_tile_clb_mode_default__fle_mode_physical__fabric_0" hierarchy_level="4">
<bitstream_block name="logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0" hierarchy_level="5">
<bitstream_block name="logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0" hierarchy_level="6">
<bitstream_block name="frac_lut4_sky130_fd_sc_hd__dfxbp_1_mem" hierarchy_level="7">
<bitstream_block name="frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem" hierarchy_level="7">
<hierarchy>
<instance level="0" name="fpga_top"/>
<instance level="1" name="grid_clb_1__1_"/>
@ -453,7 +453,7 @@
<instance level="4" name="logical_tile_clb_mode_default__fle_mode_physical__fabric_0"/>
<instance level="5" name="logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0"/>
<instance level="6" name="logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0"/>
<instance level="7" name="frac_lut4_sky130_fd_sc_hd__dfxbp_1_mem"/>
<instance level="7" name="frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem"/>
</hierarchy>
<bitstream>
<bit memory_port="mem_out[0]" value="0"/>
@ -552,7 +552,7 @@
<bitstream_block name="logical_tile_clb_mode_default__fle_mode_physical__fabric_0" hierarchy_level="4">
<bitstream_block name="logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0" hierarchy_level="5">
<bitstream_block name="logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0" hierarchy_level="6">
<bitstream_block name="frac_lut4_sky130_fd_sc_hd__dfxbp_1_mem" hierarchy_level="7">
<bitstream_block name="frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem" hierarchy_level="7">
<hierarchy>
<instance level="0" name="fpga_top"/>
<instance level="1" name="grid_clb_1__1_"/>
@ -561,7 +561,7 @@
<instance level="4" name="logical_tile_clb_mode_default__fle_mode_physical__fabric_0"/>
<instance level="5" name="logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0"/>
<instance level="6" name="logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0"/>
<instance level="7" name="frac_lut4_sky130_fd_sc_hd__dfxbp_1_mem"/>
<instance level="7" name="frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem"/>
</hierarchy>
<bitstream>
<bit memory_port="mem_out[0]" value="0"/>
@ -660,7 +660,7 @@
<bitstream_block name="logical_tile_clb_mode_default__fle_mode_physical__fabric_0" hierarchy_level="4">
<bitstream_block name="logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0" hierarchy_level="5">
<bitstream_block name="logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0" hierarchy_level="6">
<bitstream_block name="frac_lut4_sky130_fd_sc_hd__dfxbp_1_mem" hierarchy_level="7">
<bitstream_block name="frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem" hierarchy_level="7">
<hierarchy>
<instance level="0" name="fpga_top"/>
<instance level="1" name="grid_clb_1__1_"/>
@ -669,7 +669,7 @@
<instance level="4" name="logical_tile_clb_mode_default__fle_mode_physical__fabric_0"/>
<instance level="5" name="logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0"/>
<instance level="6" name="logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0"/>
<instance level="7" name="frac_lut4_sky130_fd_sc_hd__dfxbp_1_mem"/>
<instance level="7" name="frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem"/>
</hierarchy>
<bitstream>
<bit memory_port="mem_out[0]" value="0"/>
@ -768,7 +768,7 @@
<bitstream_block name="logical_tile_clb_mode_default__fle_mode_physical__fabric_0" hierarchy_level="4">
<bitstream_block name="logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0" hierarchy_level="5">
<bitstream_block name="logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0" hierarchy_level="6">
<bitstream_block name="frac_lut4_sky130_fd_sc_hd__dfxbp_1_mem" hierarchy_level="7">
<bitstream_block name="frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem" hierarchy_level="7">
<hierarchy>
<instance level="0" name="fpga_top"/>
<instance level="1" name="grid_clb_1__1_"/>
@ -777,7 +777,7 @@
<instance level="4" name="logical_tile_clb_mode_default__fle_mode_physical__fabric_0"/>
<instance level="5" name="logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0"/>
<instance level="6" name="logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0"/>
<instance level="7" name="frac_lut4_sky130_fd_sc_hd__dfxbp_1_mem"/>
<instance level="7" name="frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem"/>
</hierarchy>
<bitstream>
<bit memory_port="mem_out[0]" value="0"/>
@ -789,10 +789,10 @@
<bit memory_port="mem_out[6]" value="0"/>
<bit memory_port="mem_out[7]" value="0"/>
<bit memory_port="mem_out[8]" value="1"/>
<bit memory_port="mem_out[9]" value="0"/>
<bit memory_port="mem_out[9]" value="1"/>
<bit memory_port="mem_out[10]" value="0"/>
<bit memory_port="mem_out[11]" value="0"/>
<bit memory_port="mem_out[12]" value="1"/>
<bit memory_port="mem_out[12]" value="0"/>
<bit memory_port="mem_out[13]" value="0"/>
<bit memory_port="mem_out[14]" value="0"/>
<bit memory_port="mem_out[15]" value="0"/>
@ -884,7 +884,7 @@
<bitstream_block name="logical_tile_clb_mode_default__fle_mode_physical__fabric_0" hierarchy_level="4">
<bitstream_block name="logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0" hierarchy_level="5">
<bitstream_block name="logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0" hierarchy_level="6">
<bitstream_block name="frac_lut4_sky130_fd_sc_hd__dfxbp_1_mem" hierarchy_level="7">
<bitstream_block name="frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem" hierarchy_level="7">
<hierarchy>
<instance level="0" name="fpga_top"/>
<instance level="1" name="grid_clb_1__2_"/>
@ -893,7 +893,7 @@
<instance level="4" name="logical_tile_clb_mode_default__fle_mode_physical__fabric_0"/>
<instance level="5" name="logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0"/>
<instance level="6" name="logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0"/>
<instance level="7" name="frac_lut4_sky130_fd_sc_hd__dfxbp_1_mem"/>
<instance level="7" name="frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem"/>
</hierarchy>
<bitstream>
<bit memory_port="mem_out[0]" value="0"/>
@ -992,7 +992,7 @@
<bitstream_block name="logical_tile_clb_mode_default__fle_mode_physical__fabric_0" hierarchy_level="4">
<bitstream_block name="logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0" hierarchy_level="5">
<bitstream_block name="logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0" hierarchy_level="6">
<bitstream_block name="frac_lut4_sky130_fd_sc_hd__dfxbp_1_mem" hierarchy_level="7">
<bitstream_block name="frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem" hierarchy_level="7">
<hierarchy>
<instance level="0" name="fpga_top"/>
<instance level="1" name="grid_clb_1__2_"/>
@ -1001,7 +1001,7 @@
<instance level="4" name="logical_tile_clb_mode_default__fle_mode_physical__fabric_0"/>
<instance level="5" name="logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0"/>
<instance level="6" name="logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0"/>
<instance level="7" name="frac_lut4_sky130_fd_sc_hd__dfxbp_1_mem"/>
<instance level="7" name="frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem"/>
</hierarchy>
<bitstream>
<bit memory_port="mem_out[0]" value="0"/>
@ -1100,7 +1100,7 @@
<bitstream_block name="logical_tile_clb_mode_default__fle_mode_physical__fabric_0" hierarchy_level="4">
<bitstream_block name="logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0" hierarchy_level="5">
<bitstream_block name="logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0" hierarchy_level="6">
<bitstream_block name="frac_lut4_sky130_fd_sc_hd__dfxbp_1_mem" hierarchy_level="7">
<bitstream_block name="frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem" hierarchy_level="7">
<hierarchy>
<instance level="0" name="fpga_top"/>
<instance level="1" name="grid_clb_1__2_"/>
@ -1109,7 +1109,7 @@
<instance level="4" name="logical_tile_clb_mode_default__fle_mode_physical__fabric_0"/>
<instance level="5" name="logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0"/>
<instance level="6" name="logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0"/>
<instance level="7" name="frac_lut4_sky130_fd_sc_hd__dfxbp_1_mem"/>
<instance level="7" name="frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem"/>
</hierarchy>
<bitstream>
<bit memory_port="mem_out[0]" value="0"/>
@ -1208,7 +1208,7 @@
<bitstream_block name="logical_tile_clb_mode_default__fle_mode_physical__fabric_0" hierarchy_level="4">
<bitstream_block name="logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0" hierarchy_level="5">
<bitstream_block name="logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0" hierarchy_level="6">
<bitstream_block name="frac_lut4_sky130_fd_sc_hd__dfxbp_1_mem" hierarchy_level="7">
<bitstream_block name="frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem" hierarchy_level="7">
<hierarchy>
<instance level="0" name="fpga_top"/>
<instance level="1" name="grid_clb_1__2_"/>
@ -1217,7 +1217,7 @@
<instance level="4" name="logical_tile_clb_mode_default__fle_mode_physical__fabric_0"/>
<instance level="5" name="logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0"/>
<instance level="6" name="logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0"/>
<instance level="7" name="frac_lut4_sky130_fd_sc_hd__dfxbp_1_mem"/>
<instance level="7" name="frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem"/>
</hierarchy>
<bitstream>
<bit memory_port="mem_out[0]" value="0"/>
@ -1316,7 +1316,7 @@
<bitstream_block name="logical_tile_clb_mode_default__fle_mode_physical__fabric_0" hierarchy_level="4">
<bitstream_block name="logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0" hierarchy_level="5">
<bitstream_block name="logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0" hierarchy_level="6">
<bitstream_block name="frac_lut4_sky130_fd_sc_hd__dfxbp_1_mem" hierarchy_level="7">
<bitstream_block name="frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem" hierarchy_level="7">
<hierarchy>
<instance level="0" name="fpga_top"/>
<instance level="1" name="grid_clb_1__2_"/>
@ -1325,7 +1325,7 @@
<instance level="4" name="logical_tile_clb_mode_default__fle_mode_physical__fabric_0"/>
<instance level="5" name="logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0"/>
<instance level="6" name="logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0"/>
<instance level="7" name="frac_lut4_sky130_fd_sc_hd__dfxbp_1_mem"/>
<instance level="7" name="frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem"/>
</hierarchy>
<bitstream>
<bit memory_port="mem_out[0]" value="0"/>
@ -1424,7 +1424,7 @@
<bitstream_block name="logical_tile_clb_mode_default__fle_mode_physical__fabric_0" hierarchy_level="4">
<bitstream_block name="logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0" hierarchy_level="5">
<bitstream_block name="logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0" hierarchy_level="6">
<bitstream_block name="frac_lut4_sky130_fd_sc_hd__dfxbp_1_mem" hierarchy_level="7">
<bitstream_block name="frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem" hierarchy_level="7">
<hierarchy>
<instance level="0" name="fpga_top"/>
<instance level="1" name="grid_clb_1__2_"/>
@ -1433,7 +1433,7 @@
<instance level="4" name="logical_tile_clb_mode_default__fle_mode_physical__fabric_0"/>
<instance level="5" name="logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0"/>
<instance level="6" name="logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0"/>
<instance level="7" name="frac_lut4_sky130_fd_sc_hd__dfxbp_1_mem"/>
<instance level="7" name="frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem"/>
</hierarchy>
<bitstream>
<bit memory_port="mem_out[0]" value="0"/>
@ -1532,7 +1532,7 @@
<bitstream_block name="logical_tile_clb_mode_default__fle_mode_physical__fabric_0" hierarchy_level="4">
<bitstream_block name="logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0" hierarchy_level="5">
<bitstream_block name="logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0" hierarchy_level="6">
<bitstream_block name="frac_lut4_sky130_fd_sc_hd__dfxbp_1_mem" hierarchy_level="7">
<bitstream_block name="frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem" hierarchy_level="7">
<hierarchy>
<instance level="0" name="fpga_top"/>
<instance level="1" name="grid_clb_1__2_"/>
@ -1541,7 +1541,7 @@
<instance level="4" name="logical_tile_clb_mode_default__fle_mode_physical__fabric_0"/>
<instance level="5" name="logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0"/>
<instance level="6" name="logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0"/>
<instance level="7" name="frac_lut4_sky130_fd_sc_hd__dfxbp_1_mem"/>
<instance level="7" name="frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem"/>
</hierarchy>
<bitstream>
<bit memory_port="mem_out[0]" value="0"/>
@ -1640,7 +1640,7 @@
<bitstream_block name="logical_tile_clb_mode_default__fle_mode_physical__fabric_0" hierarchy_level="4">
<bitstream_block name="logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0" hierarchy_level="5">
<bitstream_block name="logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0" hierarchy_level="6">
<bitstream_block name="frac_lut4_sky130_fd_sc_hd__dfxbp_1_mem" hierarchy_level="7">
<bitstream_block name="frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem" hierarchy_level="7">
<hierarchy>
<instance level="0" name="fpga_top"/>
<instance level="1" name="grid_clb_1__2_"/>
@ -1649,7 +1649,7 @@
<instance level="4" name="logical_tile_clb_mode_default__fle_mode_physical__fabric_0"/>
<instance level="5" name="logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0"/>
<instance level="6" name="logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0"/>
<instance level="7" name="frac_lut4_sky130_fd_sc_hd__dfxbp_1_mem"/>
<instance level="7" name="frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem"/>
</hierarchy>
<bitstream>
<bit memory_port="mem_out[0]" value="0"/>
@ -1752,7 +1752,7 @@
<bitstream_block name="logical_tile_clb_mode_default__fle_mode_physical__fabric_0" hierarchy_level="4">
<bitstream_block name="logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0" hierarchy_level="5">
<bitstream_block name="logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0" hierarchy_level="6">
<bitstream_block name="frac_lut4_sky130_fd_sc_hd__dfxbp_1_mem" hierarchy_level="7">
<bitstream_block name="frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem" hierarchy_level="7">
<hierarchy>
<instance level="0" name="fpga_top"/>
<instance level="1" name="grid_clb_2__1_"/>
@ -1761,7 +1761,7 @@
<instance level="4" name="logical_tile_clb_mode_default__fle_mode_physical__fabric_0"/>
<instance level="5" name="logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0"/>
<instance level="6" name="logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0"/>
<instance level="7" name="frac_lut4_sky130_fd_sc_hd__dfxbp_1_mem"/>
<instance level="7" name="frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem"/>
</hierarchy>
<bitstream>
<bit memory_port="mem_out[0]" value="0"/>
@ -1860,7 +1860,7 @@
<bitstream_block name="logical_tile_clb_mode_default__fle_mode_physical__fabric_0" hierarchy_level="4">
<bitstream_block name="logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0" hierarchy_level="5">
<bitstream_block name="logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0" hierarchy_level="6">
<bitstream_block name="frac_lut4_sky130_fd_sc_hd__dfxbp_1_mem" hierarchy_level="7">
<bitstream_block name="frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem" hierarchy_level="7">
<hierarchy>
<instance level="0" name="fpga_top"/>
<instance level="1" name="grid_clb_2__1_"/>
@ -1869,7 +1869,7 @@
<instance level="4" name="logical_tile_clb_mode_default__fle_mode_physical__fabric_0"/>
<instance level="5" name="logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0"/>
<instance level="6" name="logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0"/>
<instance level="7" name="frac_lut4_sky130_fd_sc_hd__dfxbp_1_mem"/>
<instance level="7" name="frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem"/>
</hierarchy>
<bitstream>
<bit memory_port="mem_out[0]" value="0"/>
@ -1968,7 +1968,7 @@
<bitstream_block name="logical_tile_clb_mode_default__fle_mode_physical__fabric_0" hierarchy_level="4">
<bitstream_block name="logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0" hierarchy_level="5">
<bitstream_block name="logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0" hierarchy_level="6">
<bitstream_block name="frac_lut4_sky130_fd_sc_hd__dfxbp_1_mem" hierarchy_level="7">
<bitstream_block name="frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem" hierarchy_level="7">
<hierarchy>
<instance level="0" name="fpga_top"/>
<instance level="1" name="grid_clb_2__1_"/>
@ -1977,7 +1977,7 @@
<instance level="4" name="logical_tile_clb_mode_default__fle_mode_physical__fabric_0"/>
<instance level="5" name="logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0"/>
<instance level="6" name="logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0"/>
<instance level="7" name="frac_lut4_sky130_fd_sc_hd__dfxbp_1_mem"/>
<instance level="7" name="frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem"/>
</hierarchy>
<bitstream>
<bit memory_port="mem_out[0]" value="0"/>
@ -2076,7 +2076,7 @@
<bitstream_block name="logical_tile_clb_mode_default__fle_mode_physical__fabric_0" hierarchy_level="4">
<bitstream_block name="logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0" hierarchy_level="5">
<bitstream_block name="logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0" hierarchy_level="6">
<bitstream_block name="frac_lut4_sky130_fd_sc_hd__dfxbp_1_mem" hierarchy_level="7">
<bitstream_block name="frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem" hierarchy_level="7">
<hierarchy>
<instance level="0" name="fpga_top"/>
<instance level="1" name="grid_clb_2__1_"/>
@ -2085,7 +2085,7 @@
<instance level="4" name="logical_tile_clb_mode_default__fle_mode_physical__fabric_0"/>
<instance level="5" name="logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0"/>
<instance level="6" name="logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0"/>
<instance level="7" name="frac_lut4_sky130_fd_sc_hd__dfxbp_1_mem"/>
<instance level="7" name="frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem"/>
</hierarchy>
<bitstream>
<bit memory_port="mem_out[0]" value="0"/>
@ -2184,7 +2184,7 @@
<bitstream_block name="logical_tile_clb_mode_default__fle_mode_physical__fabric_0" hierarchy_level="4">
<bitstream_block name="logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0" hierarchy_level="5">
<bitstream_block name="logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0" hierarchy_level="6">
<bitstream_block name="frac_lut4_sky130_fd_sc_hd__dfxbp_1_mem" hierarchy_level="7">
<bitstream_block name="frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem" hierarchy_level="7">
<hierarchy>
<instance level="0" name="fpga_top"/>
<instance level="1" name="grid_clb_2__1_"/>
@ -2193,7 +2193,7 @@
<instance level="4" name="logical_tile_clb_mode_default__fle_mode_physical__fabric_0"/>
<instance level="5" name="logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0"/>
<instance level="6" name="logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0"/>
<instance level="7" name="frac_lut4_sky130_fd_sc_hd__dfxbp_1_mem"/>
<instance level="7" name="frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem"/>
</hierarchy>
<bitstream>
<bit memory_port="mem_out[0]" value="0"/>
@ -2292,7 +2292,7 @@
<bitstream_block name="logical_tile_clb_mode_default__fle_mode_physical__fabric_0" hierarchy_level="4">
<bitstream_block name="logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0" hierarchy_level="5">
<bitstream_block name="logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0" hierarchy_level="6">
<bitstream_block name="frac_lut4_sky130_fd_sc_hd__dfxbp_1_mem" hierarchy_level="7">
<bitstream_block name="frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem" hierarchy_level="7">
<hierarchy>
<instance level="0" name="fpga_top"/>
<instance level="1" name="grid_clb_2__1_"/>
@ -2301,7 +2301,7 @@
<instance level="4" name="logical_tile_clb_mode_default__fle_mode_physical__fabric_0"/>
<instance level="5" name="logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0"/>
<instance level="6" name="logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0"/>
<instance level="7" name="frac_lut4_sky130_fd_sc_hd__dfxbp_1_mem"/>
<instance level="7" name="frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem"/>
</hierarchy>
<bitstream>
<bit memory_port="mem_out[0]" value="0"/>
@ -2400,7 +2400,7 @@
<bitstream_block name="logical_tile_clb_mode_default__fle_mode_physical__fabric_0" hierarchy_level="4">
<bitstream_block name="logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0" hierarchy_level="5">
<bitstream_block name="logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0" hierarchy_level="6">
<bitstream_block name="frac_lut4_sky130_fd_sc_hd__dfxbp_1_mem" hierarchy_level="7">
<bitstream_block name="frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem" hierarchy_level="7">
<hierarchy>
<instance level="0" name="fpga_top"/>
<instance level="1" name="grid_clb_2__1_"/>
@ -2409,7 +2409,7 @@
<instance level="4" name="logical_tile_clb_mode_default__fle_mode_physical__fabric_0"/>
<instance level="5" name="logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0"/>
<instance level="6" name="logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0"/>
<instance level="7" name="frac_lut4_sky130_fd_sc_hd__dfxbp_1_mem"/>
<instance level="7" name="frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem"/>
</hierarchy>
<bitstream>
<bit memory_port="mem_out[0]" value="0"/>
@ -2508,7 +2508,7 @@
<bitstream_block name="logical_tile_clb_mode_default__fle_mode_physical__fabric_0" hierarchy_level="4">
<bitstream_block name="logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0" hierarchy_level="5">
<bitstream_block name="logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0" hierarchy_level="6">
<bitstream_block name="frac_lut4_sky130_fd_sc_hd__dfxbp_1_mem" hierarchy_level="7">
<bitstream_block name="frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem" hierarchy_level="7">
<hierarchy>
<instance level="0" name="fpga_top"/>
<instance level="1" name="grid_clb_2__1_"/>
@ -2517,7 +2517,7 @@
<instance level="4" name="logical_tile_clb_mode_default__fle_mode_physical__fabric_0"/>
<instance level="5" name="logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0"/>
<instance level="6" name="logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0"/>
<instance level="7" name="frac_lut4_sky130_fd_sc_hd__dfxbp_1_mem"/>
<instance level="7" name="frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem"/>
</hierarchy>
<bitstream>
<bit memory_port="mem_out[0]" value="0"/>
@ -2620,7 +2620,7 @@
<bitstream_block name="logical_tile_clb_mode_default__fle_mode_physical__fabric_0" hierarchy_level="4">
<bitstream_block name="logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0" hierarchy_level="5">
<bitstream_block name="logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0" hierarchy_level="6">
<bitstream_block name="frac_lut4_sky130_fd_sc_hd__dfxbp_1_mem" hierarchy_level="7">
<bitstream_block name="frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem" hierarchy_level="7">
<hierarchy>
<instance level="0" name="fpga_top"/>
<instance level="1" name="grid_clb_2__2_"/>
@ -2629,7 +2629,7 @@
<instance level="4" name="logical_tile_clb_mode_default__fle_mode_physical__fabric_0"/>
<instance level="5" name="logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0"/>
<instance level="6" name="logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0"/>
<instance level="7" name="frac_lut4_sky130_fd_sc_hd__dfxbp_1_mem"/>
<instance level="7" name="frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem"/>
</hierarchy>
<bitstream>
<bit memory_port="mem_out[0]" value="0"/>
@ -2728,7 +2728,7 @@
<bitstream_block name="logical_tile_clb_mode_default__fle_mode_physical__fabric_0" hierarchy_level="4">
<bitstream_block name="logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0" hierarchy_level="5">
<bitstream_block name="logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0" hierarchy_level="6">
<bitstream_block name="frac_lut4_sky130_fd_sc_hd__dfxbp_1_mem" hierarchy_level="7">
<bitstream_block name="frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem" hierarchy_level="7">
<hierarchy>
<instance level="0" name="fpga_top"/>
<instance level="1" name="grid_clb_2__2_"/>
@ -2737,7 +2737,7 @@
<instance level="4" name="logical_tile_clb_mode_default__fle_mode_physical__fabric_0"/>
<instance level="5" name="logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0"/>
<instance level="6" name="logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0"/>
<instance level="7" name="frac_lut4_sky130_fd_sc_hd__dfxbp_1_mem"/>
<instance level="7" name="frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem"/>
</hierarchy>
<bitstream>
<bit memory_port="mem_out[0]" value="0"/>
@ -2836,7 +2836,7 @@
<bitstream_block name="logical_tile_clb_mode_default__fle_mode_physical__fabric_0" hierarchy_level="4">
<bitstream_block name="logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0" hierarchy_level="5">
<bitstream_block name="logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0" hierarchy_level="6">
<bitstream_block name="frac_lut4_sky130_fd_sc_hd__dfxbp_1_mem" hierarchy_level="7">
<bitstream_block name="frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem" hierarchy_level="7">
<hierarchy>
<instance level="0" name="fpga_top"/>
<instance level="1" name="grid_clb_2__2_"/>
@ -2845,7 +2845,7 @@
<instance level="4" name="logical_tile_clb_mode_default__fle_mode_physical__fabric_0"/>
<instance level="5" name="logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0"/>
<instance level="6" name="logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0"/>
<instance level="7" name="frac_lut4_sky130_fd_sc_hd__dfxbp_1_mem"/>
<instance level="7" name="frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem"/>
</hierarchy>
<bitstream>
<bit memory_port="mem_out[0]" value="0"/>
@ -2944,7 +2944,7 @@
<bitstream_block name="logical_tile_clb_mode_default__fle_mode_physical__fabric_0" hierarchy_level="4">
<bitstream_block name="logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0" hierarchy_level="5">
<bitstream_block name="logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0" hierarchy_level="6">
<bitstream_block name="frac_lut4_sky130_fd_sc_hd__dfxbp_1_mem" hierarchy_level="7">
<bitstream_block name="frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem" hierarchy_level="7">
<hierarchy>
<instance level="0" name="fpga_top"/>
<instance level="1" name="grid_clb_2__2_"/>
@ -2953,7 +2953,7 @@
<instance level="4" name="logical_tile_clb_mode_default__fle_mode_physical__fabric_0"/>
<instance level="5" name="logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0"/>
<instance level="6" name="logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0"/>
<instance level="7" name="frac_lut4_sky130_fd_sc_hd__dfxbp_1_mem"/>
<instance level="7" name="frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem"/>
</hierarchy>
<bitstream>
<bit memory_port="mem_out[0]" value="0"/>
@ -3052,7 +3052,7 @@
<bitstream_block name="logical_tile_clb_mode_default__fle_mode_physical__fabric_0" hierarchy_level="4">
<bitstream_block name="logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0" hierarchy_level="5">
<bitstream_block name="logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0" hierarchy_level="6">
<bitstream_block name="frac_lut4_sky130_fd_sc_hd__dfxbp_1_mem" hierarchy_level="7">
<bitstream_block name="frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem" hierarchy_level="7">
<hierarchy>
<instance level="0" name="fpga_top"/>
<instance level="1" name="grid_clb_2__2_"/>
@ -3061,7 +3061,7 @@
<instance level="4" name="logical_tile_clb_mode_default__fle_mode_physical__fabric_0"/>
<instance level="5" name="logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0"/>
<instance level="6" name="logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0"/>
<instance level="7" name="frac_lut4_sky130_fd_sc_hd__dfxbp_1_mem"/>
<instance level="7" name="frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem"/>
</hierarchy>
<bitstream>
<bit memory_port="mem_out[0]" value="0"/>
@ -3160,7 +3160,7 @@
<bitstream_block name="logical_tile_clb_mode_default__fle_mode_physical__fabric_0" hierarchy_level="4">
<bitstream_block name="logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0" hierarchy_level="5">
<bitstream_block name="logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0" hierarchy_level="6">
<bitstream_block name="frac_lut4_sky130_fd_sc_hd__dfxbp_1_mem" hierarchy_level="7">
<bitstream_block name="frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem" hierarchy_level="7">
<hierarchy>
<instance level="0" name="fpga_top"/>
<instance level="1" name="grid_clb_2__2_"/>
@ -3169,7 +3169,7 @@
<instance level="4" name="logical_tile_clb_mode_default__fle_mode_physical__fabric_0"/>
<instance level="5" name="logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0"/>
<instance level="6" name="logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0"/>
<instance level="7" name="frac_lut4_sky130_fd_sc_hd__dfxbp_1_mem"/>
<instance level="7" name="frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem"/>
</hierarchy>
<bitstream>
<bit memory_port="mem_out[0]" value="0"/>
@ -3268,7 +3268,7 @@
<bitstream_block name="logical_tile_clb_mode_default__fle_mode_physical__fabric_0" hierarchy_level="4">
<bitstream_block name="logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0" hierarchy_level="5">
<bitstream_block name="logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0" hierarchy_level="6">
<bitstream_block name="frac_lut4_sky130_fd_sc_hd__dfxbp_1_mem" hierarchy_level="7">
<bitstream_block name="frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem" hierarchy_level="7">
<hierarchy>
<instance level="0" name="fpga_top"/>
<instance level="1" name="grid_clb_2__2_"/>
@ -3277,7 +3277,7 @@
<instance level="4" name="logical_tile_clb_mode_default__fle_mode_physical__fabric_0"/>
<instance level="5" name="logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0"/>
<instance level="6" name="logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0"/>
<instance level="7" name="frac_lut4_sky130_fd_sc_hd__dfxbp_1_mem"/>
<instance level="7" name="frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem"/>
</hierarchy>
<bitstream>
<bit memory_port="mem_out[0]" value="0"/>
@ -3376,7 +3376,7 @@
<bitstream_block name="logical_tile_clb_mode_default__fle_mode_physical__fabric_0" hierarchy_level="4">
<bitstream_block name="logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0" hierarchy_level="5">
<bitstream_block name="logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0" hierarchy_level="6">
<bitstream_block name="frac_lut4_sky130_fd_sc_hd__dfxbp_1_mem" hierarchy_level="7">
<bitstream_block name="frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem" hierarchy_level="7">
<hierarchy>
<instance level="0" name="fpga_top"/>
<instance level="1" name="grid_clb_2__2_"/>
@ -3385,7 +3385,7 @@
<instance level="4" name="logical_tile_clb_mode_default__fle_mode_physical__fabric_0"/>
<instance level="5" name="logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0"/>
<instance level="6" name="logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0"/>
<instance level="7" name="frac_lut4_sky130_fd_sc_hd__dfxbp_1_mem"/>
<instance level="7" name="frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem"/>
</hierarchy>
<bitstream>
<bit memory_port="mem_out[0]" value="0"/>
@ -3485,13 +3485,13 @@
<bitstream_block name="grid_io_top_top_1__3_" hierarchy_level="1">
<bitstream_block name="logical_tile_io_mode_io__0" hierarchy_level="2">
<bitstream_block name="logical_tile_io_mode_physical__iopad_0" hierarchy_level="3">
<bitstream_block name="EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem" hierarchy_level="4">
<bitstream_block name="EMBEDDED_IO_sky130_fd_sc_hd__dfxtp_1_mem" hierarchy_level="4">
<hierarchy>
<instance level="0" name="fpga_top"/>
<instance level="1" name="grid_io_top_top_1__3_"/>
<instance level="2" name="logical_tile_io_mode_io__0"/>
<instance level="3" name="logical_tile_io_mode_physical__iopad_0"/>
<instance level="4" name="EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem"/>
<instance level="4" name="EMBEDDED_IO_sky130_fd_sc_hd__dfxtp_1_mem"/>
</hierarchy>
<bitstream>
<bit memory_port="mem_out[0]" value="1"/>
@ -3503,13 +3503,13 @@
<bitstream_block name="grid_io_top_top_2__3_" hierarchy_level="1">
<bitstream_block name="logical_tile_io_mode_io__0" hierarchy_level="2">
<bitstream_block name="logical_tile_io_mode_physical__iopad_0" hierarchy_level="3">
<bitstream_block name="EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem" hierarchy_level="4">
<bitstream_block name="EMBEDDED_IO_sky130_fd_sc_hd__dfxtp_1_mem" hierarchy_level="4">
<hierarchy>
<instance level="0" name="fpga_top"/>
<instance level="1" name="grid_io_top_top_2__3_"/>
<instance level="2" name="logical_tile_io_mode_io__0"/>
<instance level="3" name="logical_tile_io_mode_physical__iopad_0"/>
<instance level="4" name="EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem"/>
<instance level="4" name="EMBEDDED_IO_sky130_fd_sc_hd__dfxtp_1_mem"/>
</hierarchy>
<bitstream>
<bit memory_port="mem_out[0]" value="1"/>
@ -3521,13 +3521,13 @@
<bitstream_block name="grid_io_right_right_3__1_" hierarchy_level="1">
<bitstream_block name="logical_tile_io_mode_io__0" hierarchy_level="2">
<bitstream_block name="logical_tile_io_mode_physical__iopad_0" hierarchy_level="3">
<bitstream_block name="EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem" hierarchy_level="4">
<bitstream_block name="EMBEDDED_IO_sky130_fd_sc_hd__dfxtp_1_mem" hierarchy_level="4">
<hierarchy>
<instance level="0" name="fpga_top"/>
<instance level="1" name="grid_io_right_right_3__1_"/>
<instance level="2" name="logical_tile_io_mode_io__0"/>
<instance level="3" name="logical_tile_io_mode_physical__iopad_0"/>
<instance level="4" name="EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem"/>
<instance level="4" name="EMBEDDED_IO_sky130_fd_sc_hd__dfxtp_1_mem"/>
</hierarchy>
<bitstream>
<bit memory_port="mem_out[0]" value="1"/>
@ -3539,13 +3539,13 @@
<bitstream_block name="grid_io_right_right_3__2_" hierarchy_level="1">
<bitstream_block name="logical_tile_io_mode_io__0" hierarchy_level="2">
<bitstream_block name="logical_tile_io_mode_physical__iopad_0" hierarchy_level="3">
<bitstream_block name="EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem" hierarchy_level="4">
<bitstream_block name="EMBEDDED_IO_sky130_fd_sc_hd__dfxtp_1_mem" hierarchy_level="4">
<hierarchy>
<instance level="0" name="fpga_top"/>
<instance level="1" name="grid_io_right_right_3__2_"/>
<instance level="2" name="logical_tile_io_mode_io__0"/>
<instance level="3" name="logical_tile_io_mode_physical__iopad_0"/>
<instance level="4" name="EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem"/>
<instance level="4" name="EMBEDDED_IO_sky130_fd_sc_hd__dfxtp_1_mem"/>
</hierarchy>
<bitstream>
<bit memory_port="mem_out[0]" value="1"/>
@ -3557,13 +3557,13 @@
<bitstream_block name="grid_io_bottom_bottom_1__0_" hierarchy_level="1">
<bitstream_block name="logical_tile_io_mode_io__0" hierarchy_level="2">
<bitstream_block name="logical_tile_io_mode_physical__iopad_0" hierarchy_level="3">
<bitstream_block name="EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem" hierarchy_level="4">
<bitstream_block name="EMBEDDED_IO_sky130_fd_sc_hd__dfxtp_1_mem" hierarchy_level="4">
<hierarchy>
<instance level="0" name="fpga_top"/>
<instance level="1" name="grid_io_bottom_bottom_1__0_"/>
<instance level="2" name="logical_tile_io_mode_io__0"/>
<instance level="3" name="logical_tile_io_mode_physical__iopad_0"/>
<instance level="4" name="EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem"/>
<instance level="4" name="EMBEDDED_IO_sky130_fd_sc_hd__dfxtp_1_mem"/>
</hierarchy>
<bitstream>
<bit memory_port="mem_out[0]" value="1"/>
@ -3573,13 +3573,13 @@
</bitstream_block>
<bitstream_block name="logical_tile_io_mode_io__1" hierarchy_level="2">
<bitstream_block name="logical_tile_io_mode_physical__iopad_0" hierarchy_level="3">
<bitstream_block name="EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem" hierarchy_level="4">
<bitstream_block name="EMBEDDED_IO_sky130_fd_sc_hd__dfxtp_1_mem" hierarchy_level="4">
<hierarchy>
<instance level="0" name="fpga_top"/>
<instance level="1" name="grid_io_bottom_bottom_1__0_"/>
<instance level="2" name="logical_tile_io_mode_io__1"/>
<instance level="3" name="logical_tile_io_mode_physical__iopad_0"/>
<instance level="4" name="EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem"/>
<instance level="4" name="EMBEDDED_IO_sky130_fd_sc_hd__dfxtp_1_mem"/>
</hierarchy>
<bitstream>
<bit memory_port="mem_out[0]" value="1"/>
@ -3589,13 +3589,13 @@
</bitstream_block>
<bitstream_block name="logical_tile_io_mode_io__2" hierarchy_level="2">
<bitstream_block name="logical_tile_io_mode_physical__iopad_0" hierarchy_level="3">
<bitstream_block name="EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem" hierarchy_level="4">
<bitstream_block name="EMBEDDED_IO_sky130_fd_sc_hd__dfxtp_1_mem" hierarchy_level="4">
<hierarchy>
<instance level="0" name="fpga_top"/>
<instance level="1" name="grid_io_bottom_bottom_1__0_"/>
<instance level="2" name="logical_tile_io_mode_io__2"/>
<instance level="3" name="logical_tile_io_mode_physical__iopad_0"/>
<instance level="4" name="EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem"/>
<instance level="4" name="EMBEDDED_IO_sky130_fd_sc_hd__dfxtp_1_mem"/>
</hierarchy>
<bitstream>
<bit memory_port="mem_out[0]" value="1"/>
@ -3605,13 +3605,13 @@
</bitstream_block>
<bitstream_block name="logical_tile_io_mode_io__3" hierarchy_level="2">
<bitstream_block name="logical_tile_io_mode_physical__iopad_0" hierarchy_level="3">
<bitstream_block name="EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem" hierarchy_level="4">
<bitstream_block name="EMBEDDED_IO_sky130_fd_sc_hd__dfxtp_1_mem" hierarchy_level="4">
<hierarchy>
<instance level="0" name="fpga_top"/>
<instance level="1" name="grid_io_bottom_bottom_1__0_"/>
<instance level="2" name="logical_tile_io_mode_io__3"/>
<instance level="3" name="logical_tile_io_mode_physical__iopad_0"/>
<instance level="4" name="EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem"/>
<instance level="4" name="EMBEDDED_IO_sky130_fd_sc_hd__dfxtp_1_mem"/>
</hierarchy>
<bitstream>
<bit memory_port="mem_out[0]" value="1"/>
@ -3621,13 +3621,13 @@
</bitstream_block>
<bitstream_block name="logical_tile_io_mode_io__4" hierarchy_level="2">
<bitstream_block name="logical_tile_io_mode_physical__iopad_0" hierarchy_level="3">
<bitstream_block name="EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem" hierarchy_level="4">
<bitstream_block name="EMBEDDED_IO_sky130_fd_sc_hd__dfxtp_1_mem" hierarchy_level="4">
<hierarchy>
<instance level="0" name="fpga_top"/>
<instance level="1" name="grid_io_bottom_bottom_1__0_"/>
<instance level="2" name="logical_tile_io_mode_io__4"/>
<instance level="3" name="logical_tile_io_mode_physical__iopad_0"/>
<instance level="4" name="EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem"/>
<instance level="4" name="EMBEDDED_IO_sky130_fd_sc_hd__dfxtp_1_mem"/>
</hierarchy>
<bitstream>
<bit memory_port="mem_out[0]" value="1"/>
@ -3637,13 +3637,13 @@
</bitstream_block>
<bitstream_block name="logical_tile_io_mode_io__5" hierarchy_level="2">
<bitstream_block name="logical_tile_io_mode_physical__iopad_0" hierarchy_level="3">
<bitstream_block name="EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem" hierarchy_level="4">
<bitstream_block name="EMBEDDED_IO_sky130_fd_sc_hd__dfxtp_1_mem" hierarchy_level="4">
<hierarchy>
<instance level="0" name="fpga_top"/>
<instance level="1" name="grid_io_bottom_bottom_1__0_"/>
<instance level="2" name="logical_tile_io_mode_io__5"/>
<instance level="3" name="logical_tile_io_mode_physical__iopad_0"/>
<instance level="4" name="EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem"/>
<instance level="4" name="EMBEDDED_IO_sky130_fd_sc_hd__dfxtp_1_mem"/>
</hierarchy>
<bitstream>
<bit memory_port="mem_out[0]" value="0"/>
@ -3655,13 +3655,13 @@
<bitstream_block name="grid_io_bottom_bottom_2__0_" hierarchy_level="1">
<bitstream_block name="logical_tile_io_mode_io__0" hierarchy_level="2">
<bitstream_block name="logical_tile_io_mode_physical__iopad_0" hierarchy_level="3">
<bitstream_block name="EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem" hierarchy_level="4">
<bitstream_block name="EMBEDDED_IO_sky130_fd_sc_hd__dfxtp_1_mem" hierarchy_level="4">
<hierarchy>
<instance level="0" name="fpga_top"/>
<instance level="1" name="grid_io_bottom_bottom_2__0_"/>
<instance level="2" name="logical_tile_io_mode_io__0"/>
<instance level="3" name="logical_tile_io_mode_physical__iopad_0"/>
<instance level="4" name="EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem"/>
<instance level="4" name="EMBEDDED_IO_sky130_fd_sc_hd__dfxtp_1_mem"/>
</hierarchy>
<bitstream>
<bit memory_port="mem_out[0]" value="1"/>
@ -3671,13 +3671,13 @@
</bitstream_block>
<bitstream_block name="logical_tile_io_mode_io__1" hierarchy_level="2">
<bitstream_block name="logical_tile_io_mode_physical__iopad_0" hierarchy_level="3">
<bitstream_block name="EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem" hierarchy_level="4">
<bitstream_block name="EMBEDDED_IO_sky130_fd_sc_hd__dfxtp_1_mem" hierarchy_level="4">
<hierarchy>
<instance level="0" name="fpga_top"/>
<instance level="1" name="grid_io_bottom_bottom_2__0_"/>
<instance level="2" name="logical_tile_io_mode_io__1"/>
<instance level="3" name="logical_tile_io_mode_physical__iopad_0"/>
<instance level="4" name="EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem"/>
<instance level="4" name="EMBEDDED_IO_sky130_fd_sc_hd__dfxtp_1_mem"/>
</hierarchy>
<bitstream>
<bit memory_port="mem_out[0]" value="1"/>
@ -3687,13 +3687,13 @@
</bitstream_block>
<bitstream_block name="logical_tile_io_mode_io__2" hierarchy_level="2">
<bitstream_block name="logical_tile_io_mode_physical__iopad_0" hierarchy_level="3">
<bitstream_block name="EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem" hierarchy_level="4">
<bitstream_block name="EMBEDDED_IO_sky130_fd_sc_hd__dfxtp_1_mem" hierarchy_level="4">
<hierarchy>
<instance level="0" name="fpga_top"/>
<instance level="1" name="grid_io_bottom_bottom_2__0_"/>
<instance level="2" name="logical_tile_io_mode_io__2"/>
<instance level="3" name="logical_tile_io_mode_physical__iopad_0"/>
<instance level="4" name="EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem"/>
<instance level="4" name="EMBEDDED_IO_sky130_fd_sc_hd__dfxtp_1_mem"/>
</hierarchy>
<bitstream>
<bit memory_port="mem_out[0]" value="1"/>
@ -3703,13 +3703,13 @@
</bitstream_block>
<bitstream_block name="logical_tile_io_mode_io__3" hierarchy_level="2">
<bitstream_block name="logical_tile_io_mode_physical__iopad_0" hierarchy_level="3">
<bitstream_block name="EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem" hierarchy_level="4">
<bitstream_block name="EMBEDDED_IO_sky130_fd_sc_hd__dfxtp_1_mem" hierarchy_level="4">
<hierarchy>
<instance level="0" name="fpga_top"/>
<instance level="1" name="grid_io_bottom_bottom_2__0_"/>
<instance level="2" name="logical_tile_io_mode_io__3"/>
<instance level="3" name="logical_tile_io_mode_physical__iopad_0"/>
<instance level="4" name="EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem"/>
<instance level="4" name="EMBEDDED_IO_sky130_fd_sc_hd__dfxtp_1_mem"/>
</hierarchy>
<bitstream>
<bit memory_port="mem_out[0]" value="1"/>
@ -3719,13 +3719,13 @@
</bitstream_block>
<bitstream_block name="logical_tile_io_mode_io__4" hierarchy_level="2">
<bitstream_block name="logical_tile_io_mode_physical__iopad_0" hierarchy_level="3">
<bitstream_block name="EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem" hierarchy_level="4">
<bitstream_block name="EMBEDDED_IO_sky130_fd_sc_hd__dfxtp_1_mem" hierarchy_level="4">
<hierarchy>
<instance level="0" name="fpga_top"/>
<instance level="1" name="grid_io_bottom_bottom_2__0_"/>
<instance level="2" name="logical_tile_io_mode_io__4"/>
<instance level="3" name="logical_tile_io_mode_physical__iopad_0"/>
<instance level="4" name="EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem"/>
<instance level="4" name="EMBEDDED_IO_sky130_fd_sc_hd__dfxtp_1_mem"/>
</hierarchy>
<bitstream>
<bit memory_port="mem_out[0]" value="1"/>
@ -3735,13 +3735,13 @@
</bitstream_block>
<bitstream_block name="logical_tile_io_mode_io__5" hierarchy_level="2">
<bitstream_block name="logical_tile_io_mode_physical__iopad_0" hierarchy_level="3">
<bitstream_block name="EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem" hierarchy_level="4">
<bitstream_block name="EMBEDDED_IO_sky130_fd_sc_hd__dfxtp_1_mem" hierarchy_level="4">
<hierarchy>
<instance level="0" name="fpga_top"/>
<instance level="1" name="grid_io_bottom_bottom_2__0_"/>
<instance level="2" name="logical_tile_io_mode_io__5"/>
<instance level="3" name="logical_tile_io_mode_physical__iopad_0"/>
<instance level="4" name="EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem"/>
<instance level="4" name="EMBEDDED_IO_sky130_fd_sc_hd__dfxtp_1_mem"/>
</hierarchy>
<bitstream>
<bit memory_port="mem_out[0]" value="1"/>
@ -3753,13 +3753,13 @@
<bitstream_block name="grid_io_left_left_0__1_" hierarchy_level="1">
<bitstream_block name="logical_tile_io_mode_io__0" hierarchy_level="2">
<bitstream_block name="logical_tile_io_mode_physical__iopad_0" hierarchy_level="3">
<bitstream_block name="EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem" hierarchy_level="4">
<bitstream_block name="EMBEDDED_IO_sky130_fd_sc_hd__dfxtp_1_mem" hierarchy_level="4">
<hierarchy>
<instance level="0" name="fpga_top"/>
<instance level="1" name="grid_io_left_left_0__1_"/>
<instance level="2" name="logical_tile_io_mode_io__0"/>
<instance level="3" name="logical_tile_io_mode_physical__iopad_0"/>
<instance level="4" name="EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem"/>
<instance level="4" name="EMBEDDED_IO_sky130_fd_sc_hd__dfxtp_1_mem"/>
</hierarchy>
<bitstream>
<bit memory_port="mem_out[0]" value="1"/>
@ -3771,13 +3771,13 @@
<bitstream_block name="grid_io_left_left_0__2_" hierarchy_level="1">
<bitstream_block name="logical_tile_io_mode_io__0" hierarchy_level="2">
<bitstream_block name="logical_tile_io_mode_physical__iopad_0" hierarchy_level="3">
<bitstream_block name="EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem" hierarchy_level="4">
<bitstream_block name="EMBEDDED_IO_sky130_fd_sc_hd__dfxtp_1_mem" hierarchy_level="4">
<hierarchy>
<instance level="0" name="fpga_top"/>
<instance level="1" name="grid_io_left_left_0__2_"/>
<instance level="2" name="logical_tile_io_mode_io__0"/>
<instance level="3" name="logical_tile_io_mode_physical__iopad_0"/>
<instance level="4" name="EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem"/>
<instance level="4" name="EMBEDDED_IO_sky130_fd_sc_hd__dfxtp_1_mem"/>
</hierarchy>
<bitstream>
<bit memory_port="mem_out[0]" value="1"/>

148
FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/openfpgashell.log
View File

@ -41,9 +41,9 @@ THE SOFTWARE.
Command line to execute: vpr /research/ece/lnis/USERS/DARPA_ERI/GF14nm_chip_2019/ICC2_Methodology_Flow/GANESH/FROG_PnR/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_task/run001/vpr_arch/top/MIN_ROUTE_CHAN_WIDTH/arch/vpr_arch.xml top.blif --clock_modeling route --device 2x2 --route_chan_width 40 --absorb_buffer_luts off
VPR FPGA Placement and Routing.
Version: 0.0.0+55f7a2c1
Revision: 55f7a2c1
Compiled: 2020-11-05T12:41:40
Version: 0.0.0+520e54d7
Revision: 520e54d7
Compiled: 2020-11-09T18:01:05
Compiler: GNU 8.4.0 on Linux-3.10.0-1062.9.1.el7.x86_64 x86_64
Build Info: release VTR_ASSERT_LEVEL=2
@ -65,25 +65,25 @@ Warning 2: Model 'io' output port 'inpad' has no timing specification (no clock
Warning 3: Model 'frac_lut4' input port 'in' has no timing specification (no clock specified to create a sequential input port, not combinationally connected to any outputs, not a clock input)
Warning 4: Model 'frac_lut4' output port 'lut4_out' has no timing specification (no clock specified to create a sequential output port, not combinationally connected to any inputs, not a clock output)
Warning 5: Model 'frac_lut4' output port 'lut3_out' has no timing specification (no clock specified to create a sequential output port, not combinationally connected to any inputs, not a clock output)
# Loading Architecture Description took 0.00 seconds (max_rss 9.0 MiB, delta_rss +0.6 MiB)
# Loading Architecture Description took 0.01 seconds (max_rss 9.0 MiB, delta_rss +0.6 MiB)
# Building complex block graph
Warning 6: [LINE 582] false logically-equivalent pin clb[0].I0[1].
Warning 7: [LINE 582] false logically-equivalent pin clb[0].I0[2].
Warning 8: [LINE 588] false logically-equivalent pin clb[0].I1[1].
Warning 9: [LINE 588] false logically-equivalent pin clb[0].I1[2].
Warning 10: [LINE 594] false logically-equivalent pin clb[0].I2[1].
Warning 11: [LINE 594] false logically-equivalent pin clb[0].I2[2].
Warning 12: [LINE 600] false logically-equivalent pin clb[0].I3[1].
Warning 13: [LINE 600] false logically-equivalent pin clb[0].I3[2].
Warning 14: [LINE 606] false logically-equivalent pin clb[0].I4[1].
Warning 15: [LINE 606] false logically-equivalent pin clb[0].I4[2].
Warning 16: [LINE 612] false logically-equivalent pin clb[0].I5[1].
Warning 17: [LINE 612] false logically-equivalent pin clb[0].I5[2].
Warning 18: [LINE 618] false logically-equivalent pin clb[0].I6[1].
Warning 19: [LINE 618] false logically-equivalent pin clb[0].I6[2].
Warning 20: [LINE 624] false logically-equivalent pin clb[0].I7[1].
Warning 21: [LINE 624] false logically-equivalent pin clb[0].I7[2].
# Building complex block graph took 0.00 seconds (max_rss 9.5 MiB, delta_rss +0.5 MiB)
Warning 6: [LINE 586] false logically-equivalent pin clb[0].I0[1].
Warning 7: [LINE 586] false logically-equivalent pin clb[0].I0[2].
Warning 8: [LINE 592] false logically-equivalent pin clb[0].I1[1].
Warning 9: [LINE 592] false logically-equivalent pin clb[0].I1[2].
Warning 10: [LINE 598] false logically-equivalent pin clb[0].I2[1].
Warning 11: [LINE 598] false logically-equivalent pin clb[0].I2[2].
Warning 12: [LINE 604] false logically-equivalent pin clb[0].I3[1].
Warning 13: [LINE 604] false logically-equivalent pin clb[0].I3[2].
Warning 14: [LINE 610] false logically-equivalent pin clb[0].I4[1].
Warning 15: [LINE 610] false logically-equivalent pin clb[0].I4[2].
Warning 16: [LINE 616] false logically-equivalent pin clb[0].I5[1].
Warning 17: [LINE 616] false logically-equivalent pin clb[0].I5[2].
Warning 18: [LINE 622] false logically-equivalent pin clb[0].I6[1].
Warning 19: [LINE 622] false logically-equivalent pin clb[0].I6[2].
Warning 20: [LINE 628] false logically-equivalent pin clb[0].I7[1].
Warning 21: [LINE 628] false logically-equivalent pin clb[0].I7[2].
# Building complex block graph took 0.01 seconds (max_rss 9.5 MiB, delta_rss +0.5 MiB)
# Load circuit
# Load circuit took 0.00 seconds (max_rss 9.9 MiB, delta_rss +0.4 MiB)
# Clean circuit
@ -250,12 +250,12 @@ Device Utilization: 0.25 (target 1.00)
Netlist conversion complete.
# Packing took 0.00 seconds (max_rss 10.6 MiB, delta_rss +0.7 MiB)
# Packing took 0.01 seconds (max_rss 10.6 MiB, delta_rss +0.7 MiB)
# Load Packing
Begin loading packed FPGA netlist file.
Netlist generated from file 'top.net'.
Detected 0 constant generators (to see names run with higher pack verbosity)
Finished loading packed FPGA netlist file (took 0 seconds).
Finished loading packed FPGA netlist file (took 0.01 seconds).
Warning 34: Treated 0 constant nets as global which will not be routed (to see net names increase packer verbosity).
# Load Packing took 0.01 seconds (max_rss 10.6 MiB, delta_rss +0.1 MiB)
Warning 35: Netlist contains 0 global net to non-global architecture pin connections
@ -301,7 +301,7 @@ Device Utilization: 0.25 (target 1.00)
Physical Tile clb:
Block Utilization: 0.25 Logical Block: clb
## Build Device Grid took 0.00 seconds (max_rss 12.7 MiB, delta_rss +0.0 MiB)
## Build Device Grid took 0.00 seconds (max_rss 10.7 MiB, delta_rss +0.0 MiB)
## Build tileable routing resource graph
X-direction routing channel width is 40
Y-direction routing channel width is 40
@ -309,10 +309,10 @@ Warning 40: in check_rr_node: RR node: 105 type: OPIN location: (1,1) pin: 50 pi
Warning 41: in check_rr_node: RR node: 106 type: OPIN location: (1,1) pin: 51 pin_name: clb.sc_out[0] capacity: 1 has no out-going edges.
Warning 42: in check_rr_node: RR node: 195 type: OPIN location: (2,1) pin: 50 pin_name: clb.regout[0] capacity: 1 has no out-going edges.
Warning 43: in check_rr_node: RR node: 196 type: OPIN location: (2,1) pin: 51 pin_name: clb.sc_out[0] capacity: 1 has no out-going edges.
## Build tileable routing resource graph took 0.01 seconds (max_rss 12.7 MiB, delta_rss +0.0 MiB)
## Build tileable routing resource graph took 0.01 seconds (max_rss 11.2 MiB, delta_rss +0.5 MiB)
RR Graph Nodes: 756
RR Graph Edges: 2930
# Create Device took 0.01 seconds (max_rss 12.7 MiB, delta_rss +0.0 MiB)
# Create Device took 0.01 seconds (max_rss 11.2 MiB, delta_rss +0.5 MiB)
# Placement
## Computing placement delta delay look-up
@ -321,12 +321,12 @@ Warning 44: in check_rr_node: RR node: 119 type: OPIN location: (1,1) pin: 50 pi
Warning 45: in check_rr_node: RR node: 120 type: OPIN location: (1,1) pin: 51 pin_name: clb.sc_out[0] capacity: 1 has no out-going edges.
Warning 46: in check_rr_node: RR node: 327 type: OPIN location: (2,1) pin: 50 pin_name: clb.regout[0] capacity: 1 has no out-going edges.
Warning 47: in check_rr_node: RR node: 328 type: OPIN location: (2,1) pin: 51 pin_name: clb.sc_out[0] capacity: 1 has no out-going edges.
### Build routing resource graph took 0.00 seconds (max_rss 12.7 MiB, delta_rss +0.0 MiB)
### Build routing resource graph took 0.00 seconds (max_rss 11.2 MiB, delta_rss +0.0 MiB)
RR Graph Nodes: 756
RR Graph Edges: 2428
### Computing delta delays
### Computing delta delays took 0.00 seconds (max_rss 12.7 MiB, delta_rss +0.0 MiB)
## Computing placement delta delay look-up took 0.00 seconds (max_rss 12.7 MiB, delta_rss +0.0 MiB)
### Computing delta delays took 0.00 seconds (max_rss 11.5 MiB, delta_rss +0.0 MiB)
## Computing placement delta delay look-up took 0.00 seconds (max_rss 11.5 MiB, delta_rss +0.3 MiB)
There are 3 point to point connections in this circuit.
@ -440,7 +440,7 @@ Placement total # of swap attempts: 292
Swaps aborted : 0 ( 0.0 %)
Aborted Move Reasons:
# Placement took 0.01 seconds (max_rss 12.7 MiB, delta_rss +0.0 MiB)
# Placement took 0.01 seconds (max_rss 11.7 MiB, delta_rss +0.5 MiB)
# Routing
## Build tileable routing resource graph
@ -450,7 +450,7 @@ Warning 48: in check_rr_node: RR node: 105 type: OPIN location: (1,1) pin: 50 pi
Warning 49: in check_rr_node: RR node: 106 type: OPIN location: (1,1) pin: 51 pin_name: clb.sc_out[0] capacity: 1 has no out-going edges.
Warning 50: in check_rr_node: RR node: 195 type: OPIN location: (2,1) pin: 50 pin_name: clb.regout[0] capacity: 1 has no out-going edges.
Warning 51: in check_rr_node: RR node: 196 type: OPIN location: (2,1) pin: 51 pin_name: clb.sc_out[0] capacity: 1 has no out-going edges.
## Build tileable routing resource graph took 0.00 seconds (max_rss 12.7 MiB, delta_rss +0.0 MiB)
## Build tileable routing resource graph took 0.01 seconds (max_rss 11.7 MiB, delta_rss +0.0 MiB)
RR Graph Nodes: 756
RR Graph Edges: 2930
Confirming router algorithm: TIMING_DRIVEN.
@ -464,7 +464,7 @@ Restoring best routing
Critical path: 0.86731 ns
Successfully routed after 2 routing iterations.
Router Stats: total_nets_routed: 4 total_connections_routed: 4 total_heap_pushes: 289 total_heap_pops: 187
# Routing took 0.01 seconds (max_rss 12.7 MiB, delta_rss +0.0 MiB)
# Routing took 0.01 seconds (max_rss 11.9 MiB, delta_rss +0.2 MiB)
Checking to ensure routing is legal...
Completed routing consistency check successfully.
@ -562,9 +562,9 @@ Setup slack histogram:
[ -8.7e-10: -8.7e-10) 0 ( 0.0%) |
[ -8.7e-10: -8.7e-10) 0 ( 0.0%) |
Timing analysis took 0.000351611 seconds (0.000312774 STA, 3.8837e-05 slack) (54 full updates: 51 setup, 0 hold, 3 combined).
Timing analysis took 0.000405567 seconds (0.000363868 STA, 4.1699e-05 slack) (54 full updates: 51 setup, 0 hold, 3 combined).
VPR suceeded
The entire flow of VPR took 0.07 seconds (max_rss 12.7 MiB)
The entire flow of VPR took 0.09 seconds (max_rss 11.9 MiB)
Command line to execute: read_openfpga_arch -f /research/ece/lnis/USERS/DARPA_ERI/GF14nm_chip_2019/ICC2_Methodology_Flow/GANESH/FROG_PnR/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_task/run001/vpr_arch/top/MIN_ROUTE_CHAN_WIDTH/arch/openfpga_arch.xml
@ -574,14 +574,14 @@ Reading XML architecture '/research/ece/lnis/USERS/DARPA_ERI/GF14nm_chip_2019/IC
Read OpenFPGA architecture
Warning 52: Automatically set circuit model 'frac_lut4' to be default in its type.
Warning 53: Automatically set circuit model 'sky130_fd_sc_hd__sdfxtp_1' to be default in its type.
Warning 54: Automatically set circuit model 'sky130_fd_sc_hd__dfxbp_1' to be default in its type.
Use the default configurable memory model 'sky130_fd_sc_hd__dfxbp_1' for circuit model 'mux_tree' port 'sram')
Use the default configurable memory model 'sky130_fd_sc_hd__dfxbp_1' for circuit model 'mux_tree_tapbuf' port 'sram')
Use the default configurable memory model 'sky130_fd_sc_hd__dfxbp_1' for circuit model 'frac_lut4' port 'sram')
Read OpenFPGA architecture took 0.00 seconds (max_rss 12.7 MiB, delta_rss +0.0 MiB)
Warning 54: Automatically set circuit model 'sky130_fd_sc_hd__dfxtp_1' to be default in its type.
Use the default configurable memory model 'sky130_fd_sc_hd__dfxtp_1' for circuit model 'mux_tree' port 'sram')
Use the default configurable memory model 'sky130_fd_sc_hd__dfxtp_1' for circuit model 'mux_tree_tapbuf' port 'sram')
Use the default configurable memory model 'sky130_fd_sc_hd__dfxtp_1' for circuit model 'frac_lut4' port 'sram')
Read OpenFPGA architecture took 0.00 seconds (max_rss 12.0 MiB, delta_rss +0.1 MiB)
Check circuit library
Checking circuit library passed.
Check circuit library took 0.00 seconds (max_rss 12.7 MiB, delta_rss +0.0 MiB)
Check circuit library took 0.00 seconds (max_rss 12.3 MiB, delta_rss +0.0 MiB)
Found 0 errors when checking configurable memory circuit models!
Command line to execute: read_openfpga_simulation_setting -f /research/ece/lnis/USERS/DARPA_ERI/Tapeout/May2020/OpenFPGA_for_Chip/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml
@ -590,7 +590,7 @@ Confirm selected options when call command 'read_openfpga_simulation_setting':
--file, -f: /research/ece/lnis/USERS/DARPA_ERI/Tapeout/May2020/OpenFPGA_for_Chip/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml
Reading XML simulation setting '/research/ece/lnis/USERS/DARPA_ERI/Tapeout/May2020/OpenFPGA_for_Chip/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml'...
Read OpenFPGA simulation settings
Read OpenFPGA simulation settings took 0.00 seconds (max_rss 12.7 MiB, delta_rss +0.0 MiB)
Read OpenFPGA simulation settings took 0.00 seconds (max_rss 12.3 MiB, delta_rss +0.0 MiB)
Command line to execute: link_openfpga_arch --activity_file top_ace_out.act --sort_gsb_chan_node_in_edges
@ -633,7 +633,7 @@ Done with 18 nodes mapping
[88%] Backannotated GSB[2][1]
[100%] Backannotated GSB[2][2]
Backannotated 9 General Switch Blocks (GSBs).
# Build General Switch Block(GSB) annotation on top of routing resource graph took 0.00 seconds (max_rss 12.7 MiB, delta_rss +0.0 MiB)
# Build General Switch Block(GSB) annotation on top of routing resource graph took 0.00 seconds (max_rss 12.3 MiB, delta_rss +0.0 MiB)
# Sort incoming edges for each routing track output node of General Switch Block(GSB)
[11%] Sorted edges for GSB[0][0]
[22%] Sorted edges for GSB[0][1]
@ -645,14 +645,14 @@ Backannotated 9 General Switch Blocks (GSBs).
[88%] Sorted edges for GSB[2][1]
[100%] Sorted edges for GSB[2][2]
Sorted edges for 9 General Switch Blocks (GSBs).
# Sort incoming edges for each routing track output node of General Switch Block(GSB) took 0.00 seconds (max_rss 12.7 MiB, delta_rss +0.0 MiB)
# Sort incoming edges for each routing track output node of General Switch Block(GSB) took 0.00 seconds (max_rss 12.3 MiB, delta_rss +0.0 MiB)
# Build a library of physical multiplexers
Built a multiplexer library of 15 physical multiplexers.
Maximum multiplexer size is 17.
# Build a library of physical multiplexers took 0.00 seconds (max_rss 12.7 MiB, delta_rss +0.0 MiB)
# Build a library of physical multiplexers took 0.00 seconds (max_rss 12.5 MiB, delta_rss +0.3 MiB)
# Build the annotation about direct connection between tiles
Built 6 tile-to-tile direct connections
# Build the annotation about direct connection between tiles took 0.00 seconds (max_rss 12.7 MiB, delta_rss +0.0 MiB)
# Build the annotation about direct connection between tiles took 0.00 seconds (max_rss 12.5 MiB, delta_rss +0.0 MiB)
Building annotation for mapped blocks on grid locations...Done
User specified the operating clock frequency to use VPR results
Use VPR critical path delay 1.04077e-18 [ns] with a 20 [%] slack in OpenFPGA.
@ -662,7 +662,7 @@ Average net density: 0.42
Median net density: 0.00
Average net density after weighting: 0.42
Will apply 2 operating clock cycles to simulations
Link OpenFPGA architecture to VPR architecture took 0.00 seconds (max_rss 12.7 MiB, delta_rss +0.0 MiB)
Link OpenFPGA architecture to VPR architecture took 0.00 seconds (max_rss 12.6 MiB, delta_rss +0.3 MiB)
Command line to execute: build_fabric --compress_routing --duplicate_grid_pin --load_fabric_key /research/ece/lnis/USERS/DARPA_ERI/Tapeout/May2020/OpenFPGA_for_Chip/openfpga_flow/tasks/FPGA22_HIER_SKY_task/arch/fabric_key.xml
@ -676,7 +676,7 @@ Confirm selected options when call command 'build_fabric':
--verbose: off
Identify unique General Switch Blocks (GSBs)
Detected 9 unique general switch blocks from a total of 9 (compression rate=0.00%)
Identify unique General Switch Blocks (GSBs) took 0.00 seconds (max_rss 12.7 MiB, delta_rss +0.0 MiB)
Identify unique General Switch Blocks (GSBs) took 0.00 seconds (max_rss 12.6 MiB, delta_rss +0.0 MiB)
Read Fabric Key
Read Fabric Key took 0.00 seconds (max_rss 12.7 MiB, delta_rss +0.0 MiB)
@ -691,7 +691,7 @@ Build fabric module graph
# Build local encoder (for multiplexers) modules
# Build local encoder (for multiplexers) modules took 0.00 seconds (max_rss 12.7 MiB, delta_rss +0.0 MiB)
# Building multiplexer modules
# Building multiplexer modules took 0.00 seconds (max_rss 12.9 MiB, delta_rss +0.2 MiB)
# Building multiplexer modules took 0.00 seconds (max_rss 12.9 MiB, delta_rss +0.3 MiB)
# Build Look-Up Table (LUT) modules
# Build Look-Up Table (LUT) modules took 0.00 seconds (max_rss 13.2 MiB, delta_rss +0.3 MiB)
# Build wire modules
@ -703,41 +703,41 @@ Building logical tiles...Done
Building physical tiles...Done
# Build grid modules took 0.00 seconds (max_rss 13.7 MiB, delta_rss +0.5 MiB)
# Build unique routing modules...
# Build unique routing modules... took 0.01 seconds (max_rss 16.5 MiB, delta_rss +2.8 MiB)
# Build unique routing modules... took 0.02 seconds (max_rss 15.8 MiB, delta_rss +2.1 MiB)
# Build FPGA fabric module
## Add grid instances to top module
## Add grid instances to top module took 0.00 seconds (max_rss 16.5 MiB, delta_rss +0.0 MiB)
## Add grid instances to top module took 0.00 seconds (max_rss 15.8 MiB, delta_rss +0.0 MiB)
## Add switch block instances to top module
## Add switch block instances to top module took 0.00 seconds (max_rss 16.5 MiB, delta_rss +0.0 MiB)
## Add switch block instances to top module took 0.00 seconds (max_rss 15.8 MiB, delta_rss +0.0 MiB)
## Add connection block instances to top module
## Add connection block instances to top module took 0.00 seconds (max_rss 16.5 MiB, delta_rss +0.0 MiB)
## Add connection block instances to top module took 0.00 seconds (max_rss 15.8 MiB, delta_rss +0.0 MiB)
## Add connection block instances to top module
## Add connection block instances to top module took 0.00 seconds (max_rss 16.5 MiB, delta_rss +0.0 MiB)
## Add connection block instances to top module took 0.00 seconds (max_rss 16.0 MiB, delta_rss +0.3 MiB)
## Add module nets between grids and GSBs
## Add module nets between grids and GSBs took 0.00 seconds (max_rss 17.0 MiB, delta_rss +0.5 MiB)
## Add module nets between grids and GSBs took 0.01 seconds (max_rss 16.5 MiB, delta_rss +0.5 MiB)
## Add module nets for inter-tile connections
## Add module nets for inter-tile connections took 0.00 seconds (max_rss 17.0 MiB, delta_rss +0.0 MiB)
## Add module nets for inter-tile connections took 0.00 seconds (max_rss 16.5 MiB, delta_rss +0.0 MiB)
## Add module nets for configuration buses
## Add module nets for configuration buses took 0.00 seconds (max_rss 17.3 MiB, delta_rss +0.0 MiB)
# Build FPGA fabric module took 0.01 seconds (max_rss 17.3 MiB, delta_rss +0.8 MiB)
Build fabric module graph took 0.02 seconds (max_rss 17.3 MiB, delta_rss +4.6 MiB)
## Add module nets for configuration buses took 0.00 seconds (max_rss 16.8 MiB, delta_rss +0.3 MiB)
# Build FPGA fabric module took 0.01 seconds (max_rss 16.8 MiB, delta_rss +1.0 MiB)
Build fabric module graph took 0.03 seconds (max_rss 16.8 MiB, delta_rss +4.1 MiB)
Create I/O location mapping for top module
Create I/O location mapping for top module took 0.00 seconds (max_rss 17.3 MiB, delta_rss +0.0 MiB)
Create I/O location mapping for top module took 0.00 seconds (max_rss 16.8 MiB, delta_rss +0.0 MiB)
Command line to execute: repack
Confirm selected options when call command 'repack':
--verbose: off
Build routing resource graph for the physical implementation of logical tile
Build routing resource graph for the physical implementation of logical tile took 0.00 seconds (max_rss 17.6 MiB, delta_rss +0.3 MiB)
Build routing resource graph for the physical implementation of logical tile took 0.00 seconds (max_rss 17.0 MiB, delta_rss +0.3 MiB)
Repack clustered blocks to physical implementation of logical tile
Repack clustered block 'c'...Done
Repack clustered block 'out:c'...Done
Repack clustered block 'a'...Done
Repack clustered block 'b'...Done
Repack clustered blocks to physical implementation of logical tile took 0.00 seconds (max_rss 17.6 MiB, delta_rss +0.0 MiB)
Repack clustered blocks to physical implementation of logical tile took 0.00 seconds (max_rss 17.0 MiB, delta_rss +0.0 MiB)
Build truth tables for physical LUTs
Build truth tables for physical LUTs took 0.00 seconds (max_rss 17.8 MiB, delta_rss +0.3 MiB)
Build truth tables for physical LUTs took 0.00 seconds (max_rss 17.0 MiB, delta_rss +0.0 MiB)
Command line to execute: build_architecture_bitstream --write_file fabric_indepenent_bitstream.xml
@ -753,10 +753,10 @@ Generating bitstream for X-direction Connection blocks ...Done
Generating bitstream for Y-direction Connection blocks ...Done
Build fabric-independent bitstream for implementation 'top'
took 0.01 seconds (max_rss 17.8 MiB, delta_rss +0.0 MiB)
took 0.01 seconds (max_rss 17.0 MiB, delta_rss +0.0 MiB)
Warning 56: Directory path is empty and nothing will be created.
Write 2106 architecture independent bitstream into XML file 'fabric_indepenent_bitstream.xml'
Write 2106 architecture independent bitstream into XML file 'fabric_indepenent_bitstream.xml' took 0.02 seconds (max_rss 17.8 MiB, delta_rss +0.0 MiB)
Write 2106 architecture independent bitstream into XML file 'fabric_indepenent_bitstream.xml' took 0.03 seconds (max_rss 17.3 MiB, delta_rss +0.3 MiB)
Command line to execute: build_fabric_bitstream
@ -767,7 +767,7 @@ Build fabric dependent bitstream
Build fabric dependent bitstream
took 0.00 seconds (max_rss 18.1 MiB, delta_rss +0.3 MiB)
took 0.00 seconds (max_rss 17.3 MiB, delta_rss +0.0 MiB)
Command line to execute: write_fabric_bitstream --format plain_text --file fabric_bitstream.bit
@ -777,7 +777,7 @@ Confirm selected options when call command 'write_fabric_bitstream':
--verbose: off
Warning 57: Directory path is empty and nothing will be created.
Write 2106 fabric bitstream into plain text file 'fabric_bitstream.bit'
Write 2106 fabric bitstream into plain text file 'fabric_bitstream.bit' took 0.01 seconds (max_rss 18.1 MiB, delta_rss +0.0 MiB)
Write 2106 fabric bitstream into plain text file 'fabric_bitstream.bit' took 0.00 seconds (max_rss 17.3 MiB, delta_rss +0.0 MiB)
Command line to execute: write_fabric_bitstream --format xml --file fabric_bitstream.xml
@ -787,7 +787,7 @@ Confirm selected options when call command 'write_fabric_bitstream':
--verbose: off
Warning 58: Directory path is empty and nothing will be created.
Write 2106 fabric bitstream into xml file 'fabric_bitstream.xml'
Write 2106 fabric bitstream into xml file 'fabric_bitstream.xml' took 0.01 seconds (max_rss 18.1 MiB, delta_rss +0.0 MiB)
Write 2106 fabric bitstream into xml file 'fabric_bitstream.xml' took 0.01 seconds (max_rss 17.3 MiB, delta_rss +0.0 MiB)
Command line to execute: write_fabric_verilog --file ./SRC --explicit_port_mapping --include_timing --include_signal_init --support_icarus_simulator --verbose
@ -849,7 +849,7 @@ Building physical tiles...Done
Writing Verilog netlist for top-level module of FPGA fabric './SRC/fpga_top.v'...Done
Written 73 Verilog modules in total
Write Verilog netlists for FPGA fabric
took 0.17 seconds (max_rss 18.3 MiB, delta_rss +0.2 MiB)
took 0.19 seconds (max_rss 17.7 MiB, delta_rss +0.4 MiB)
Command line to execute: write_verilog_testbench --file ./SRC --reference_benchmark_file_path top_output_verilog.v --print_top_testbench --print_preconfig_top_testbench --print_simulation_ini ./SimulationDeck/simulation_deck.ini --explicit_port_mapping
@ -869,17 +869,17 @@ Write Verilog testbenches for FPGA fabric
Warning 60: Directory './SRC' already exists. Will overwrite contents
# Write pre-configured FPGA top-level Verilog netlist for design 'top'
# Write pre-configured FPGA top-level Verilog netlist for design 'top' took 0.01 seconds (max_rss 18.3 MiB, delta_rss +0.0 MiB)
# Write pre-configured FPGA top-level Verilog netlist for design 'top' took 0.01 seconds (max_rss 17.7 MiB, delta_rss +0.0 MiB)
# Write configuration-skip testbench for FPGA top-level Verilog netlist implemented by 'top'
# Write configuration-skip testbench for FPGA top-level Verilog netlist implemented by 'top' took 0.00 seconds (max_rss 18.3 MiB, delta_rss +0.0 MiB)
# Write configuration-skip testbench for FPGA top-level Verilog netlist implemented by 'top' took 0.00 seconds (max_rss 17.7 MiB, delta_rss +0.0 MiB)
# Write autocheck testbench for FPGA top-level Verilog netlist for 'top'
Will use 2107 configuration clock cycles to top testbench
# Write autocheck testbench for FPGA top-level Verilog netlist for 'top' took 0.01 seconds (max_rss 18.3 MiB, delta_rss +0.0 MiB)
# Write autocheck testbench for FPGA top-level Verilog netlist for 'top' took 0.01 seconds (max_rss 17.8 MiB, delta_rss +0.1 MiB)
Succeed to create directory './SimulationDeck'
# Write exchangeable file containing simulation information './SimulationDeck/simulation_deck.ini'
# Write exchangeable file containing simulation information './SimulationDeck/simulation_deck.ini' took 0.00 seconds (max_rss 18.3 MiB, delta_rss +0.0 MiB)
# Write exchangeable file containing simulation information './SimulationDeck/simulation_deck.ini' took 0.00 seconds (max_rss 17.8 MiB, delta_rss +0.0 MiB)
Write Verilog testbenches for FPGA fabric
took 0.03 seconds (max_rss 18.3 MiB, delta_rss +0.0 MiB)
took 0.03 seconds (max_rss 17.8 MiB, delta_rss +0.1 MiB)
Command line to execute: exit
@ -887,6 +887,6 @@ Confirm selected options when call command 'exit':
Finish execution with 0 errors
The entire OpenFPGA flow took 0.19 seconds
The entire OpenFPGA flow took 0.25 seconds
Thank you for using OpenFPGA!

9
FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_task/arch/openfpga_arch.xml
View File

@ -171,16 +171,15 @@
<port type="output" prefix="lut3_out" size="2" lut_frac_level="3" lut_output_mask="0,1"/>
<port type="output" prefix="lut4_out" size="1" lut_output_mask="0"/>
<port type="sram" prefix="sram" size="16"/>
<port type="sram" prefix="mode" size="1" mode_select="true" circuit_model_name="sky130_fd_sc_hd__dfxbp_1" default_val="1"/>
<port type="sram" prefix="mode" size="1" mode_select="true" circuit_model_name="sky130_fd_sc_hd__dfxtp_1" default_val="1"/>
</circuit_model>
<!--Scan-chain DFF subckt ports should be defined as <D> <Q> <Qb> <CLK> <RESET> <SET> -->
<circuit_model type="ccff" name="sky130_fd_sc_hd__dfxbp_1" prefix="sky130_fd_sc_hd__dfxbp_1" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/tasks/FPGA22_HIER_SKY_PNR/skywater/libraries/sky130_fd_sc_hd/latest/cells/dfxbp/sky130_fd_sc_hd__dfxbp_1.v">
<circuit_model type="ccff" name="sky130_fd_sc_hd__dfxtp_1" prefix="sky130_fd_sc_hd__dfxtp_1" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/tasks/FPGA22_HIER_SKY_PNR/skywater/libraries/sky130_fd_sc_hd/latest/cells/dfxtp/sky130_fd_sc_hd__dfxtp_1.v">
<design_technology type="cmos"/>
<input_buffer exist="true" circuit_model_name="sky130_fd_sc_hd__inv_1"/>
<output_buffer exist="true" circuit_model_name="sky130_fd_sc_hd__inv_1"/>
<port type="input" prefix="D" size="1"/>
<port type="output" prefix="Q" size="1"/>
<port type="output" prefix="Q_N" size="1"/>
<port type="clock" prefix="prog_clk" lib_name="CLK" size="1" is_global="true" default_val="0" is_prog="true"/>
</circuit_model>
<circuit_model type="iopad" name="EMBEDDED_IO" prefix="EMBEDDED_IO" is_default="true" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/tasks/FPGA22_HIER_SKY_PNR/sc_verilog/digital_io_hd.v">
@ -192,11 +191,11 @@
<port type="output" prefix="SOC_DIR" lib_name="SOC_DIR" size="1" is_global="true" is_io="true"/>
<port type="output" prefix="inpad" lib_name="FPGA_IN" size="1"/>
<port type="input" prefix="outpad" lib_name="FPGA_OUT" size="1"/>
<port type="sram" prefix="en" lib_name="FPGA_DIR" size="1" mode_select="true" circuit_model_name="sky130_fd_sc_hd__dfxbp_1" default_val="1"/>
<port type="sram" prefix="en" lib_name="FPGA_DIR" size="1" mode_select="true" circuit_model_name="sky130_fd_sc_hd__dfxtp_1" default_val="1"/>
</circuit_model>
</circuit_library>
<configuration_protocol>
<organization type="scan_chain" circuit_model_name="sky130_fd_sc_hd__dfxbp_1" num_regions="1"/>
<organization type="scan_chain" circuit_model_name="sky130_fd_sc_hd__dfxtp_1" num_regions="1"/>
</configuration_protocol>
<connection_block>
<switch name="ipin_cblock" circuit_model_name="mux_tree_tapbuf"/>

20
FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_task/arch/vpr_arch.xml
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@ -579,49 +579,53 @@
<!-- We use direct connections to reduce the area to the most
The global local routing is going to compensate the loss in routability
-->
<direct name="direct_fle0" input="clb.I0" output="fle[0:0].in[0:2]">
<!-- FIXME: The implicit port definition results in I0[0] connected to
in[2]. Such twisted connection is not expected.
I[0] should be connected to in[0]
-->
<direct name="direct_fle0" input="clb.I0[0:2]" output="fle[0:0].in[0:2]">
<!-- TODO: Timing should be backannotated from post-PnR results -->
</direct>
<direct name="direct_fle0i" input="clb.I0i" output="fle[0:0].in[3]">
<!-- TODO: Timing should be backannotated from post-PnR results -->
</direct>
<direct name="direct_fle1" input="clb.I1" output="fle[1:1].in[0:2]">
<direct name="direct_fle1" input="clb.I1[0:2]" output="fle[1:1].in[0:2]">
<!-- TODO: Timing should be backannotated from post-PnR results -->
</direct>
<direct name="direct_fle1i" input="clb.I1i" output="fle[1:1].in[3]">
<!-- TODO: Timing should be backannotated from post-PnR results -->
</direct>
<direct name="direct_fle2" input="clb.I2" output="fle[2:2].in[0:2]">
<direct name="direct_fle2" input="clb.I2[0:2]" output="fle[2:2].in[0:2]">
<!-- TODO: Timing should be backannotated from post-PnR results -->
</direct>
<direct name="direct_fle2i" input="clb.I2i" output="fle[2:2].in[3]">
<!-- TODO: Timing should be backannotated from post-PnR results -->
</direct>
<direct name="direct_fle3" input="clb.I3" output="fle[3:3].in[0:2]">
<direct name="direct_fle3" input="clb.I3[0:2]" output="fle[3:3].in[0:2]">
<!-- TODO: Timing should be backannotated from post-PnR results -->
</direct>
<direct name="direct_fle3i" input="clb.I3i" output="fle[3:3].in[3]">
<!-- TODO: Timing should be backannotated from post-PnR results -->
</direct>
<direct name="direct_fle4" input="clb.I4" output="fle[4:4].in[0:2]">
<direct name="direct_fle4" input="clb.I4[0:2]" output="fle[4:4].in[0:2]">
<!-- TODO: Timing should be backannotated from post-PnR results -->
</direct>
<direct name="direct_fle4i" input="clb.I4i" output="fle[4:4].in[3]">
<!-- TODO: Timing should be backannotated from post-PnR results -->
</direct>
<direct name="direct_fle5" input="clb.I5" output="fle[5:5].in[0:2]">
<direct name="direct_fle5" input="clb.I5[0:2]" output="fle[5:5].in[0:2]">
<!-- TODO: Timing should be backannotated from post-PnR results -->
</direct>
<direct name="direct_fle5i" input="clb.I5i" output="fle[5:5].in[3]">
<!-- TODO: Timing should be backannotated from post-PnR results -->
</direct>
<direct name="direct_fle6" input="clb.I6" output="fle[6:6].in[0:2]">
<direct name="direct_fle6" input="clb.I6[0:2]" output="fle[6:6].in[0:2]">
<!-- TODO: Timing should be backannotated from post-PnR results -->
</direct>
<direct name="direct_fle6i" input="clb.I6i" output="fle[6:6].in[3]">
<!-- TODO: Timing should be backannotated from post-PnR results -->
</direct>
<direct name="direct_fle7" input="clb.I7" output="fle[7:7].in[0:2]">
<direct name="direct_fle7" input="clb.I7[0:2]" output="fle[7:7].in[0:2]">
<!-- TODO: Timing should be backannotated from post-PnR results -->
</direct>
<direct name="direct_fle7i" input="clb.I7i" output="fle[7:7].in[3]">

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32
FPGA22_HIER_SKY_PNR/fpga_core/rpts_icc2/module_utilization.tsv
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@ -1,18 +1,18 @@
| Module | Util| Area| Sites| Insts| Std_Cells
|--------------------|----------|-----------------|-------|-------|-------
| sb_0__0_ | 27.75 | 9068.697600 | 7248 | 1 | 95
| sb_0__1_ | 51.68 | 9809.408000 | 7840 | 1 | 138
| sb_0__2_ | 31.95 | 9068.697600 | 7248 | 1 | 96
| sb_1__0_ | 46.31 | 11471.001600 | 9168 | 1 | 150
| sb_1__1_ | 66.68 | 12211.712000 | 9760 | 1 | 185
| sb_1__2_ | 48.12 | 11471.001600 | 9168 | 1 | 140
| sb_2__0_ | 40.31 | 9068.697600 | 7248 | 1 | 107
| sb_2__1_ | 60.96 | 9809.408000 | 7840 | 1 | 151
| sb_2__2_ | 41.16 | 9068.697600 | 7248 | 1 | 89
| cbx_1__0_ | 54.01 | 5925.683200 | 4736 | 2 | 140
| cbx_1__1_ | 74.16 | 5925.683200 | 4736 | 2 | 112
| cbx_1__2_ | 76.12 | 5925.683200 | 4736 | 2 | 104
| cby_0__1_ | 29.85 | 5184.972800 | 4144 | 2 | 106
| cby_1__1_ | 79.92 | 5184.972800 | 4144 | 2 | 95
| cby_2__1_ | 80.91 | 5184.972800 | 4144 | 2 | 87
| grid_clb_1__1_ | 76.73 | 12071.577600 | 9648 | 4 | 52
| sb_0__0_ | 24.99 | 8728.371200 | 6976 | 1 | 78
| sb_0__1_ | 48.87 | 9449.062400 | 7552 | 1 | 127
| sb_0__2_ | 29.93 | 8728.371200 | 6976 | 1 | 88
| sb_1__0_ | 44.23 | 10970.521600 | 8768 | 1 | 135
| sb_1__1_ | 65.73 | 11691.212800 | 9344 | 1 | 181
| sb_1__2_ | 47.88 | 10970.521600 | 8768 | 1 | 145
| sb_2__0_ | 36.31 | 8728.371200 | 6976 | 1 | 95
| sb_2__1_ | 58.37 | 9449.062400 | 7552 | 1 | 146
| sb_2__2_ | 39.94 | 8728.371200 | 6976 | 1 | 89
| cbx_1__0_ | 56.73 | 5765.529600 | 4608 | 2 | 151
| cbx_1__1_ | 71.12 | 5765.529600 | 4608 | 2 | 110
| cbx_1__2_ | 74.91 | 5765.529600 | 4608 | 2 | 111
| cby_0__1_ | 29.89 | 5044.838400 | 4032 | 2 | 103
| cby_1__1_ | 78.17 | 5044.838400 | 4032 | 2 | 96
| cby_2__1_ | 80.56 | 5044.838400 | 4032 | 2 | 88
| grid_clb_1__1_ | 75.92 | 11531.059200 | 9216 | 4 | 58

1 | Module | Util| Area| Sites| Insts| Std_Cells
2 |--------------------|----------|-----------------|-------|-------|-------
3 | sb_0__0_ | 27.75 | 9068.697600 | 7248 | 1 | 95 | sb_0__0_ | 24.99 | 8728.371200 | 6976 | 1 | 78
4 | sb_0__1_ | 51.68 | 9809.408000 | 7840 | 1 | 138 | sb_0__1_ | 48.87 | 9449.062400 | 7552 | 1 | 127
5 | sb_0__2_ | 31.95 | 9068.697600 | 7248 | 1 | 96 | sb_0__2_ | 29.93 | 8728.371200 | 6976 | 1 | 88
6 | sb_1__0_ | 46.31 | 11471.001600 | 9168 | 1 | 150 | sb_1__0_ | 44.23 | 10970.521600 | 8768 | 1 | 135
7 | sb_1__1_ | 66.68 | 12211.712000 | 9760 | 1 | 185 | sb_1__1_ | 65.73 | 11691.212800 | 9344 | 1 | 181
8 | sb_1__2_ | 48.12 | 11471.001600 | 9168 | 1 | 140 | sb_1__2_ | 47.88 | 10970.521600 | 8768 | 1 | 145
9 | sb_2__0_ | 40.31 | 9068.697600 | 7248 | 1 | 107 | sb_2__0_ | 36.31 | 8728.371200 | 6976 | 1 | 95
10 | sb_2__1_ | 60.96 | 9809.408000 | 7840 | 1 | 151 | sb_2__1_ | 58.37 | 9449.062400 | 7552 | 1 | 146
11 | sb_2__2_ | 41.16 | 9068.697600 | 7248 | 1 | 89 | sb_2__2_ | 39.94 | 8728.371200 | 6976 | 1 | 89
12 | cbx_1__0_ | 54.01 | 5925.683200 | 4736 | 2 | 140 | cbx_1__0_ | 56.73 | 5765.529600 | 4608 | 2 | 151
13 | cbx_1__1_ | 74.16 | 5925.683200 | 4736 | 2 | 112 | cbx_1__1_ | 71.12 | 5765.529600 | 4608 | 2 | 110
14 | cbx_1__2_ | 76.12 | 5925.683200 | 4736 | 2 | 104 | cbx_1__2_ | 74.91 | 5765.529600 | 4608 | 2 | 111
15 | cby_0__1_ | 29.85 | 5184.972800 | 4144 | 2 | 106 | cby_0__1_ | 29.89 | 5044.838400 | 4032 | 2 | 103
16 | cby_1__1_ | 79.92 | 5184.972800 | 4144 | 2 | 95 | cby_1__1_ | 78.17 | 5044.838400 | 4032 | 2 | 96
17 | cby_2__1_ | 80.91 | 5184.972800 | 4144 | 2 | 87 | cby_2__1_ | 80.56 | 5044.838400 | 4032 | 2 | 88
18 | grid_clb_1__1_ | 76.73 | 12071.577600 | 9648 | 4 | 52 | grid_clb_1__1_ | 75.92 | 11531.059200 | 9216 | 4 | 58

49
FPGA22_HIER_SKY_PNR/fpga_core/rpts_icc2/std_cell_utilization.tsv
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@ -1,31 +1,32 @@
Ref Name Total Area Utilization_% Instance Count
----------------------------------------------------------------------------------------------------
sky130_fd_sc_hd__mux2_1 33410.793600 6.86 2967
sky130_fd_sc_hd__dfxbp_1 31285.004800 6.43 1316
sky130_fd_sc_hd__dlymetal6s2s_1 9258.880000 1.90 740
sky130_fd_sc_hd__dlymetal6s6s_1 9071.200000 1.86 725
sky130_fd_sc_hd__dlygate4sd3_1 5695.462400 1.17 569
sky130_fd_sc_hd__buf_4 2552.448000 0.52 340
sky130_fd_sc_hd__dlygate4sd2_1 1769.196800 0.36 202
sky130_fd_sc_hd__mux2_1 32960.361600 6.77 2927
sky130_fd_sc_hd__dfxtp_1 25584.537600 5.25 1278
sky130_fd_sc_hd__dlymetal6s2s_1 9484.096000 1.95 758
sky130_fd_sc_hd__dlymetal6s6s_1 8896.032000 1.83 711
sky130_fd_sc_hd__dlygate4sd3_1 6205.952000 1.27 620
sky130_fd_sc_hd__buf_4 2695.084800 0.55 359
sky130_fd_sc_hd__dlygate4sd2_1 1891.814400 0.39 216
sky130_fd_sc_hd__sdfxtp_1 1681.612800 0.35 64
sky130_fd_sc_hd__mux2_8 1208.659200 0.25 46
sky130_fd_sc_hd__dlygate4sd1_1 613.088000 0.13 70
sky130_fd_sc_hd__buf_2 375.360000 0.08 75
sky130_fd_sc_hd__inv_1 375.360000 0.08 100
sky130_fd_sc_hd__conb_1 326.563200 0.07 87
sky130_fd_sc_hd__mux2_8 814.531200 0.17 31
sky130_fd_sc_hd__inv_1 390.374400 0.08 104
sky130_fd_sc_hd__conb_1 330.316800 0.07 88
sky130_fd_sc_hd__dlygate4sd1_1 289.027200 0.06 33
sky130_fd_sc_hd__buf_6 202.694400 0.04 18
sky130_fd_sc_hd__or2_0 200.192000 0.04 32
sky130_fd_sc_hd__buf_6 135.129600 0.03 12
sky130_fd_sc_hd__buf_2 180.172800 0.04 36
sky130_fd_sc_hd__clkinv_16 90.086400 0.02 3
sky130_fd_sc_hd__buf_12 80.076800 0.02 4
sky130_fd_sc_hd__buf_8 75.072000 0.02 5
sky130_fd_sc_hd__clkbuf_1 60.057600 0.01 16
sky130_fd_sc_hd__clkinv_16 30.028800 0.01 1
sky130_fd_sc_hd__clkdlybuf4s50_2 22.521600 0.00 2
sky130_fd_sc_hd__clkinvlp_4 22.521600 0.00 3
sky130_fd_sc_hd__clkinvlp_2 20.019200 0.00 4
sky130_fd_sc_hd__clkinv_4 8.758400 0.00 1
sky130_fd_sc_hd__inv_4 6.256000 0.00 1
sky130_fd_sc_hd__clkinv_2 5.004800 0.00 1
sky130_fd_sc_hd__inv_2 3.753600 0.00 1
FPGA_BBOX_AREA 229900.4928
sky130_fd_sc_hd__clkbuf_1 41.289600 0.01 11
sky130_fd_sc_hd__mux2_4 30.028800 0.01 2
sky130_fd_sc_hd__clkinv_8 16.265600 0.00 1
sky130_fd_sc_hd__inv_2 15.014400 0.00 4
sky130_fd_sc_hd__inv_4 12.512000 0.00 2
sky130_fd_sc_hd__mux2_2 11.260800 0.00 1
sky130_fd_sc_hd__clkinv_2 10.009600 0.00 2
sky130_fd_sc_hd__inv_6 8.758400 0.00 1
sky130_fd_sc_hd__clkinvlp_2 5.004800 0.00 1
FPGA_BBOX_AREA 221972.8896
CORE_BBOX_AREA 486866.944
FPGA_BBOX_UTIL 47.2203947368
FPGA_BBOX_UTIL 45.5921052632

Can't render this file because it has a wrong number of fields in line 2.

24
FPGA22_HIER_SKY_PNR/fpga_core/rpts_icc2/timing_reports.txt
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@ -6,7 +6,7 @@ Report : clock timing
-setup
Design : fpga_core
Version: P-2019.03-SP4
Date : Sun Nov 8 18:28:15 2020
Date : Mon Nov 9 18:55:42 2020
****************************************
Information: Timer using 'PrimeTime Delay Calculation, SI, Timing Window Analysis, AWP, CRPR'. (TIM-050)
@ -16,7 +16,7 @@ Information: Timer using 'PrimeTime Delay Calculation, SI, Timing Window Analysi
--- Latency ---
Clock Pin Trans Source Offset Network Total Corner
---------------------------------------------------------------------------------------------------
grid_clb_2__2_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0/sky130_fd_sc_hd__sdfxtp_1_0_/CLK 0.162 0.000 -- 0.429 0.429 rp-+ nominal
grid_clb_2__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_1/sky130_fd_sc_hd__sdfxtp_1_0_/CLK 0.175 0.000 -- 0.370 0.370 rp-+ nominal
---------------------------------------------------------------------------------------------------
Mode: full_chip
@ -25,7 +25,7 @@ Information: Timer using 'PrimeTime Delay Calculation, SI, Timing Window Analysi
--- Latency ---
Clock Pin Trans Source Offset Network Total Corner
---------------------------------------------------------------------------------------------------
sb_0__2_/mem_right_track_0/sky130_fd_sc_hd__dfxbp_1_1_/CLK 0.347 0.000 -- 4.898 4.898 rp-+ nominal
sb_0__2_/mem_right_track_20/sky130_fd_sc_hd__dfxtp_1_0_/CLK 0.352 0.000 -- 4.373 4.373 rp-+ nominal
---------------------------------------------------------------------------------------------------
****************************************
Report : clock timing
@ -34,7 +34,7 @@ Report : clock timing
-setup
Design : fpga_core
Version: P-2019.03-SP4
Date : Sun Nov 8 18:28:15 2020
Date : Mon Nov 9 18:55:42 2020
****************************************
Information: Timer using 'PrimeTime Delay Calculation, SI, Timing Window Analysis, AWP, CRPR'. (TIM-050)
@ -43,8 +43,8 @@ Information: Timer using 'PrimeTime Delay Calculation, SI, Timing Window Analysi
Clock Pin Latency CRP Skew Corner
---------------------------------------------------------------------------------------------------
grid_clb_2__2_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_7/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_1/sky130_fd_sc_hd__sdfxtp_1_0_/CLK 0.427 rp-+ nominal
grid_clb_2__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0/sky130_fd_sc_hd__sdfxtp_1_0_/CLK 0.026 0.000 0.401 rp-+ nominal
grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_7/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_1/sky130_fd_sc_hd__sdfxtp_1_0_/CLK 0.365 rp-+ nominal
grid_clb_2__2_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0/sky130_fd_sc_hd__sdfxtp_1_0_/CLK 0.026 0.000 0.338 rp-+ nominal
---------------------------------------------------------------------------------------------------
@ -53,8 +53,8 @@ Information: Timer using 'PrimeTime Delay Calculation, SI, Timing Window Analysi
Clock Pin Latency CRP Skew Corner
---------------------------------------------------------------------------------------------------
cby_2__1_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem/sky130_fd_sc_hd__dfxbp_1_0_/CLK 3.374 rp-+ nominal
sb_2__0_/mem_top_track_0/sky130_fd_sc_hd__dfxbp_1_0_/CLK 0.949 0.000 2.424 rp-+ nominal
sb_0__2_/mem_bottom_track_25/sky130_fd_sc_hd__dfxtp_1_1_/CLK 4.370 rp-+ nominal
cby_0__2_/mem_right_ipin_0/sky130_fd_sc_hd__dfxtp_1_0_/CLK 2.387 0.000 1.983 rp-+ nominal
---------------------------------------------------------------------------------------------------
Information: Timer using 'PrimeTime Delay Calculation, SI, Timing Window Analysis, AWP, CRPR'. (TIM-050)
@ -63,7 +63,7 @@ Report : global timing
-format { narrow }
Design : fpga_core
Version: P-2019.03-SP4
Date : Sun Nov 8 18:28:15 2020
Date : Mon Nov 9 18:55:42 2020
****************************************
No setup violations found.
@ -73,9 +73,9 @@ Hold violations
--------------------------------------------------------------
Total reg->reg in->reg reg->out in->out
--------------------------------------------------------------
WNS -1.248 -1.248 0.000 0.000 0.000
TNS -1.390 -1.390 0.000 0.000 0.000
NUM 2 2 0 0 0
WNS -0.238 -0.238 0.000 0.000 0.000
TNS -0.598 -0.598 0.000 0.000 0.000
NUM 3 3 0 0 0
--------------------------------------------------------------
1

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