14 Commits

Author	SHA1	Message	Date
Tarachand Pagarani	1a4b1bc6b4	Disable generation of formal verification testbench due to disk space ... limitation on github actions. Disable testcase not fitting on 32x32 device	2021-01-05 19:44:08 -08:00
Tarachand Pagarani	1aa0ef68e4	incoporated changes based on feedback from xifan	2020-12-24 23:05:47 -08:00
Tarachand Pagarani	cfdaedcdd0	added script with random key generation example	2020-12-17 01:42:19 -08:00
tangxifan	c237500588	[Script] Remove signal initialization from testbench generator	2020-11-26 18:23:26 -07:00
tangxifan	973fe1acc8	[Script] Add signal initialization to openfpga-run scripts	2020-11-23 15:13:06 -07:00
tangxifan	a97598cef9	[Script] Patch example openfpga shell script to manage clock routing in VPR	2020-11-17 14:27:14 -07:00
tangxifan	be33082faf	[Arch] Remove out-of-data architectures	2020-11-13 09:50:45 -07:00
tangxifan	6e254356d1	[Script] Add openfpga script template using fabric key	2020-11-08 11:46:46 -07:00
tangxifan	309c63513a	[Script] Add example openfpga-run scripts using fabric key	2020-11-08 11:41:07 -07:00
tangxifan	28b56d2462	[Script] Update openfpga shell script and tasks for customized fabric netlist location	2020-10-12 14:43:50 -06:00
tangxifan	798e26e958	[Script] Add openfpga sdc generation script	2020-10-10 20:16:10 -06:00
tangxifan	3479502ab7	[Script] Update task template for testbench generation	2020-10-10 11:32:52 -06:00
tangxifan	a2b42c2e5f	[Script] Now use variables to redirect the output directory of Verilog/SDC files	2020-10-09 16:00:41 -06:00
tangxifan	64bbaf374d	[Flow] Add scripts to run OpenFPGA tasks	2020-10-09 14:49:54 -06:00