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[Script] Update task template for testbench generation

This commit is contained in:
tangxifan 2020-10-10 11:32:52 -06:00
parent abe56ce2c2
commit 3479502ab7
3 changed files with 40 additions and 4 deletions
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6
SCRIPT/openfpga_shell_script/skywater_generate_testbench_example_script.openfpga
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@ -53,15 +53,15 @@ write_fabric_bitstream --file fabric_bitstream.xml --format xml
# - Enable top-level testbench which is a full verification including programming circuit and core logic of FPGA
# - Enable pre-configured top-level testbench which is a fast verification skipping programming phase
# - Simulation ini file is optional and is needed only when you need to interface different HDL simulators using openfpga flow-run scripts
write_verilog_testbench --file ./SRC \
write_verilog_testbench --file ${OPENFPGA_VERILOG_OUTPUT_DIR}/verilog_testbench \
--reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} \
--print_top_testbench \
--print_preconfig_top_testbench \
--print_simulation_ini ./SimulationDeck/simulation_deck.ini \
--print_simulation_ini ${OPENFPGA_VERILOG_OUTPUT_DIR}/SimulationDeck/simulation_deck.ini \
--explicit_port_mapping
# Write the SDC to run timing analysis for a mapped FPGA fabric
write_analysis_sdc --file ./SDC_analysis
write_analysis_sdc --file ${OPENFPGA_VERILOG_OUTPUT_DIR}/sdc_analysis
# Finish and exit OpenFPGA
exit

2
SCRIPT/skywater_openfpga_task/k4_cc_fdms_2x2/generate_fabric/config/task_template.conf
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@ -25,7 +25,7 @@ openfpga_verilog_output_dir=${SKYWATER_OPENFPGA_HOME}/HDL/k4_FPGA_2x2_fdms_cc
openfpga_sdc_output_dir=${SKYWATER_OPENFPGA_HOME}/SDC/k4_FPGA_2x2_fdms_cc
[ARCHITECTURES]
arch0=${SKYWATER_OPENFPGA_HOME}/ARCH/openfpga_flow/vpr_arch/k4_frac_N8_tileable_adder_register_scan_chain_nonLR_skywater130nm.xml
arch0=${SKYWATER_OPENFPGA_HOME}/ARCH/vpr_arch/k4_frac_N8_tileable_adder_register_scan_chain_nonLR_skywater130nm.xml
[BENCHMARKS]
bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.v

36
SCRIPT/skywater_openfpga_task/k4_cc_fdms_2x2/generate_testbench/config/task_template.conf Normal file
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@ -0,0 +1,36 @@
# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
# Configuration file for running experiments
# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
# timeout_each_job : FPGA Task script splits fpga flow into multiple jobs
# Each job execute fpga_flow script on combination of architecture & benchmark
# timeout_each_job is timeout for each job
# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
[GENERAL]
run_engine=openfpga_shell
power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml
power_analysis = true
spice_output=false
verilog_output=true
timeout_each_job = 1*60
fpga_flow=yosys_vpr
[OpenFPGA_SHELL]
openfpga_shell_template=${SKYWATER_OPENFPGA_HOME}/SCRIPT/openfpga_shell_script/skywater_generate_testbenech_example_script.openfpga
openfpga_arch_file=${SKYWATER_OPENFPGA_HOME}/ARCH/openfpga_arch/k4_frac_N8_adder_register_scan_chain_skywater130nm_fdms_cc_openfpga.xml
openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml
openfpga_vpr_device_layout=2x2
openfpga_vpr_route_chan_width=40
openfpga_verilog_output_dir=${SKYWATER_OPENFPGA_HOME}/TESTBENCH/k4_FPGA_2x2_fdms_cc
[ARCHITECTURES]
arch0=${SKYWATER_OPENFPGA_HOME}/ARCH/vpr_arch/k4_frac_N8_tileable_adder_register_scan_chain_nonLR_skywater130nm.xml
[BENCHMARKS]
bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.v
[SYNTHESIS_PARAM]
bench0_top = and2
[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH]
#end_flow_with_test=