From 3479502ab743fffaedc3df5a141bde838f1e71fe Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Sat, 10 Oct 2020 11:32:52 -0600
Subject: [PATCH] [Script] Update task template for testbench generation

---
 ...generate_testbench_example_script.openfpga |  6 ++--
 .../generate_fabric/config/task_template.conf |  2 +-
 .../config/task_template.conf                 | 36 +++++++++++++++++++
 3 files changed, 40 insertions(+), 4 deletions(-)
 create mode 100644 SCRIPT/skywater_openfpga_task/k4_cc_fdms_2x2/generate_testbench/config/task_template.conf

diff --git a/SCRIPT/openfpga_shell_script/skywater_generate_testbench_example_script.openfpga b/SCRIPT/openfpga_shell_script/skywater_generate_testbench_example_script.openfpga
index 46d6163..8b7f99a 100644
--- a/SCRIPT/openfpga_shell_script/skywater_generate_testbench_example_script.openfpga
+++ b/SCRIPT/openfpga_shell_script/skywater_generate_testbench_example_script.openfpga
@@ -53,15 +53,15 @@ write_fabric_bitstream --file fabric_bitstream.xml --format xml
 #  - Enable top-level testbench which is a full verification including programming circuit and core logic of FPGA
 #  - Enable pre-configured top-level testbench which is a fast verification skipping programming phase
 #  - Simulation ini file is optional and is needed only when you need to interface different HDL simulators using openfpga flow-run scripts
-write_verilog_testbench --file ./SRC \
+write_verilog_testbench --file ${OPENFPGA_VERILOG_OUTPUT_DIR}/verilog_testbench \
   --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} \
   --print_top_testbench \
   --print_preconfig_top_testbench \
-  --print_simulation_ini ./SimulationDeck/simulation_deck.ini \
+  --print_simulation_ini ${OPENFPGA_VERILOG_OUTPUT_DIR}/SimulationDeck/simulation_deck.ini \
   --explicit_port_mapping
 
 # Write the SDC to run timing analysis for a mapped FPGA fabric
-write_analysis_sdc --file ./SDC_analysis
+write_analysis_sdc --file ${OPENFPGA_VERILOG_OUTPUT_DIR}/sdc_analysis
 
 # Finish and exit OpenFPGA
 exit
diff --git a/SCRIPT/skywater_openfpga_task/k4_cc_fdms_2x2/generate_fabric/config/task_template.conf b/SCRIPT/skywater_openfpga_task/k4_cc_fdms_2x2/generate_fabric/config/task_template.conf
index 73ff84d..292f8a2 100644
--- a/SCRIPT/skywater_openfpga_task/k4_cc_fdms_2x2/generate_fabric/config/task_template.conf
+++ b/SCRIPT/skywater_openfpga_task/k4_cc_fdms_2x2/generate_fabric/config/task_template.conf
@@ -25,7 +25,7 @@ openfpga_verilog_output_dir=${SKYWATER_OPENFPGA_HOME}/HDL/k4_FPGA_2x2_fdms_cc
 openfpga_sdc_output_dir=${SKYWATER_OPENFPGA_HOME}/SDC/k4_FPGA_2x2_fdms_cc
 
 [ARCHITECTURES]
-arch0=${SKYWATER_OPENFPGA_HOME}/ARCH/openfpga_flow/vpr_arch/k4_frac_N8_tileable_adder_register_scan_chain_nonLR_skywater130nm.xml
+arch0=${SKYWATER_OPENFPGA_HOME}/ARCH/vpr_arch/k4_frac_N8_tileable_adder_register_scan_chain_nonLR_skywater130nm.xml
 
 [BENCHMARKS]
 bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.v
diff --git a/SCRIPT/skywater_openfpga_task/k4_cc_fdms_2x2/generate_testbench/config/task_template.conf b/SCRIPT/skywater_openfpga_task/k4_cc_fdms_2x2/generate_testbench/config/task_template.conf
new file mode 100644
index 0000000..a9774d0
--- /dev/null
+++ b/SCRIPT/skywater_openfpga_task/k4_cc_fdms_2x2/generate_testbench/config/task_template.conf
@@ -0,0 +1,36 @@
+# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
+# Configuration file for running experiments
+# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
+# timeout_each_job : FPGA Task script splits fpga flow into multiple jobs
+# Each job execute fpga_flow script on combination of architecture & benchmark
+# timeout_each_job is timeout for each job
+# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
+
+[GENERAL]
+run_engine=openfpga_shell
+power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml
+power_analysis = true
+spice_output=false
+verilog_output=true
+timeout_each_job = 1*60
+fpga_flow=yosys_vpr
+
+[OpenFPGA_SHELL]
+openfpga_shell_template=${SKYWATER_OPENFPGA_HOME}/SCRIPT/openfpga_shell_script/skywater_generate_testbenech_example_script.openfpga
+openfpga_arch_file=${SKYWATER_OPENFPGA_HOME}/ARCH/openfpga_arch/k4_frac_N8_adder_register_scan_chain_skywater130nm_fdms_cc_openfpga.xml
+openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml
+openfpga_vpr_device_layout=2x2
+openfpga_vpr_route_chan_width=40
+openfpga_verilog_output_dir=${SKYWATER_OPENFPGA_HOME}/TESTBENCH/k4_FPGA_2x2_fdms_cc
+
+[ARCHITECTURES]
+arch0=${SKYWATER_OPENFPGA_HOME}/ARCH/vpr_arch/k4_frac_N8_tileable_adder_register_scan_chain_nonLR_skywater130nm.xml
+
+[BENCHMARKS]
+bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.v
+
+[SYNTHESIS_PARAM]
+bench0_top = and2
+
+[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH]
+#end_flow_with_test=