7 Commits

Author	SHA1	Message	Date
Ganesh Gore	0cc5b492d2	[Cleanup] Removed/Ignored testbench files from generated source	2020-12-02 12:03:24 -07:00
Ganesh Gore	7dd7e33cb6	Change configuration flipflop + Fixed configuration chain	2020-11-09 19:17:15 -07:00
Ganesh Gore	015c67e10f	Added clock feedthroughs	2020-11-08 18:37:55 -07:00
Ganesh Gore	229b8e22b4	Fixed scan-chain connections	2020-11-08 01:06:13 -07:00
Ganesh Gore	31a73a42ba	Updated design with new architecure and merged grid_io	2020-11-06 22:35:31 -07:00
Ganesh Gore	72ff141046	[DESIGN] Updated FPGA22 Design ... + Utilization increased to 60% + Added track offset + Added Power ring + Added Tapcells + Added additional reports and screenshot to track improvements	2020-10-27 14:54:19 -06:00
Ganesh Gore	8b22960ddc	[Design] Added FPGA22 design with SKY130_FD_SC_HD	2020-10-26 23:59:20 -06:00