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444 Commits

Author SHA1 Message Date
tangxifan 3cc54ccb59 [MSIM] Bug fix 2020-12-08 10:15:39 -07:00
tangxifan 4247819ccb Merge branch 'xt_dev' of https://github.com/LNIS-Projects/skywater-openfpga into xt_dev 2020-12-08 10:13:33 -07:00
tangxifan 55ff90905f [DC] Add scripts to automate the synthesis for local encoders 2020-12-08 10:12:57 -07:00
tangxifan 77dfb469b5
Update MSIM/common/run_post_pnr_msim_task.py 
Co-authored-by: Ashton Snelgrove <ashton.snelgrove@utah.edu>
 2020-12-07 17:41:22 -07:00
tangxifan 7f9c8e2e90 [Doc] Add Readme for design compiler workspace 2020-12-07 17:40:08 -07:00
tangxifan 2f741ecc15 [MSIM] Now modelsim verification is multithreaded 2020-12-07 15:25:48 -07:00
Laboratory for Nano Integrated Systems (LNIS) 67e0c94c66
Merge pull request #58 from lnis-uofu/xt_dev 
Scripts for Verifications on Custom Cell -based FPGA (SOFA CHD)
 2020-12-07 09:45:43 -07:00
tangxifan fd074254e9
Merge pull request #57 from lnis-uofu/ganesh_dev 
Added Caravel merge and precheck in action + Updated SOFA-HD and QLSOFA-HD gds
 2020-12-07 09:07:30 -07:00
Ganesh Gore 7967d1da1f [Bugfix] Solved merge conflict 2020-12-06 23:13:59 -07:00
Ganesh Gore 5474ff53c5 [Fixup] Merge conflict with master 2020-12-06 21:41:06 -07:00
Ganesh Gore b90ee124a3 Resolves merge conflict with master 2020-12-06 21:35:34 -07:00
Ganesh Gore b0098ed4b9 Merge remote-tracking branch 'origin/master' into ganesh_dev 2020-12-06 21:29:06 -07:00
Ganesh Gore 5679ee0cb4 [QLSOFA-HD] Fixed reset signal short/GDS precision to 1000 2020-12-06 20:47:52 -07:00
Ganesh Gore 12ffaed8fa [QLSOFA-HD] Added screenshots for top level PnR 2020-12-06 20:45:31 -07:00
tangxifan 7f53e0ef18 [HDL] Add HDL for custom cells 2020-12-06 14:15:03 -07:00
tangxifan aa90424ada [HDL] Add primitive include lines for digital I/O built with HD cells 2020-12-06 11:35:35 -07:00
tangxifan 21a4928002 [HDL] Bug fix in custom cell code generator 2020-12-06 11:28:37 -07:00
tangxifan da08e505b5 [MSIM] Support pre-pnr simulation in script-run verification 2020-12-06 11:13:50 -07:00
Ganesh Gore 328594d8c5 [Action] Clean up action scripts 2020-12-06 01:53:21 -07:00
Ganesh Gore 9322afadad [Action] Added 30 min timeout ticker 2020-12-06 01:42:07 -07:00
Ganesh Gore ea7e2b248b [Action] Testing Docker action 2020-12-06 01:41:58 -07:00
Ganesh Gore 10cab93799 [Action] Integrated MPW prechecker 2020-12-06 01:41:58 -07:00
Ganesh Gore 40c131983a [FPGA1212_v1] Changed gds precision to 1000 2020-12-06 01:41:58 -07:00
Ganesh Gore 6af001df11 Added SynRepoConfig is paths 2020-12-06 01:41:58 -07:00
Ganesh Gore 2bada6124f [Action] Changed Docker workdir 2020-12-06 01:41:46 -07:00
Ganesh Gore cfa2bb96c4 [Action] Removed nojekyll file addition 2020-12-06 01:41:46 -07:00
Ganesh Gore 51cd5d6630 [Action] Added Docker itegration 2020-12-06 01:41:36 -07:00
Ganesh Gore 60060762e5 [Action] Replaced destination repo url 2020-12-06 01:41:00 -07:00
Ganesh Gore 2ecc166e95 [Action] Added destination repo push action 2020-12-06 01:40:38 -07:00
Ganesh Gore 8105a46f07 [Actions] Alternate option to modify file 2020-12-06 01:40:21 -07:00
Ganesh Gore d63dfa00b7 [Actions] filename bugfix 2020-12-06 01:40:21 -07:00
Ganesh Gore 027f0f76a2 [bugfix] Indentation bug in actions yaml 2020-12-06 01:40:21 -07:00
Ganesh Gore 41f2844698 [Action] And modify file and push action 2020-12-06 01:40:21 -07:00
Ganesh Gore 62e0cffea1 [Actions] Disables build test in ganesh_dev branch 2020-12-06 01:40:21 -07:00
Ganesh Gore d5a5ec5b1d [Actions] Testing repository fetch option 2020-12-06 01:40:21 -07:00
Ganesh Gore 452af85e98 [Cleanup] Removed/Ignored testbench files from generated source 2020-12-06 01:40:21 -07:00
tangxifan f5c1d9c0a0 [Arch] enable local encoders 2020-12-06 01:40:21 -07:00
tangxifan ad120e205b [CI] Add new arch to CI test 2020-12-06 01:40:21 -07:00
tangxifan 004f9dbcca [Arch] Bug fix in new arch 2020-12-06 01:40:21 -07:00
tangxifan c015d65a03 [Script] Add task run for custom cell FPGA architectures 2020-12-06 01:40:21 -07:00
tangxifan 4ddc6955a3 [Arch] Add architecture using custom cells 2020-12-06 01:40:21 -07:00
tangxifan 22451870dd [CI] Patch github repo path to sync with OpenFPGA repo movement 2020-12-06 01:39:16 -07:00
tangxifan 87f79d78bb [CI] Add wrapper generator examples to CI 2020-12-06 01:39:16 -07:00
tangxifan 696529b43d [Script] Increase routing chan width from 40 to 60 for version 1.2 2020-12-06 01:39:16 -07:00
Laboratory for Nano Integrated Systems (LNIS) f572be8fc2
Merge pull request #56 from lnis-uofu/xt_dev 
Python script to adapt OpenFPGA netlist to use custom MUX cells
 2020-12-05 22:11:36 -07:00
tangxifan 443eb12710 [CI] Add test to CI 2020-12-05 21:17:59 -07:00
tangxifan 22f2b3aa90 [HDL] Add python script to adapt OpenFPGA MUX primitives to use custom cells 2020-12-05 21:14:56 -07:00
tangxifan 6039ae92ca [Arch] Bug fix for buffering two-level routing multiplexers using custom cells 2020-12-05 19:37:34 -07:00
Laboratory for Nano Integrated Systems (LNIS) 52413059f6
Merge pull request #55 from lnis-uofu/xt_dev 
Major Changes in Documentation
 2020-12-04 14:47:52 -07:00
tangxifan 3a75e079ba [Doc] Update the frontpage README 2020-12-04 14:09:40 -07:00