riscv
/
SOFA
mirror of https://github.com/lnis-uofu/SOFA.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity

Added sofa fpga lite design

This commit is contained in:
Ganesh Gore 2023-02-19 10:58:24 -07:00
parent e508bdd905
commit f5ff147ddb
62 changed files with 23716 additions and 3 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

12
SCRIPT/openfpga_shell_script/fix_heterogeneous_device_routeW_example_script.openfpga
View File

@ -1,6 +1,12 @@
# Run VPR for the 'and' design # This script is designed to generate fabric Verilog netlists
#--write_rr_graph example_rr_graph.xml # with a fixed device layout
vpr ${VPR_ARCH_FILE} ${VPR_TESTBENCH_BLIF} --device ${OPENFPGA_VPR_DEVICE_LAYOUT} --route_chan_width ${OPENFPGA_VPR_ROUTE_CHAN_WIDTH} --constant_net_method route # It will only output netlists to be used by backend tools,
# i.e., Synopsys ICC2, including
# - Verilog netlists
# - fabric hierarchy description for ICC2's hierarchical flow
# - Timing/Design constraints
vpr ${VPR_ARCH_FILE} ${VPR_TESTBENCH_BLIF} --device ${OPENFPGA_VPR_DEVICE_LAYOUT} --route_chan_width ${OPENFPGA_VPR_ROUTE_CHAN_WIDTH} --constant_net_method route --absorb_buffer_luts off --clock_modeling ideal
# Read OpenFPGA architecture definition # Read OpenFPGA architecture definition
read_openfpga_arch -f ${OPENFPGA_ARCH_FILE} read_openfpga_arch -f ${OPENFPGA_ARCH_FILE}

51
SOFA_A/Makefile Normal file
View File

@ -0,0 +1,51 @@
##########################################################################################
##########################################################################################
SHELL=bash
PYTHON_EXEC=python3.8
RERUN = 0
PROJ_NAME=SOFA_A
TB = top
OPTIONS =
.SILENT:
.ONESHELL:
.PHONY: runOpenFPGA
generate_netlist:
echo "Generating OpenFPGA netlist"
source $${OPENFPGA_PATH}/openfpga.sh
cp ${PROJ_NAME}_task/config/task_generation.conf ${PROJ_NAME}_task/config/task.conf
rerun-task ${PROJ_NAME}_task
mkdir -p ${PROJ_NAME}_verilog
cp -r ${PROJ_NAME}_task/latest/*/*/*/SRC/* ${PROJ_NAME}_verilog
runOpenFPGA:
SECONDS=0
source config.sh
# ===================== Check Tools =====================
which python3.8 > /dev/null
if [ $$? -eq 1 ]; then
echo "xxxxxxxx Python version 3.8 is required xxxxxxxx"; exit;
fi
# =================== Clean Previous Run =================================
rm -f $${OPENFPGA_PATH}/openfpga_flow/tasks/$${TASK_DIR_NAME}
(cd ./$${TASK_DIR_NAME}/config && rm -f task.conf && cp task_simulation.conf task.conf)
# ===================== Generate Netlist =================================
(currDir=$${PWD} && cd $$OPENFPGA_PATH && source openfpga.sh && cd $$currDir &&
run-task $${TASK_DIR_NAME} --remove_run_dir all
run-task $${TASK_DIR_NAME} ${OPTIONS})
if [ $$? -eq 1 ]; then
echo "X X X X X X Failed to generate netlist X X X X X X"; exit;
fi
duration=$$SECONDS
date > runOpenFPGA
echo "$$(($$duration / 60)) minutes and $$(($$duration % 60)) seconds elapsed." >> runOpenFPGA
clean:
rm -rf runOpenFPGA

2
SOFA_A/README.md Normal file
View File

@ -0,0 +1,2 @@
SOFA-A
======

1
SOFA_A/SOFA_A_task/BENCHMARK Symbolic link
View File

@ -0,0 +1 @@
../../BENCHMARK

678
SOFA_A/SOFA_A_task/arch/fabric_key.xml Normal file
View File

@ -0,0 +1,678 @@
<?xml version="1.0" ?>
<fabric_key>
<region id="0">
<key id="0" alias="sb_12__12_"/>
<key id="1" alias="cbx_12__12_"/>
<key id="2" alias="grid_io_top_top_12__13_"/>
<key id="3" alias="sb_11__12_"/>
<key id="4" alias="cbx_11__12_"/>
<key id="5" alias="grid_io_top_top_11__13_"/>
<key id="6" alias="sb_10__12_"/>
<key id="7" alias="cbx_10__12_"/>
<key id="8" alias="grid_io_top_top_10__13_"/>
<key id="9" alias="sb_9__12_"/>
<key id="10" alias="cbx_9__12_"/>
<key id="11" alias="grid_io_top_top_9__13_"/>
<key id="12" alias="sb_8__12_"/>
<key id="13" alias="cbx_8__12_"/>
<key id="14" alias="grid_io_top_top_8__13_"/>
<key id="15" alias="sb_7__12_"/>
<key id="16" alias="cbx_7__12_"/>
<key id="17" alias="grid_io_top_top_7__13_"/>
<key id="18" alias="sb_6__12_"/>
<key id="19" alias="cbx_6__12_"/>
<key id="20" alias="grid_io_top_top_6__13_"/>
<key id="21" alias="sb_5__12_"/>
<key id="22" alias="cbx_5__12_"/>
<key id="23" alias="grid_io_top_top_5__13_"/>
<key id="24" alias="sb_4__12_"/>
<key id="25" alias="cbx_4__12_"/>
<key id="26" alias="grid_io_top_top_4__13_"/>
<key id="27" alias="sb_3__12_"/>
<key id="28" alias="cbx_3__12_"/>
<key id="29" alias="grid_io_top_top_3__13_"/>
<key id="30" alias="sb_2__12_"/>
<key id="31" alias="cbx_2__12_"/>
<key id="32" alias="grid_io_top_top_2__13_"/>
<key id="33" alias="sb_1__12_"/>
<key id="34" alias="cbx_1__12_"/>
<key id="35" alias="grid_io_top_top_1__13_"/>
<key id="36" alias="sb_0__12_"/>
<key id="37" alias="cby_0__12_"/>
<key id="38" alias="grid_io_left_left_0__12_"/>
<key id="39" alias="grid_clb_1__12_"/>
<key id="40" alias="cby_1__12_"/>
<key id="41" alias="grid_clb_2__12_"/>
<key id="42" alias="cby_2__12_"/>
<key id="43" alias="grid_clb_3__12_"/>
<key id="44" alias="cby_3__12_"/>
<key id="45" alias="grid_clb_4__12_"/>
<key id="46" alias="cby_4__12_"/>
<key id="47" alias="grid_clb_5__12_"/>
<key id="48" alias="cby_5__12_"/>
<key id="49" alias="grid_clb_6__12_"/>
<key id="50" alias="cby_6__12_"/>
<key id="51" alias="grid_clb_7__12_"/>
<key id="52" alias="cby_7__12_"/>
<key id="53" alias="grid_clb_8__12_"/>
<key id="54" alias="cby_8__12_"/>
<key id="55" alias="grid_clb_9__12_"/>
<key id="56" alias="cby_9__12_"/>
<key id="57" alias="grid_clb_10__12_"/>
<key id="58" alias="cby_10__12_"/>
<key id="59" alias="grid_clb_11__12_"/>
<key id="60" alias="cby_11__12_"/>
<key id="61" alias="grid_clb_12__12_"/>
<key id="62" alias="cby_12__12_"/>
<key id="63" alias="grid_io_right_right_13__12_"/>
<key id="64" alias="sb_12__11_"/>
<key id="65" alias="cbx_12__11_"/>
<key id="66" alias="sb_11__11_"/>
<key id="67" alias="cbx_11__11_"/>
<key id="68" alias="sb_10__11_"/>
<key id="69" alias="cbx_10__11_"/>
<key id="70" alias="sb_9__11_"/>
<key id="71" alias="cbx_9__11_"/>
<key id="72" alias="sb_8__11_"/>
<key id="73" alias="cbx_8__11_"/>
<key id="74" alias="sb_7__11_"/>
<key id="75" alias="cbx_7__11_"/>
<key id="76" alias="sb_6__11_"/>
<key id="77" alias="cbx_6__11_"/>
<key id="78" alias="sb_5__11_"/>
<key id="79" alias="cbx_5__11_"/>
<key id="80" alias="sb_4__11_"/>
<key id="81" alias="cbx_4__11_"/>
<key id="82" alias="sb_3__11_"/>
<key id="83" alias="cbx_3__11_"/>
<key id="84" alias="sb_2__11_"/>
<key id="85" alias="cbx_2__11_"/>
<key id="86" alias="sb_1__11_"/>
<key id="87" alias="cbx_1__11_"/>
<key id="88" alias="sb_0__11_"/>
<key id="89" alias="cby_0__11_"/>
<key id="90" alias="grid_io_left_left_0__11_"/>
<key id="91" alias="grid_clb_1__11_"/>
<key id="92" alias="cby_1__11_"/>
<key id="93" alias="grid_clb_2__11_"/>
<key id="94" alias="cby_2__11_"/>
<key id="95" alias="grid_clb_3__11_"/>
<key id="96" alias="cby_3__11_"/>
<key id="97" alias="grid_clb_4__11_"/>
<key id="98" alias="cby_4__11_"/>
<key id="99" alias="grid_clb_5__11_"/>
<key id="100" alias="cby_5__11_"/>
<key id="101" alias="grid_clb_6__11_"/>
<key id="102" alias="cby_6__11_"/>
<key id="103" alias="grid_clb_7__11_"/>
<key id="104" alias="cby_7__11_"/>
<key id="105" alias="grid_clb_8__11_"/>
<key id="106" alias="cby_8__11_"/>
<key id="107" alias="grid_clb_9__11_"/>
<key id="108" alias="cby_9__11_"/>
<key id="109" alias="grid_clb_10__11_"/>
<key id="110" alias="cby_10__11_"/>
<key id="111" alias="grid_clb_11__11_"/>
<key id="112" alias="cby_11__11_"/>
<key id="113" alias="grid_clb_12__11_"/>
<key id="114" alias="cby_12__11_"/>
<key id="115" alias="grid_io_right_right_13__11_"/>
<key id="116" alias="sb_12__10_"/>
<key id="117" alias="cbx_12__10_"/>
<key id="118" alias="sb_11__10_"/>
<key id="119" alias="cbx_11__10_"/>
<key id="120" alias="sb_10__10_"/>
<key id="121" alias="cbx_10__10_"/>
<key id="122" alias="sb_9__10_"/>
<key id="123" alias="cbx_9__10_"/>
<key id="124" alias="sb_8__10_"/>
<key id="125" alias="cbx_8__10_"/>
<key id="126" alias="sb_7__10_"/>
<key id="127" alias="cbx_7__10_"/>
<key id="128" alias="sb_6__10_"/>
<key id="129" alias="cbx_6__10_"/>
<key id="130" alias="sb_5__10_"/>
<key id="131" alias="cbx_5__10_"/>
<key id="132" alias="sb_4__10_"/>
<key id="133" alias="cbx_4__10_"/>
<key id="134" alias="sb_3__10_"/>
<key id="135" alias="cbx_3__10_"/>
<key id="136" alias="sb_2__10_"/>
<key id="137" alias="cbx_2__10_"/>
<key id="138" alias="sb_1__10_"/>
<key id="139" alias="cbx_1__10_"/>
<key id="140" alias="sb_0__10_"/>
<key id="141" alias="cby_0__10_"/>
<key id="142" alias="grid_io_left_left_0__10_"/>
<key id="143" alias="grid_clb_1__10_"/>
<key id="144" alias="cby_1__10_"/>
<key id="145" alias="grid_clb_2__10_"/>
<key id="146" alias="cby_2__10_"/>
<key id="147" alias="grid_clb_3__10_"/>
<key id="148" alias="cby_3__10_"/>
<key id="149" alias="grid_clb_4__10_"/>
<key id="150" alias="cby_4__10_"/>
<key id="151" alias="grid_clb_5__10_"/>
<key id="152" alias="cby_5__10_"/>
<key id="153" alias="grid_clb_6__10_"/>
<key id="154" alias="cby_6__10_"/>
<key id="155" alias="grid_clb_7__10_"/>
<key id="156" alias="cby_7__10_"/>
<key id="157" alias="grid_clb_8__10_"/>
<key id="158" alias="cby_8__10_"/>
<key id="159" alias="grid_clb_9__10_"/>
<key id="160" alias="cby_9__10_"/>
<key id="161" alias="grid_clb_10__10_"/>
<key id="162" alias="cby_10__10_"/>
<key id="163" alias="grid_clb_11__10_"/>
<key id="164" alias="cby_11__10_"/>
<key id="165" alias="grid_clb_12__10_"/>
<key id="166" alias="cby_12__10_"/>
<key id="167" alias="grid_io_right_right_13__10_"/>
<key id="168" alias="sb_12__9_"/>
<key id="169" alias="cbx_12__9_"/>
<key id="170" alias="sb_11__9_"/>
<key id="171" alias="cbx_11__9_"/>
<key id="172" alias="sb_10__9_"/>
<key id="173" alias="cbx_10__9_"/>
<key id="174" alias="sb_9__9_"/>
<key id="175" alias="cbx_9__9_"/>
<key id="176" alias="sb_8__9_"/>
<key id="177" alias="cbx_8__9_"/>
<key id="178" alias="sb_7__9_"/>
<key id="179" alias="cbx_7__9_"/>
<key id="180" alias="sb_6__9_"/>
<key id="181" alias="cbx_6__9_"/>
<key id="182" alias="sb_5__9_"/>
<key id="183" alias="cbx_5__9_"/>
<key id="184" alias="sb_4__9_"/>
<key id="185" alias="cbx_4__9_"/>
<key id="186" alias="sb_3__9_"/>
<key id="187" alias="cbx_3__9_"/>
<key id="188" alias="sb_2__9_"/>
<key id="189" alias="cbx_2__9_"/>
<key id="190" alias="sb_1__9_"/>
<key id="191" alias="cbx_1__9_"/>
<key id="192" alias="sb_0__9_"/>
<key id="193" alias="cby_0__9_"/>
<key id="194" alias="grid_io_left_left_0__9_"/>
<key id="195" alias="grid_clb_1__9_"/>
<key id="196" alias="cby_1__9_"/>
<key id="197" alias="grid_clb_2__9_"/>
<key id="198" alias="cby_2__9_"/>
<key id="199" alias="grid_clb_3__9_"/>
<key id="200" alias="cby_3__9_"/>
<key id="201" alias="grid_clb_4__9_"/>
<key id="202" alias="cby_4__9_"/>
<key id="203" alias="grid_clb_5__9_"/>
<key id="204" alias="cby_5__9_"/>
<key id="205" alias="grid_clb_6__9_"/>
<key id="206" alias="cby_6__9_"/>
<key id="207" alias="grid_clb_7__9_"/>
<key id="208" alias="cby_7__9_"/>
<key id="209" alias="grid_clb_8__9_"/>
<key id="210" alias="cby_8__9_"/>
<key id="211" alias="grid_clb_9__9_"/>
<key id="212" alias="cby_9__9_"/>
<key id="213" alias="grid_clb_10__9_"/>
<key id="214" alias="cby_10__9_"/>
<key id="215" alias="grid_clb_11__9_"/>
<key id="216" alias="cby_11__9_"/>
<key id="217" alias="grid_clb_12__9_"/>
<key id="218" alias="cby_12__9_"/>
<key id="219" alias="grid_io_right_right_13__9_"/>
<key id="220" alias="sb_12__8_"/>
<key id="221" alias="cbx_12__8_"/>
<key id="222" alias="sb_11__8_"/>
<key id="223" alias="cbx_11__8_"/>
<key id="224" alias="sb_10__8_"/>
<key id="225" alias="cbx_10__8_"/>
<key id="226" alias="sb_9__8_"/>
<key id="227" alias="cbx_9__8_"/>
<key id="228" alias="sb_8__8_"/>
<key id="229" alias="cbx_8__8_"/>
<key id="230" alias="sb_7__8_"/>
<key id="231" alias="cbx_7__8_"/>
<key id="232" alias="sb_6__8_"/>
<key id="233" alias="cbx_6__8_"/>
<key id="234" alias="sb_5__8_"/>
<key id="235" alias="cbx_5__8_"/>
<key id="236" alias="sb_4__8_"/>
<key id="237" alias="cbx_4__8_"/>
<key id="238" alias="sb_3__8_"/>
<key id="239" alias="cbx_3__8_"/>
<key id="240" alias="sb_2__8_"/>
<key id="241" alias="cbx_2__8_"/>
<key id="242" alias="sb_1__8_"/>
<key id="243" alias="cbx_1__8_"/>
<key id="244" alias="sb_0__8_"/>
<key id="245" alias="cby_0__8_"/>
<key id="246" alias="grid_io_left_left_0__8_"/>
<key id="247" alias="grid_clb_1__8_"/>
<key id="248" alias="cby_1__8_"/>
<key id="249" alias="grid_clb_2__8_"/>
<key id="250" alias="cby_2__8_"/>
<key id="251" alias="grid_clb_3__8_"/>
<key id="252" alias="cby_3__8_"/>
<key id="253" alias="grid_clb_4__8_"/>
<key id="254" alias="cby_4__8_"/>
<key id="255" alias="grid_clb_5__8_"/>
<key id="256" alias="cby_5__8_"/>
<key id="257" alias="grid_clb_6__8_"/>
<key id="258" alias="cby_6__8_"/>
<key id="259" alias="grid_clb_7__8_"/>
<key id="260" alias="cby_7__8_"/>
<key id="261" alias="grid_clb_8__8_"/>
<key id="262" alias="cby_8__8_"/>
<key id="263" alias="grid_clb_9__8_"/>
<key id="264" alias="cby_9__8_"/>
<key id="265" alias="grid_clb_10__8_"/>
<key id="266" alias="cby_10__8_"/>
<key id="267" alias="grid_clb_11__8_"/>
<key id="268" alias="cby_11__8_"/>
<key id="269" alias="grid_clb_12__8_"/>
<key id="270" alias="cby_12__8_"/>
<key id="271" alias="grid_io_right_right_13__8_"/>
<key id="272" alias="sb_12__7_"/>
<key id="273" alias="cbx_12__7_"/>
<key id="274" alias="sb_11__7_"/>
<key id="275" alias="cbx_11__7_"/>
<key id="276" alias="sb_10__7_"/>
<key id="277" alias="cbx_10__7_"/>
<key id="278" alias="sb_9__7_"/>
<key id="279" alias="cbx_9__7_"/>
<key id="280" alias="sb_8__7_"/>
<key id="281" alias="cbx_8__7_"/>
<key id="282" alias="sb_7__7_"/>
<key id="283" alias="cbx_7__7_"/>
<key id="284" alias="sb_6__7_"/>
<key id="285" alias="cbx_6__7_"/>
<key id="286" alias="sb_5__7_"/>
<key id="287" alias="cbx_5__7_"/>
<key id="288" alias="sb_4__7_"/>
<key id="289" alias="cbx_4__7_"/>
<key id="290" alias="sb_3__7_"/>
<key id="291" alias="cbx_3__7_"/>
<key id="292" alias="sb_2__7_"/>
<key id="293" alias="cbx_2__7_"/>
<key id="294" alias="sb_1__7_"/>
<key id="295" alias="cbx_1__7_"/>
<key id="296" alias="sb_0__7_"/>
<key id="297" alias="cby_0__7_"/>
<key id="298" alias="grid_io_left_left_0__7_"/>
<key id="299" alias="grid_clb_1__7_"/>
<key id="300" alias="cby_1__7_"/>
<key id="301" alias="grid_clb_2__7_"/>
<key id="302" alias="cby_2__7_"/>
<key id="303" alias="grid_clb_3__7_"/>
<key id="304" alias="cby_3__7_"/>
<key id="305" alias="grid_clb_4__7_"/>
<key id="306" alias="cby_4__7_"/>
<key id="307" alias="grid_clb_5__7_"/>
<key id="308" alias="cby_5__7_"/>
<key id="309" alias="grid_clb_6__7_"/>
<key id="310" alias="cby_6__7_"/>
<key id="311" alias="grid_clb_7__7_"/>
<key id="312" alias="cby_7__7_"/>
<key id="313" alias="grid_clb_8__7_"/>
<key id="314" alias="cby_8__7_"/>
<key id="315" alias="grid_clb_9__7_"/>
<key id="316" alias="cby_9__7_"/>
<key id="317" alias="grid_clb_10__7_"/>
<key id="318" alias="cby_10__7_"/>
<key id="319" alias="grid_clb_11__7_"/>
<key id="320" alias="cby_11__7_"/>
<key id="321" alias="grid_clb_12__7_"/>
<key id="322" alias="cby_12__7_"/>
<key id="323" alias="grid_io_right_right_13__7_"/>
<key id="324" alias="sb_12__6_"/>
<key id="325" alias="cbx_12__6_"/>
<key id="326" alias="sb_11__6_"/>
<key id="327" alias="cbx_11__6_"/>
<key id="328" alias="sb_10__6_"/>
<key id="329" alias="cbx_10__6_"/>
<key id="330" alias="sb_9__6_"/>
<key id="331" alias="cbx_9__6_"/>
<key id="332" alias="sb_8__6_"/>
<key id="333" alias="cbx_8__6_"/>
<key id="334" alias="sb_7__6_"/>
<key id="335" alias="cbx_7__6_"/>
<key id="336" alias="sb_6__6_"/>
<key id="337" alias="cbx_6__6_"/>
<key id="338" alias="sb_5__6_"/>
<key id="339" alias="cbx_5__6_"/>
<key id="340" alias="sb_4__6_"/>
<key id="341" alias="cbx_4__6_"/>
<key id="342" alias="sb_3__6_"/>
<key id="343" alias="cbx_3__6_"/>
<key id="344" alias="sb_2__6_"/>
<key id="345" alias="cbx_2__6_"/>
<key id="346" alias="sb_1__6_"/>
<key id="347" alias="cbx_1__6_"/>
<key id="348" alias="sb_0__6_"/>
<key id="349" alias="cby_0__6_"/>
<key id="350" alias="grid_io_left_left_0__6_"/>
<key id="351" alias="grid_clb_1__6_"/>
<key id="352" alias="cby_1__6_"/>
<key id="353" alias="grid_clb_2__6_"/>
<key id="354" alias="cby_2__6_"/>
<key id="355" alias="grid_clb_3__6_"/>
<key id="356" alias="cby_3__6_"/>
<key id="357" alias="grid_clb_4__6_"/>
<key id="358" alias="cby_4__6_"/>
<key id="359" alias="grid_clb_5__6_"/>
<key id="360" alias="cby_5__6_"/>
<key id="361" alias="grid_clb_6__6_"/>
<key id="362" alias="cby_6__6_"/>
<key id="363" alias="grid_clb_7__6_"/>
<key id="364" alias="cby_7__6_"/>
<key id="365" alias="grid_clb_8__6_"/>
<key id="366" alias="cby_8__6_"/>
<key id="367" alias="grid_clb_9__6_"/>
<key id="368" alias="cby_9__6_"/>
<key id="369" alias="grid_clb_10__6_"/>
<key id="370" alias="cby_10__6_"/>
<key id="371" alias="grid_clb_11__6_"/>
<key id="372" alias="cby_11__6_"/>
<key id="373" alias="grid_clb_12__6_"/>
<key id="374" alias="cby_12__6_"/>
<key id="375" alias="grid_io_right_right_13__6_"/>
<key id="376" alias="sb_12__5_"/>
<key id="377" alias="cbx_12__5_"/>
<key id="378" alias="sb_11__5_"/>
<key id="379" alias="cbx_11__5_"/>
<key id="380" alias="sb_10__5_"/>
<key id="381" alias="cbx_10__5_"/>
<key id="382" alias="sb_9__5_"/>
<key id="383" alias="cbx_9__5_"/>
<key id="384" alias="sb_8__5_"/>
<key id="385" alias="cbx_8__5_"/>
<key id="386" alias="sb_7__5_"/>
<key id="387" alias="cbx_7__5_"/>
<key id="388" alias="sb_6__5_"/>
<key id="389" alias="cbx_6__5_"/>
<key id="390" alias="sb_5__5_"/>
<key id="391" alias="cbx_5__5_"/>
<key id="392" alias="sb_4__5_"/>
<key id="393" alias="cbx_4__5_"/>
<key id="394" alias="sb_3__5_"/>
<key id="395" alias="cbx_3__5_"/>
<key id="396" alias="sb_2__5_"/>
<key id="397" alias="cbx_2__5_"/>
<key id="398" alias="sb_1__5_"/>
<key id="399" alias="cbx_1__5_"/>
<key id="400" alias="sb_0__5_"/>
<key id="401" alias="cby_0__5_"/>
<key id="402" alias="grid_io_left_left_0__5_"/>
<key id="403" alias="grid_clb_1__5_"/>
<key id="404" alias="cby_1__5_"/>
<key id="405" alias="grid_clb_2__5_"/>
<key id="406" alias="cby_2__5_"/>
<key id="407" alias="grid_clb_3__5_"/>
<key id="408" alias="cby_3__5_"/>
<key id="409" alias="grid_clb_4__5_"/>
<key id="410" alias="cby_4__5_"/>
<key id="411" alias="grid_clb_5__5_"/>
<key id="412" alias="cby_5__5_"/>
<key id="413" alias="grid_clb_6__5_"/>
<key id="414" alias="cby_6__5_"/>
<key id="415" alias="grid_clb_7__5_"/>
<key id="416" alias="cby_7__5_"/>
<key id="417" alias="grid_clb_8__5_"/>
<key id="418" alias="cby_8__5_"/>
<key id="419" alias="grid_clb_9__5_"/>
<key id="420" alias="cby_9__5_"/>
<key id="421" alias="grid_clb_10__5_"/>
<key id="422" alias="cby_10__5_"/>
<key id="423" alias="grid_clb_11__5_"/>
<key id="424" alias="cby_11__5_"/>
<key id="425" alias="grid_clb_12__5_"/>
<key id="426" alias="cby_12__5_"/>
<key id="427" alias="grid_io_right_right_13__5_"/>
<key id="428" alias="sb_12__4_"/>
<key id="429" alias="cbx_12__4_"/>
<key id="430" alias="sb_11__4_"/>
<key id="431" alias="cbx_11__4_"/>
<key id="432" alias="sb_10__4_"/>
<key id="433" alias="cbx_10__4_"/>
<key id="434" alias="sb_9__4_"/>
<key id="435" alias="cbx_9__4_"/>
<key id="436" alias="sb_8__4_"/>
<key id="437" alias="cbx_8__4_"/>
<key id="438" alias="sb_7__4_"/>
<key id="439" alias="cbx_7__4_"/>
<key id="440" alias="sb_6__4_"/>
<key id="441" alias="cbx_6__4_"/>
<key id="442" alias="sb_5__4_"/>
<key id="443" alias="cbx_5__4_"/>
<key id="444" alias="sb_4__4_"/>
<key id="445" alias="cbx_4__4_"/>
<key id="446" alias="sb_3__4_"/>
<key id="447" alias="cbx_3__4_"/>
<key id="448" alias="sb_2__4_"/>
<key id="449" alias="cbx_2__4_"/>
<key id="450" alias="sb_1__4_"/>
<key id="451" alias="cbx_1__4_"/>
<key id="452" alias="sb_0__4_"/>
<key id="453" alias="cby_0__4_"/>
<key id="454" alias="grid_io_left_left_0__4_"/>
<key id="455" alias="grid_clb_1__4_"/>
<key id="456" alias="cby_1__4_"/>
<key id="457" alias="grid_clb_2__4_"/>
<key id="458" alias="cby_2__4_"/>
<key id="459" alias="grid_clb_3__4_"/>
<key id="460" alias="cby_3__4_"/>
<key id="461" alias="grid_clb_4__4_"/>
<key id="462" alias="cby_4__4_"/>
<key id="463" alias="grid_clb_5__4_"/>
<key id="464" alias="cby_5__4_"/>
<key id="465" alias="grid_clb_6__4_"/>
<key id="466" alias="cby_6__4_"/>
<key id="467" alias="grid_clb_7__4_"/>
<key id="468" alias="cby_7__4_"/>
<key id="469" alias="grid_clb_8__4_"/>
<key id="470" alias="cby_8__4_"/>
<key id="471" alias="grid_clb_9__4_"/>
<key id="472" alias="cby_9__4_"/>
<key id="473" alias="grid_clb_10__4_"/>
<key id="474" alias="cby_10__4_"/>
<key id="475" alias="grid_clb_11__4_"/>
<key id="476" alias="cby_11__4_"/>
<key id="477" alias="grid_clb_12__4_"/>
<key id="478" alias="cby_12__4_"/>
<key id="479" alias="grid_io_right_right_13__4_"/>
<key id="480" alias="sb_12__3_"/>
<key id="481" alias="cbx_12__3_"/>
<key id="482" alias="sb_11__3_"/>
<key id="483" alias="cbx_11__3_"/>
<key id="484" alias="sb_10__3_"/>
<key id="485" alias="cbx_10__3_"/>
<key id="486" alias="sb_9__3_"/>
<key id="487" alias="cbx_9__3_"/>
<key id="488" alias="sb_8__3_"/>
<key id="489" alias="cbx_8__3_"/>
<key id="490" alias="sb_7__3_"/>
<key id="491" alias="cbx_7__3_"/>
<key id="492" alias="sb_6__3_"/>
<key id="493" alias="cbx_6__3_"/>
<key id="494" alias="sb_5__3_"/>
<key id="495" alias="cbx_5__3_"/>
<key id="496" alias="sb_4__3_"/>
<key id="497" alias="cbx_4__3_"/>
<key id="498" alias="sb_3__3_"/>
<key id="499" alias="cbx_3__3_"/>
<key id="500" alias="sb_2__3_"/>
<key id="501" alias="cbx_2__3_"/>
<key id="502" alias="sb_1__3_"/>
<key id="503" alias="cbx_1__3_"/>
<key id="504" alias="sb_0__3_"/>
<key id="505" alias="cby_0__3_"/>
<key id="506" alias="grid_io_left_left_0__3_"/>
<key id="507" alias="grid_clb_1__3_"/>
<key id="508" alias="cby_1__3_"/>
<key id="509" alias="grid_clb_2__3_"/>
<key id="510" alias="cby_2__3_"/>
<key id="511" alias="grid_clb_3__3_"/>
<key id="512" alias="cby_3__3_"/>
<key id="513" alias="grid_clb_4__3_"/>
<key id="514" alias="cby_4__3_"/>
<key id="515" alias="grid_clb_5__3_"/>
<key id="516" alias="cby_5__3_"/>
<key id="517" alias="grid_clb_6__3_"/>
<key id="518" alias="cby_6__3_"/>
<key id="519" alias="grid_clb_7__3_"/>
<key id="520" alias="cby_7__3_"/>
<key id="521" alias="grid_clb_8__3_"/>
<key id="522" alias="cby_8__3_"/>
<key id="523" alias="grid_clb_9__3_"/>
<key id="524" alias="cby_9__3_"/>
<key id="525" alias="grid_clb_10__3_"/>
<key id="526" alias="cby_10__3_"/>
<key id="527" alias="grid_clb_11__3_"/>
<key id="528" alias="cby_11__3_"/>
<key id="529" alias="grid_clb_12__3_"/>
<key id="530" alias="cby_12__3_"/>
<key id="531" alias="grid_io_right_right_13__3_"/>
<key id="532" alias="sb_12__2_"/>
<key id="533" alias="cbx_12__2_"/>
<key id="534" alias="sb_11__2_"/>
<key id="535" alias="cbx_11__2_"/>
<key id="536" alias="sb_10__2_"/>
<key id="537" alias="cbx_10__2_"/>
<key id="538" alias="sb_9__2_"/>
<key id="539" alias="cbx_9__2_"/>
<key id="540" alias="sb_8__2_"/>
<key id="541" alias="cbx_8__2_"/>
<key id="542" alias="sb_7__2_"/>
<key id="543" alias="cbx_7__2_"/>
<key id="544" alias="sb_6__2_"/>
<key id="545" alias="cbx_6__2_"/>
<key id="546" alias="sb_5__2_"/>
<key id="547" alias="cbx_5__2_"/>
<key id="548" alias="sb_4__2_"/>
<key id="549" alias="cbx_4__2_"/>
<key id="550" alias="sb_3__2_"/>
<key id="551" alias="cbx_3__2_"/>
<key id="552" alias="sb_2__2_"/>
<key id="553" alias="cbx_2__2_"/>
<key id="554" alias="sb_1__2_"/>
<key id="555" alias="cbx_1__2_"/>
<key id="556" alias="sb_0__2_"/>
<key id="557" alias="cby_0__2_"/>
<key id="558" alias="grid_io_left_left_0__2_"/>
<key id="559" alias="grid_clb_1__2_"/>
<key id="560" alias="cby_1__2_"/>
<key id="561" alias="grid_clb_2__2_"/>
<key id="562" alias="cby_2__2_"/>
<key id="563" alias="grid_clb_3__2_"/>
<key id="564" alias="cby_3__2_"/>
<key id="565" alias="grid_clb_4__2_"/>
<key id="566" alias="cby_4__2_"/>
<key id="567" alias="grid_clb_5__2_"/>
<key id="568" alias="cby_5__2_"/>
<key id="569" alias="grid_clb_6__2_"/>
<key id="570" alias="cby_6__2_"/>
<key id="571" alias="grid_clb_7__2_"/>
<key id="572" alias="cby_7__2_"/>
<key id="573" alias="grid_clb_8__2_"/>
<key id="574" alias="cby_8__2_"/>
<key id="575" alias="grid_clb_9__2_"/>
<key id="576" alias="cby_9__2_"/>
<key id="577" alias="grid_clb_10__2_"/>
<key id="578" alias="cby_10__2_"/>
<key id="579" alias="grid_clb_11__2_"/>
<key id="580" alias="cby_11__2_"/>
<key id="581" alias="grid_clb_12__2_"/>
<key id="582" alias="cby_12__2_"/>
<key id="583" alias="grid_io_right_right_13__2_"/>
<key id="584" alias="sb_12__1_"/>
<key id="585" alias="cbx_12__1_"/>
<key id="586" alias="sb_11__1_"/>
<key id="587" alias="cbx_11__1_"/>
<key id="588" alias="sb_10__1_"/>
<key id="589" alias="cbx_10__1_"/>
<key id="590" alias="sb_9__1_"/>
<key id="591" alias="cbx_9__1_"/>
<key id="592" alias="sb_8__1_"/>
<key id="593" alias="cbx_8__1_"/>
<key id="594" alias="sb_7__1_"/>
<key id="595" alias="cbx_7__1_"/>
<key id="596" alias="sb_6__1_"/>
<key id="597" alias="cbx_6__1_"/>
<key id="598" alias="sb_5__1_"/>
<key id="599" alias="cbx_5__1_"/>
<key id="600" alias="sb_4__1_"/>
<key id="601" alias="cbx_4__1_"/>
<key id="602" alias="sb_3__1_"/>
<key id="603" alias="cbx_3__1_"/>
<key id="604" alias="sb_2__1_"/>
<key id="605" alias="cbx_2__1_"/>
<key id="606" alias="sb_1__1_"/>
<key id="607" alias="cbx_1__1_"/>
<key id="608" alias="sb_0__1_"/>
<key id="609" alias="cby_0__1_"/>
<key id="610" alias="grid_io_left_left_0__1_"/>
<key id="611" alias="grid_clb_1__1_"/>
<key id="612" alias="cby_1__1_"/>
<key id="613" alias="grid_clb_2__1_"/>
<key id="614" alias="cby_2__1_"/>
<key id="615" alias="grid_clb_3__1_"/>
<key id="616" alias="cby_3__1_"/>
<key id="617" alias="grid_clb_4__1_"/>
<key id="618" alias="cby_4__1_"/>
<key id="619" alias="grid_clb_5__1_"/>
<key id="620" alias="cby_5__1_"/>
<key id="621" alias="grid_clb_6__1_"/>
<key id="622" alias="cby_6__1_"/>
<key id="623" alias="grid_clb_7__1_"/>
<key id="624" alias="cby_7__1_"/>
<key id="625" alias="grid_clb_8__1_"/>
<key id="626" alias="cby_8__1_"/>
<key id="627" alias="grid_clb_9__1_"/>
<key id="628" alias="cby_9__1_"/>
<key id="629" alias="grid_clb_10__1_"/>
<key id="630" alias="cby_10__1_"/>
<key id="631" alias="grid_clb_11__1_"/>
<key id="632" alias="cby_11__1_"/>
<key id="633" alias="grid_clb_12__1_"/>
<key id="634" alias="cby_12__1_"/>
<key id="635" alias="grid_io_right_right_13__1_"/>
<key id="636" alias="sb_12__0_"/>
<key id="637" alias="cbx_12__0_"/>
<key id="638" alias="grid_io_bottom_bottom_12__0_"/>
<key id="639" alias="sb_11__0_"/>
<key id="640" alias="cbx_11__0_"/>
<key id="641" alias="grid_io_bottom_bottom_11__0_"/>
<key id="642" alias="sb_10__0_"/>
<key id="643" alias="cbx_10__0_"/>
<key id="644" alias="grid_io_bottom_bottom_10__0_"/>
<key id="645" alias="sb_9__0_"/>
<key id="646" alias="cbx_9__0_"/>
<key id="647" alias="grid_io_bottom_bottom_9__0_"/>
<key id="648" alias="sb_8__0_"/>
<key id="649" alias="cbx_8__0_"/>
<key id="650" alias="grid_io_bottom_bottom_8__0_"/>
<key id="651" alias="sb_7__0_"/>
<key id="652" alias="cbx_7__0_"/>
<key id="653" alias="grid_io_bottom_bottom_7__0_"/>
<key id="654" alias="sb_6__0_"/>
<key id="655" alias="cbx_6__0_"/>
<key id="656" alias="grid_io_bottom_bottom_6__0_"/>
<key id="657" alias="sb_5__0_"/>
<key id="658" alias="cbx_5__0_"/>
<key id="659" alias="grid_io_bottom_bottom_5__0_"/>
<key id="660" alias="sb_4__0_"/>
<key id="661" alias="cbx_4__0_"/>
<key id="662" alias="grid_io_bottom_bottom_4__0_"/>
<key id="663" alias="sb_3__0_"/>
<key id="664" alias="cbx_3__0_"/>
<key id="665" alias="grid_io_bottom_bottom_3__0_"/>
<key id="666" alias="sb_2__0_"/>
<key id="667" alias="cbx_2__0_"/>
<key id="668" alias="grid_io_bottom_bottom_2__0_"/>
<key id="669" alias="sb_1__0_"/>
<key id="670" alias="cbx_1__0_"/>
<key id="671" alias="grid_io_bottom_bottom_1__0_"/>
<key id="672" alias="sb_0__0_"/>
</region>
</fabric_key>

272
SOFA_A/SOFA_A_task/arch/openfpga_arch.xml Normal file
View File

@ -0,0 +1,272 @@
<!-- Architecture annotation for OpenFPGA framework
This annotation supports the k4_frac_cc_sky130nm.xml
- General purpose logic block
- K = 6, N = 10, I = 40
- Single mode
- Routing architecture
- L = 4, fc_in = 0.15, fc_out = 0.1
- Skywater 130nm PDK
- circuit models are binded to the opensource skywater
foundry middle-speed (ms) standard cell library
-->
<openfpga_architecture>
<technology_library>
<device_library>
<device_model name="logic" type="transistor">
<lib type="industry" corner="TOP_TT" ref="M" path="${OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.pm"/>
<design vdd="0.9" pn_ratio="2"/>
<pmos name="pch" chan_length="40e-9" min_width="140e-9" variation="logic_transistor_var"/>
<nmos name="nch" chan_length="40e-9" min_width="140e-9" variation="logic_transistor_var"/>
</device_model>
<device_model name="io" type="transistor">
<lib type="academia" ref="M" path="${OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.pm"/>
<design vdd="2.5" pn_ratio="3"/>
<pmos name="pch_25" chan_length="270e-9" min_width="320e-9" variation="io_transistor_var"/>
<nmos name="nch_25" chan_length="270e-9" min_width="320e-9" variation="io_transistor_var"/>
</device_model>
</device_library>
<variation_library>
<variation name="logic_transistor_var" abs_deviation="0.1" num_sigma="3"/>
<variation name="io_transistor_var" abs_deviation="0.1" num_sigma="3"/>
</variation_library>
</technology_library>
<circuit_library>
<circuit_model type="inv_buf" name="sky130_fd_sc_hd__inv_1" prefix="sky130_fd_sc_hd__inv_1" is_default="true" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/tasks/FPGA22_HIER_SKY_PNR/skywater/libraries/sky130_fd_sc_hd/latest/cells/inv/sky130_fd_sc_hd__inv_1.v">
<design_technology type="cmos" topology="inverter" size="1"/>
<device_technology device_model_name="logic"/>
<port type="input" prefix="in" lib_name="A" size="1"/>
<port type="output" prefix="out" lib_name="Y" size="1"/>
<delay_matrix type="rise" in_port="in" out_port="out">
10e-12
</delay_matrix>
<delay_matrix type="fall" in_port="in" out_port="out">
10e-12
</delay_matrix>
</circuit_model>
<circuit_model type="inv_buf" name="sky130_fd_sc_hd__buf_2" prefix="sky130_fd_sc_hd__buf_2" is_default="false" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/tasks/FPGA22_HIER_SKY_PNR/skywater/libraries/sky130_fd_sc_hd/latest/cells/buf/sky130_fd_sc_hd__buf_2.v">
<design_technology type="cmos" topology="buffer" size="1" num_level="2" f_per_stage="2"/>
<device_technology device_model_name="logic"/>
<port type="input" prefix="in" lib_name="A" size="1"/>
<port type="output" prefix="out" lib_name="X" size="1"/>
<delay_matrix type="rise" in_port="in" out_port="out">
10e-12
</delay_matrix>
<delay_matrix type="fall" in_port="in" out_port="out">
10e-12
</delay_matrix>
</circuit_model>
<circuit_model type="inv_buf" name="sky130_fd_sc_hd__buf_4" prefix="sky130_fd_sc_hd__buf_4" is_default="false" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/tasks/FPGA22_HIER_SKY_PNR/skywater/libraries/sky130_fd_sc_hd/latest/cells/buf/sky130_fd_sc_hd__buf_4.v">
<design_technology type="cmos" topology="buffer" size="1" num_level="2" f_per_stage="4"/>
<device_technology device_model_name="logic"/>
<port type="input" prefix="in" lib_name="A" size="1"/>
<port type="output" prefix="out" lib_name="X" size="1"/>
<delay_matrix type="rise" in_port="in" out_port="out">
10e-12
</delay_matrix>
<delay_matrix type="fall" in_port="in" out_port="out">
10e-12
</delay_matrix>
</circuit_model>
<circuit_model type="inv_buf" name="sky130_fd_sc_hd__inv_2" prefix="sky130_fd_sc_hd__inv_2" is_default="false" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/tasks/FPGA22_HIER_SKY_PNR/skywater/libraries/sky130_fd_sc_hd/latest/cells/inv/sky130_fd_sc_hd__inv_2.v">
<design_technology type="cmos" topology="buffer" size="1"/>
<device_technology device_model_name="logic"/>
<port type="input" prefix="in" lib_name="A" size="1"/>
<port type="output" prefix="out" lib_name="Y" size="1"/>
<delay_matrix type="rise" in_port="in" out_port="out">
10e-12
</delay_matrix>
<delay_matrix type="fall" in_port="in" out_port="out">
10e-12
</delay_matrix>
</circuit_model>
<circuit_model type="gate" name="sky130_fd_sc_hd__or2_1" prefix="sky130_fd_sc_hd__or2_1" is_default="true" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/tasks/FPGA22_HIER_SKY_PNR/skywater/libraries/sky130_fd_sc_hd/latest/cells/or2/sky130_fd_sc_hd__or2_1.v">
<design_technology type="cmos" topology="OR"/>
<device_technology device_model_name="logic"/>
<input_buffer exist="false"/>
<output_buffer exist="false"/>
<port type="input" prefix="a" lib_name="A" size="1"/>
<port type="input" prefix="b" lib_name="B" size="1"/>
<port type="output" prefix="out" lib_name="X" size="1"/>
<delay_matrix type="rise" in_port="a b" out_port="out">
10e-12 5e-12
</delay_matrix>
<delay_matrix type="fall" in_port="a b" out_port="out">
10e-12 5e-12
</delay_matrix>
</circuit_model>
<!-- Define a circuit model for the standard cell MUX2
OpenFPGA requires the following truth table for the MUX2
When the select signal sel is enabled, the first input, i.e., in0
will be propagated to the output, i.e., out
If your standard cell provider does not offer the exact truth table,
you can simply swap the inputs as shown in the example below
-->
<circuit_model type="gate" name="sky130_fd_sc_hd__mux2_1" prefix="sky130_fd_sc_hd__mux2_1" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/tasks/FPGA22_HIER_SKY_PNR/skywater/libraries/sky130_fd_sc_hd/latest/cells/mux2/sky130_fd_sc_hd__mux2_1.v">
<design_technology type="cmos" topology="MUX2"/>
<device_technology device_model_name="logic"/>
<input_buffer exist="false"/>
<output_buffer exist="false"/>
<port type="input" prefix="in0" lib_name="A1" size="1"/>
<port type="input" prefix="in1" lib_name="A0" size="1"/>
<port type="input" prefix="sel" lib_name="S" size="1"/>
<port type="output" prefix="out" lib_name="X" size="1"/>
</circuit_model>
<circuit_model type="chan_wire" name="chan_segment" prefix="track_seg" is_default="true">
<design_technology type="cmos"/>
<input_buffer exist="false"/>
<output_buffer exist="false"/>
<port type="input" prefix="in" size="1"/>
<port type="output" prefix="out" size="1"/>
<wire_param model_type="pi" R="101" C="22.5e-15" num_level="1"/>
<!-- model_type could be T, res_val and cap_val DON'T CARE -->
</circuit_model>
<circuit_model type="wire" name="direct_interc" prefix="direct_interc" is_default="true">
<design_technology type="cmos"/>
<input_buffer exist="false"/>
<output_buffer exist="false"/>
<port type="input" prefix="in" size="1"/>
<port type="output" prefix="out" size="1"/>
<wire_param model_type="pi" R="0" C="0" num_level="1"/>
<!-- model_type could be T, res_val cap_val should be defined -->
</circuit_model>
<circuit_model type="mux" name="mux_tree" prefix="mux_tree" is_default="true" dump_structural_verilog="true">
<design_technology type="cmos" structure="tree" add_const_input="true" const_input_val="1"/>
<input_buffer exist="false"/>
<output_buffer exist="false"/>
<pass_gate_logic circuit_model_name="sky130_fd_sc_hd__mux2_1"/>
<port type="input" prefix="in" size="1"/>
<port type="output" prefix="out" size="1"/>
<port type="sram" prefix="sram" size="1"/>
</circuit_model>
<circuit_model type="mux" name="mux_tree_tapbuf" prefix="mux_tree_tapbuf" dump_structural_verilog="true">
<design_technology type="cmos" structure="tree" add_const_input="true" const_input_val="1"/>
<input_buffer exist="false"/>
<output_buffer exist="true" circuit_model_name="sky130_fd_sc_hd__buf_4"/>
<pass_gate_logic circuit_model_name="sky130_fd_sc_hd__mux2_1"/>
<port type="input" prefix="in" size="1"/>
<port type="output" prefix="out" size="1"/>
<port type="sram" prefix="sram" size="1"/>
</circuit_model>
<!--DFF subckt ports should be defined as <D> <Q> <CLK> <RESET> <SET> -->
<circuit_model type="ff" name="sky130_fd_sc_hd__sdfrtp_1" prefix="sky130_fd_sc_hd__sdfrtp_1" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/tasks/FPGA22_HIER_SKY_PNR/skywater/libraries/sky130_fd_sc_hd/latest/cells/sdfrtp/sky130_fd_sc_hd__sdfrtp_1.v">
<design_technology type="cmos"/>
<input_buffer exist="true" circuit_model_name="sky130_fd_sc_hd__inv_1"/>
<output_buffer exist="true" circuit_model_name="sky130_fd_sc_hd__inv_1"/>
<port type="input" prefix="D" size="1"/>
<port type="input" prefix="DI" lib_name="SCD" size="1"/>
<port type="input" prefix="Test_en" lib_name="SCE" size="1" is_global="true" default_val="0"/>
<port type="input" prefix="reset" lib_name="RESET_B" size="1" default_val="1"/>
<port type="output" prefix="Q" size="1"/>
<port type="clock" prefix="clk" lib_name="CLK" size="1" is_global="false" default_val="0" />
</circuit_model>
<circuit_model type="lut" name="frac_lut4" prefix="frac_lut4" dump_structural_verilog="true">
<design_technology type="cmos" fracturable_lut="true"/>
<input_buffer exist="false"/>
<output_buffer exist="true" circuit_model_name="sky130_fd_sc_hd__buf_2"/>
<lut_input_inverter exist="true" circuit_model_name="sky130_fd_sc_hd__inv_1"/>
<lut_input_buffer exist="true" circuit_model_name="sky130_fd_sc_hd__buf_2"/>
<lut_intermediate_buffer exist="true" circuit_model_name="sky130_fd_sc_hd__buf_2" location_map="-1-"/>
<pass_gate_logic circuit_model_name="sky130_fd_sc_hd__mux2_1"/>
<port type="input" prefix="in" size="4" tri_state_map="---1" circuit_model_name="sky130_fd_sc_hd__or2_1"/>
<port type="output" prefix="lut2_out" size="2" lut_frac_level="2" lut_output_mask="2,3"/>
<port type="output" prefix="lut3_out" size="2" lut_frac_level="3" lut_output_mask="0,1"/>
<port type="output" prefix="lut4_out" size="1" lut_output_mask="0"/>
<port type="sram" prefix="sram" size="16"/>
<port type="sram" prefix="mode" size="1" mode_select="true" circuit_model_name="sky130_fd_sc_hd__dfrtp_1" default_val="1"/>
</circuit_model>
<!--Scan-chain DFF subckt ports should be defined as <D> <Q> <Qb> <CLK> <RESET> <SET> -->
<circuit_model type="ccff" name="sky130_fd_sc_hd__dfrtp_1" prefix="sky130_fd_sc_hd__dfrtp_1" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/tasks/FPGA22_HIER_SKY_PNR/skywater/libraries/sky130_fd_sc_hd/latest/cells/dfrtp/sky130_fd_sc_hd__dfrtp_1.v">
<design_technology type="cmos"/>
<input_buffer exist="true" circuit_model_name="sky130_fd_sc_hd__inv_1"/>
<output_buffer exist="true" circuit_model_name="sky130_fd_sc_hd__inv_1"/>
<port type="input" prefix="D" size="1"/>
<port type="output" prefix="Q" size="1"/>
<port type="clock" prefix="prog_clk" lib_name="CLK" size="1" is_global="true" default_val="0" is_prog="true"/>
<port type="input" prefix="pReset" lib_name="RESET_B" size="1" is_global="true" default_val="1" is_prog="true" is_reset="true"/>
</circuit_model>
<circuit_model type="iopad" name="EMBEDDED_IO_HD" prefix="EMBEDDED_IO_HD" is_default="true" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/tasks/FPGA22_HIER_SKY_PNR/sc_verilog/digital_io_hd.v">
<design_technology type="cmos"/>
<input_buffer exist="true" circuit_model_name="sky130_fd_sc_hd__inv_1"/>
<output_buffer exist="true" circuit_model_name="sky130_fd_sc_hd__inv_1"/>
<port type="input" prefix="SOC_IN" lib_name="SOC_IN" size="1" is_global="true" is_io="true" is_data_io="true"/>
<port type="output" prefix="SOC_OUT" lib_name="SOC_OUT" size="1" is_global="true" is_io="true" is_data_io="true"/>
<port type="output" prefix="SOC_DIR" lib_name="SOC_DIR" size="1" is_global="true" is_io="true"/>
<port type="input" prefix="IO_ISOL_N" lib_name="IO_ISOL_N" size="1" is_global="true" default_val="1"/>
<port type="output" prefix="inpad" lib_name="FPGA_IN" size="1"/>
<port type="input" prefix="outpad" lib_name="FPGA_OUT" size="1"/>
<port type="sram" prefix="en" lib_name="FPGA_DIR" size="1" mode_select="true" circuit_model_name="sky130_fd_sc_hd__dfrtp_1" default_val="1"/>
</circuit_model>
<circuit_model type="hard_logic" name="sky130_fd_sc_hd__mux2_1_wrapper" prefix="sky130_fd_sc_hd__mux2_1_wrapper" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/tasks/FPGA22_HIER_SKY_PNR/sc_verilog/sky130_fd_sc_hd_wrapper.v">
<design_technology type="cmos"/>
<device_technology device_model_name="logic"/>
<input_buffer exist="false"/>
<output_buffer exist="false"/>
<port type="input" prefix="a" lib_name="A0" size="1"/>
<port type="input" prefix="b" lib_name="A1" size="1"/>
<port type="input" prefix="cin" lib_name="S" size="1"/>
<port type="output" prefix="cout" lib_name="X" size="1"/>
</circuit_model>
</circuit_library>
<configuration_protocol>
<organization type="scan_chain" circuit_model_name="sky130_fd_sc_hd__dfrtp_1" num_regions="1"/>
</configuration_protocol>
<connection_block>
<switch name="ipin_cblock" circuit_model_name="mux_tree_tapbuf"/>
</connection_block>
<switch_block>
<switch name="L1_mux" circuit_model_name="mux_tree_tapbuf"/>
<switch name="L2_mux" circuit_model_name="mux_tree_tapbuf"/>
<switch name="L4_mux" circuit_model_name="mux_tree_tapbuf"/>
</switch_block>
<routing_segment>
<segment name="L1" circuit_model_name="chan_segment"/>
<segment name="L2" circuit_model_name="chan_segment"/>
<segment name="L4" circuit_model_name="chan_segment"/>
</routing_segment>
<direct_connection>
<direct name="carry_chain" circuit_model_name="direct_interc"/>
<direct name="shift_register" circuit_model_name="direct_interc"/>
<direct name="scan_chain" circuit_model_name="direct_interc" type="column" x_dir="positive" y_dir="positive"/>
</direct_connection>
<tile_annotations>
<global_port name="clk" is_clock="true" default_val="0">
<tile name="clb" port="clk" x="-1" y="-1"/>
</global_port>
<global_port name="Reset" is_reset="true" default_val="1">
<tile name="clb" port="reset" x="-1" y="-1"/>
</global_port>
</tile_annotations>
<pb_type_annotations>
<!-- physical pb_type binding in complex block IO -->
<pb_type name="io" physical_mode_name="physical" idle_mode_name="inpad"/>
<!-- IMPORTANT: must set unused I/Os to operating in INPUT mode !!! -->
<pb_type name="io[physical].iopad" circuit_model_name="EMBEDDED_IO_HD" mode_bits="1"/>
<pb_type name="io[inpad].inpad" physical_pb_type_name="io[physical].iopad" mode_bits="1"/>
<pb_type name="io[outpad].outpad" physical_pb_type_name="io[physical].iopad" mode_bits="0"/>
<!-- End physical pb_type binding in complex block IO -->
<!-- physical pb_type binding in complex block CLB -->
<!-- physical mode will be the default mode if not specified -->
<pb_type name="clb.fle" physical_mode_name="physical"/>
<pb_type name="clb.fle[physical].fabric.frac_logic.frac_lut4" circuit_model_name="frac_lut4" mode_bits="0"/>
<pb_type name="clb.fle[physical].fabric.frac_logic.carry_follower" circuit_model_name="sky130_fd_sc_hd__mux2_1_wrapper"/>
<pb_type name="clb.fle[physical].fabric.ff" circuit_model_name="sky130_fd_sc_hd__sdfrtp_1"/>
<!-- Binding operating pb_type to physical pb_type -->
<pb_type name="clb.fle[n2_lut3].lut3inter.ble3.lut3" physical_pb_type_name="clb.fle[physical].fabric.frac_logic.frac_lut4" mode_bits="1" physical_pb_type_index_factor="0.5">
<!-- Binding the lut3 to the first 3 inputs of fracturable lut4 -->
<port name="in" physical_mode_port="in[0:2]"/>
<port name="out" physical_mode_port="lut3_out[0:0]" physical_mode_pin_rotate_offset="1"/>
</pb_type>
<pb_type name="clb.fle[n2_lut3].lut3inter.ble3.ff" physical_pb_type_name="clb.fle[physical].fabric.ff"/>
<!-- Binding operating pb_types in mode 'ble4' -->
<pb_type name="clb.fle[n1_lut4].ble4.lut4" physical_pb_type_name="clb.fle[physical].fabric.frac_logic.frac_lut4" mode_bits="0">
<!-- Binding the lut4 to the first 4 inputs of fracturable lut4 -->
<port name="in" physical_mode_port="in[0:3]"/>
<port name="out" physical_mode_port="lut4_out"/>
</pb_type>
<pb_type name="clb.fle[n1_lut4].ble4.ff" physical_pb_type_name="clb.fle[physical].fabric.ff" physical_pb_type_index_factor="2" physical_pb_type_index_offset="0"/>
<!-- Binding operating pb_types in mode 'shift_register' -->
<pb_type name="clb.fle[shift_register].shift_reg.ff" physical_pb_type_name="clb.fle[physical].fabric.ff"/>
<!-- End physical pb_type binding in complex block IO -->
</pb_type_annotations>
</openfpga_architecture>

676
SOFA_A/SOFA_A_task/arch/vpr_arch.xml Normal file
View File

@ -0,0 +1,676 @@
<architecture>
<models>
<!-- A virtual model for I/O to be used in the physical mode of io block -->
<model name="io">
<input_ports>
<port name="outpad"/>
</input_ports>
<output_ports>
<port name="inpad"/>
</output_ports>
</model>
<model name="frac_lut4">
<input_ports>
<port name="in"/>
</input_ports>
<output_ports>
<port name="lut2_out"/>
<port name="lut3_out"/>
<port name="lut4_out"/>
</output_ports>
</model>
<model name="carry_follower">
<input_ports>
<port name="a"/>
<port name="b"/>
<port name="cin"/>
</input_ports>
<output_ports>
<port name="cout"/>
</output_ports>
</model>
<!-- A virtual model for scan-chain flip-flop to be used in the physical mode of FF -->
<model name="scff">
<input_ports>
<port name="D" clock="clk"/>
<port name="DI" clock="clk"/>
<port name="reset" clock="clk"/>
<port name="clk" is_clock="1"/>
</input_ports>
<output_ports>
<port name="Q" clock="clk"/>
</output_ports>
</model>
</models>
<tiles>
<!-- Top-side has 1 I/O per tile -->
<tile name="io_top" area="0">
<sub_tile name="io_top" capacity="8">
<equivalent_sites>
<site pb_type="io"/>
</equivalent_sites>
<input name="outpad" num_pins="1"/>
<output name="inpad" num_pins="1"/>
<fc in_type="frac" in_val="0.15" out_type="frac" out_val="0.10"/>
<pinlocations pattern="custom">
<loc side="bottom">io_top.outpad io_top.inpad</loc>
</pinlocations>
</sub_tile>
</tile>
<!-- Right-side has 1 I/O per tile -->
<tile name="io_right" area="0">
<sub_tile name="io_right" capacity="8">
<equivalent_sites>
<site pb_type="io"/>
</equivalent_sites>
<input name="outpad" num_pins="1"/>
<output name="inpad" num_pins="1"/>
<fc in_type="frac" in_val="0.15" out_type="frac" out_val="0.10"/>
<pinlocations pattern="custom">
<loc side="left">io_right.outpad io_right.inpad</loc>
</pinlocations>
</sub_tile>
</tile>
<!-- Bottom-side has 9 I/O per tile -->
<tile name="io_bottom" area="0">
<sub_tile name="io_bottom" capacity="9">
<equivalent_sites>
<site pb_type="io"/>
</equivalent_sites>
<input name="outpad" num_pins="1"/>
<output name="inpad" num_pins="1"/>
<fc in_type="frac" in_val="0.15" out_type="frac" out_val="0.10"/>
<pinlocations pattern="custom">
<loc side="top">io_bottom.outpad io_bottom.inpad</loc>
</pinlocations>
</sub_tile>
</tile>
<!-- Left-side has 1 I/O per tile -->
<tile name="io_left" area="0">
<sub_tile name="io_left" capacity="1">
<equivalent_sites>
<site pb_type="io"/>
</equivalent_sites>
<input name="outpad" num_pins="1"/>
<output name="inpad" num_pins="1"/>
<fc in_type="frac" in_val="0.15" out_type="frac" out_val="0.10"/>
<pinlocations pattern="custom">
<loc side="right">io_left.outpad io_left.inpad</loc>
</pinlocations>
</sub_tile>
</tile>
<!-- CLB has most pins on the top and right sides -->
<tile name="clb" area="53894">
<sub_tile name="clb" capacity="1">
<equivalent_sites>
<site pb_type="clb"/>
</equivalent_sites>
<input name="I0" num_pins="2" equivalent="full"/>
<input name="I0i" num_pins="2" equivalent="none"/>
<input name="I1" num_pins="2" equivalent="full"/>
<input name="I1i" num_pins="2" equivalent="none"/>
<input name="I2" num_pins="2" equivalent="full"/>
<input name="I2i" num_pins="2" equivalent="none"/>
<input name="I3" num_pins="2" equivalent="full"/>
<input name="I3i" num_pins="2" equivalent="none"/>
<input name="I4" num_pins="2" equivalent="full"/>
<input name="I4i" num_pins="2" equivalent="none"/>
<input name="I5" num_pins="2" equivalent="full"/>
<input name="I5i" num_pins="2" equivalent="none"/>
<input name="I6" num_pins="2" equivalent="full"/>
<input name="I6i" num_pins="2" equivalent="none"/>
<input name="I7" num_pins="2" equivalent="full"/>
<input name="I7i" num_pins="2" equivalent="none"/>
<input name="reg_in" num_pins="1"/>
<input name="sc_in" num_pins="1"/>
<input name="cin" num_pins="1"/>
<input name="reset" num_pins="1" is_non_clock_global="true"/>
<output name="O" num_pins="16" equivalent="none"/>
<output name="reg_out" num_pins="1"/>
<output name="sc_out" num_pins="1"/>
<output name="cout" num_pins="1"/>
<clock name="clk" num_pins="1"/>
<fc in_type="frac" in_val="0.15" out_type="frac" out_val="0.10">
<fc_override port_name="reg_in" fc_type="frac" fc_val="0"/>
<fc_override port_name="reg_out" fc_type="frac" fc_val="0"/>
<fc_override port_name="sc_in" fc_type="frac" fc_val="0"/>
<fc_override port_name="sc_out" fc_type="frac" fc_val="0"/>
<fc_override port_name="cin" fc_type="frac" fc_val="0"/>
<fc_override port_name="cout" fc_type="frac" fc_val="0"/>
<fc_override port_name="clk" fc_type="frac" fc_val="0"/>
<fc_override port_name="reset" fc_type="frac" fc_val="0"/>
</fc>
<!--pinlocations pattern="spread"/-->
<pinlocations pattern="custom">
<loc side="left">clb.clk clb.reset</loc>
<loc side="top">clb.reg_in clb.sc_in clb.cin clb.O[7:0] clb.I0 clb.I0i clb.I1 clb.I1i clb.I2 clb.I2i clb.I3 clb.I3i</loc>
<loc side="right">clb.O[15:8] clb.I4 clb.I4i clb.I5 clb.I5i clb.I6 clb.I6i clb.I7 clb.I7i</loc>
<loc side="bottom">clb.reg_out clb.sc_out clb.cout</loc>
</pinlocations>
</sub_tile>
</tile>
</tiles>
<!-- ODIN II specific config ends -->
<!-- Physical descriptions begin -->
<layout tileable="true">
<auto_layout aspect_ratio="1.0">
<!--Perimeter of 'io' blocks with 'EMPTY' blocks at corners-->
<row type="io_top" starty="H-1" priority="100"/>
<row type="io_bottom" starty="0" priority="100"/>
<col type="io_left" startx="0" priority="100"/>
<col type="io_right" startx="W-1" priority="100"/>
<corners type="EMPTY" priority="101"/>
<!--Fill with 'clb'-->
<fill type="clb" priority="10"/>
</auto_layout>
<fixed_layout name="2x2" width="4" height="4">
<!--Perimeter of 'io' blocks with 'EMPTY' blocks at corners-->
<row type="io_top" starty="H-1" priority="100"/>
<row type="io_bottom" starty="0" priority="100"/>
<col type="io_left" startx="0" priority="100"/>
<col type="io_right" startx="W-1" priority="100"/>
<corners type="EMPTY" priority="101"/>
<!--Fill with 'clb'-->
<fill type="clb" priority="10"/>
</fixed_layout>
<fixed_layout name="12x12" width="14" height="14">
<!--Perimeter of 'io' blocks with 'EMPTY' blocks at corners-->
<row type="io_top" starty="H-1" priority="100"/>
<row type="io_bottom" starty="0" priority="100"/>
<col type="io_left" startx="0" priority="100"/>
<col type="io_right" startx="W-1" priority="100"/>
<corners type="EMPTY" priority="101"/>
<!--Fill with 'clb'-->
<fill type="clb" priority="10"/>
</fixed_layout>
<fixed_layout name="16x16" width="18" height="18">
<!--Perimeter of 'io' blocks with 'EMPTY' blocks at corners-->
<row type="io_top" starty="H-1" priority="100"/>
<row type="io_bottom" starty="0" priority="100"/>
<col type="io_left" startx="0" priority="100"/>
<col type="io_right" startx="W-1" priority="100"/>
<corners type="EMPTY" priority="101"/>
<!--Fill with 'clb'-->
<fill type="clb" priority="10"/>
</fixed_layout>
</layout>
<device>
<sizing R_minW_nmos="8926" R_minW_pmos="16067"/>
<!-- The grid_logic_tile_area below will be used for all blocks that do not explicitly set their own (non-routing)
area; set to 0 since we explicitly set the area of all blocks currently in this architecture file.
-->
<area grid_logic_tile_area="0"/>
<chan_width_distr>
<x distr="uniform" peak="1.000000"/>
<y distr="uniform" peak="1.000000"/>
</chan_width_distr>
<switch_block type="wilton" fs="3" sub_type="subset" sub_fs="3"/>
<connection_block input_switch_name="ipin_cblock"/>
</device>
<switchlist>
<switch type="mux" name="L1_mux" R="0" Cin="0" Cout="0" Tdel="${L1_SB_MUX_DELAY}" mux_trans_size="2.630740" buf_size="27.645901"/>
<switch type="mux" name="L2_mux" R="0" Cin="0" Cout="0" Tdel="${L2_SB_MUX_DELAY}" mux_trans_size="2.630740" buf_size="27.645901"/>
<switch type="mux" name="L4_mux" R="0" Cin="0" Cout="0" Tdel="${L4_SB_MUX_DELAY}" mux_trans_size="2.630740" buf_size="27.645901"/>
<!--switch ipin_cblock resistance set to yeild for 4x minimum drive strength buffer-->
<switch type="mux" name="ipin_cblock" R="0" Cout="0" Cin="0" Tdel="${CB_MUX_DELAY}" mux_trans_size="1.222260" buf_size="auto"/>
</switchlist>
<segmentlist>
<!-- GIVE a specific name for the segment! OpenFPGA appreciate that! -->
<segment name="L1" freq="0.10" length="1" type="unidir" Rmetal="${L1_WIRE_R}" Cmetal="${L1_WIRE_C}">
<mux name="L1_mux"/>
<sb type="pattern">1 1</sb>
<cb type="pattern">1</cb>
</segment>
<segment name="L2" freq="0.10" length="2" type="unidir" Rmetal="${L2_WIRE_R}" Cmetal="${L2_WIRE_C}">
<mux name="L2_mux"/>
<sb type="pattern">1 1 1</sb>
<cb type="pattern">1 1</cb>
</segment>
<segment name="L4" freq="0.80" length="4" type="unidir" Rmetal="${L4_WIRE_R}" Cmetal="${L4_WIRE_C}">
<mux name="L4_mux"/>
<sb type="pattern">1 1 1 1 1</sb>
<cb type="pattern">1 1 1 1</cb>
</segment>
</segmentlist>
<directlist>
<direct name="carry_chain" from_pin="clb.cout" to_pin="clb.cin" x_offset="0" y_offset="-1" z_offset="0"/>
<direct name="shift_register" from_pin="clb.reg_out" to_pin="clb.reg_in" x_offset="0" y_offset="-1" z_offset="0"/>
<direct name="scan_chain" from_pin="clb.sc_out" to_pin="clb.sc_in" x_offset="0" y_offset="-1" z_offset="0"/>
</directlist>
<complexblocklist>
<!-- Define input pads begin -->
<pb_type name="io">
<input name="outpad" num_pins="1"/>
<output name="inpad" num_pins="1"/>
<!-- Do NOT add clock pins to I/O here!!! VPR does not build clock network in the way that OpenFPGA can support
If you need to register the I/O, define clocks in the circuit models
These clocks can be handled in back-end
-->
<!-- A mode denotes the physical implementation of an I/O
This mode will be not packable but is mainly used for fabric verilog generation
-->
<mode name="physical" disabled_in_pack="true">
<pb_type name="iopad" blif_model=".subckt io" num_pb="1">
<input name="outpad" num_pins="1"/>
<output name="inpad" num_pins="1"/>
</pb_type>
<interconnect>
<direct name="outpad" input="io.outpad" output="iopad.outpad">
<delay_constant max="${OUTPAD_DELAY}" in_port="io.outpad" out_port="iopad.outpad"/>
</direct>
<direct name="inpad" input="iopad.inpad" output="io.inpad">
<delay_constant max="${INPAD_DELAY}" in_port="iopad.inpad" out_port="io.inpad"/>
</direct>
</interconnect>
</mode>
<!-- IOs can operate as either inputs or outputs.
Delays below come from Ian Kuon. They are small, so they should be interpreted as
the delays to and from registers in the I/O (and generally I/Os are registered
today and that is when you timing analyze them.
-->
<mode name="inpad">
<pb_type name="inpad" blif_model=".input" num_pb="1">
<output name="inpad" num_pins="1"/>
</pb_type>
<interconnect>
<direct name="inpad" input="inpad.inpad" output="io.inpad">
<delay_constant max="${INPAD_DELAY}" in_port="inpad.inpad" out_port="io.inpad"/>
</direct>
</interconnect>
</mode>
<mode name="outpad">
<pb_type name="outpad" blif_model=".output" num_pb="1">
<input name="outpad" num_pins="1"/>
</pb_type>
<interconnect>
<direct name="outpad" input="io.outpad" output="outpad.outpad">
<delay_constant max="${OUTPAD_DELAY}" in_port="io.outpad" out_port="outpad.outpad"/>
</direct>
</interconnect>
</mode>
<power method="ignore"/>
</pb_type>
<!-- Define I/O pads ends -->
<!-- Define general purpose logic block (CLB) begin -->
<!-- -Due to the absence of local routing,
the 4 inputs of fracturable LUT4 are no longer equivalent,
because the 4th input can not be switched when the dual-LUT3 modes are used.
So pin equivalence should be applied to the first 3 inputs only
-->
<pb_type name="clb">
<input name="I0" num_pins="2" equivalent="full"/>
<input name="I0i" num_pins="2" equivalent="none"/>
<input name="I1" num_pins="2" equivalent="full"/>
<input name="I1i" num_pins="2" equivalent="none"/>
<input name="I2" num_pins="2" equivalent="full"/>
<input name="I2i" num_pins="2" equivalent="none"/>
<input name="I3" num_pins="2" equivalent="full"/>
<input name="I3i" num_pins="2" equivalent="none"/>
<input name="I4" num_pins="2" equivalent="full"/>
<input name="I4i" num_pins="2" equivalent="none"/>
<input name="I5" num_pins="2" equivalent="full"/>
<input name="I5i" num_pins="2" equivalent="none"/>
<input name="I6" num_pins="2" equivalent="full"/>
<input name="I6i" num_pins="2" equivalent="none"/>
<input name="I7" num_pins="2" equivalent="full"/>
<input name="I7i" num_pins="2" equivalent="none"/>
<input name="reg_in" num_pins="1"/>
<input name="sc_in" num_pins="1"/>
<input name="cin" num_pins="1"/>
<input name="reset" num_pins="1" is_non_clock_global="true"/>
<output name="O" num_pins="16" equivalent="none"/>
<output name="reg_out" num_pins="1"/>
<output name="sc_out" num_pins="1"/>
<output name="cout" num_pins="1"/>
<clock name="clk" num_pins="1"/>
<!-- Describe fracturable logic element.
Each fracturable logic element has a 6-LUT that can alternatively operate as two 5-LUTs with shared inputs.
The outputs of the fracturable logic element can be optionally registered
-->
<pb_type name="fle" num_pb="8">
<input name="in" num_pins="4"/>
<input name="reg_in" num_pins="1"/>
<input name="sc_in" num_pins="1"/>
<input name="cin" num_pins="1"/>
<input name="reset" num_pins="1"/>
<output name="out" num_pins="2"/>
<output name="reg_out" num_pins="1"/>
<output name="sc_out" num_pins="1"/>
<output name="cout" num_pins="1"/>
<clock name="clk" num_pins="1"/>
<!-- Physical mode definition begin (physical implementation of the fle) -->
<mode name="physical" disabled_in_pack="true">
<pb_type name="fabric" num_pb="1">
<input name="in" num_pins="4"/>
<input name="reg_in" num_pins="1"/>
<input name="sc_in" num_pins="1"/>
<input name="cin" num_pins="1"/>
<input name="reset" num_pins="1"/>
<output name="out" num_pins="2"/>
<output name="reg_out" num_pins="1"/>
<output name="sc_out" num_pins="1"/>
<output name="cout" num_pins="1"/>
<clock name="clk" num_pins="1"/>
<pb_type name="frac_logic" num_pb="1">
<input name="in" num_pins="4"/>
<input name="cin" num_pins="1"/>
<output name="out" num_pins="2"/>
<output name="cout" num_pins="1"/>
<!-- Define LUT -->
<pb_type name="frac_lut4" blif_model=".subckt frac_lut4" num_pb="1">
<input name="in" num_pins="4"/>
<output name="lut2_out" num_pins="2"/>
<output name="lut3_out" num_pins="2"/>
<output name="lut4_out" num_pins="1"/>
</pb_type>
<pb_type name="carry_follower" blif_model=".subckt carry_follower" num_pb="1">
<input name="a" num_pins="1"/>
<input name="b" num_pins="1"/>
<input name="cin" num_pins="1"/>
<output name="cout" num_pins="1"/>
</pb_type>
<interconnect>
<direct name="direct1" input="frac_logic.in[0:1]" output="frac_lut4.in[0:1]"/>
<direct name="direct2" input="frac_logic.in[3:3]" output="frac_lut4.in[3:3]"/>
<direct name="direct3" input="frac_logic.cin" output="carry_follower.b"/>
<direct name="direct4" input="frac_lut4.lut2_out[1:1]" output="carry_follower.a"/>
<direct name="direct5" input="frac_lut4.lut2_out[0:0]" output="carry_follower.cin"/>
<direct name="direct6" input="carry_follower.cout" output="frac_logic.cout"/>
<direct name="direct7" input="frac_lut4.lut3_out[1]" output="frac_logic.out[1]"/>
<!-- Xifan Tang: I use out[0] because the output of lut6 in lut6 mode is wired to the out[0] -->
<mux name="mux1" input="frac_lut4.lut4_out frac_lut4.lut3_out[0]" output="frac_logic.out[0]"/>
<mux name="mux2" input="frac_logic.cin frac_logic.in[2:2]" output="frac_lut4.in[2:2]"/>
</interconnect>
</pb_type>
<!-- Define flip-flop with scan-chain capability, DI is the scan-chain data input -->
<pb_type name="ff" blif_model=".subckt scff" num_pb="2">
<input name="D" num_pins="1"/>
<input name="DI" num_pins="1"/>
<input name="reset" num_pins="1"/>
<output name="Q" num_pins="1"/>
<clock name="clk" num_pins="1"/>
<T_setup value="${FF_T_SETUP}" port="ff.D" clock="clk"/>
<T_setup value="${FF_T_SETUP}" port="ff.DI" clock="clk"/>
<T_setup value="${FF_T_SETUP}" port="ff.reset" clock="clk"/>
<T_clock_to_Q max="${FF_T_CLK2Q}" port="ff.Q" clock="clk"/>
</pb_type>
<interconnect>
<direct name="direct1" input="fabric.in" output="frac_logic.in"/>
<direct name="direct2" input="fabric.cin" output="frac_logic.cin"/>
<direct name="direct3" input="fabric.sc_in" output="ff[0].DI"/>
<direct name="direct4" input="ff[0].Q" output="ff[1].DI"/>
<direct name="direct5" input="ff[1].Q" output="fabric.sc_out"/>
<direct name="direct6" input="ff[1].Q" output="fabric.reg_out"/>
<direct name="direct7" input="frac_logic.cout" output="fabric.cout"/>
<complete name="complete1" input="fabric.clk" output="ff[1:0].clk"/>
<complete name="complete2" input="fabric.reset" output="ff[1:0].reset"/>
<mux name="mux1" input="frac_logic.out[0:0] fabric.reg_in" output="ff[0:0].D">
<delay_constant max="${LUT_OUT0_TO_FF_D_DELAY}" in_port="frac_logic.out[0:0]" out_port="ff[0:0].D"/>
<delay_constant max="${LUT_OUT0_TO_FF_D_DELAY}" in_port="fabric.reg_in" out_port="ff[0:0].D"/>
</mux>
<mux name="mux2" input="frac_logic.out[1:1] ff[0:0].Q" output="ff[1:1].D">
<delay_constant max="${LUT_OUT1_TO_FF_D_DELAY}" in_port="frac_logic.out[1:1]" out_port="ff[1:1].D"/>
<delay_constant max="${LUT_OUT1_TO_FF_D_DELAY}" in_port="ff[0:0].Q" out_port="ff[1:1].D"/>
</mux>
<mux name="mux3" input="ff[0].Q frac_logic.out[0]" output="fabric.out[0]">
<!-- LUT to output is faster than FF to output on a Stratix IV -->
<delay_constant max="${LUT_OUT0_TO_FLE_OUT_DELAY}" in_port="frac_logic.out[0]" out_port="fabric.out[0]"/>
<delay_constant max="${FF0_Q_TO_FLE_OUT_DELAY}" in_port="ff[0].Q" out_port="fabric.out[0]"/>
</mux>
<mux name="mux4" input="ff[1].Q frac_logic.out[1]" output="fabric.out[1]">
<!-- LUT to output is faster than FF to output on a Stratix IV -->
<delay_constant max="${LUT_OUT1_TO_FLE_OUT_DELAY}" in_port="frac_logic.out[1]" out_port="fabric.out[1]"/>
<delay_constant max="${FF1_Q_TO_FLE_OUT_DELAY}" in_port="ff[1].Q" out_port="fabric.out[1]"/>
</mux>
</interconnect>
</pb_type>
<interconnect>
<direct name="direct1" input="fle.in" output="fabric.in"/>
<direct name="direct2" input="fle.reg_in" output="fabric.reg_in"/>
<direct name="direct3" input="fle.sc_in" output="fabric.sc_in"/>
<direct name="direct4" input="fle.cin" output="fabric.cin"/>
<direct name="direct5" input="fabric.out" output="fle.out"/>
<direct name="direct6" input="fabric.reg_out" output="fle.reg_out"/>
<direct name="direct7" input="fabric.sc_out" output="fle.sc_out"/>
<direct name="direct8" input="fabric.cout" output="fle.cout"/>
<direct name="direct9" input="fle.clk" output="fabric.clk"/>
<direct name="direct10" input="fle.reset" output="fabric.reset"/>
</interconnect>
</mode>
<!-- Physical mode definition end (physical implementation of the fle) -->
<!-- Dual 3-LUT mode definition begin -->
<mode name="n2_lut3">
<pb_type name="lut3inter" num_pb="1">
<input name="in" num_pins="3"/>
<output name="out" num_pins="2"/>
<clock name="clk" num_pins="1"/>
<pb_type name="ble3" num_pb="2">
<input name="in" num_pins="3"/>
<output name="out" num_pins="1"/>
<clock name="clk" num_pins="1"/>
<!-- Define the LUT -->
<pb_type name="lut3" blif_model=".names" num_pb="1" class="lut">
<input name="in" num_pins="3" port_class="lut_in"/>
<output name="out" num_pins="1" port_class="lut_out"/>
<!-- LUT timing using delay matrix -->
<delay_matrix type="max" in_port="lut3.in" out_port="lut3.out">
${LUT3_DELAY}
${LUT3_DELAY}
${LUT3_DELAY}
</delay_matrix>
</pb_type>
<!-- Define the flip-flop -->
<pb_type name="ff" blif_model=".latch" num_pb="1" class="flipflop">
<input name="D" num_pins="1" port_class="D"/>
<output name="Q" num_pins="1" port_class="Q"/>
<clock name="clk" num_pins="1" port_class="clock"/>
<T_setup value="${FF_T_SETUP}" port="ff.D" clock="clk"/>
<T_clock_to_Q max="${FF_T_CLK2Q}" port="ff.Q" clock="clk"/>
</pb_type>
<interconnect>
<direct name="direct1" input="ble3.in[2:0]" output="lut3[0:0].in[2:0]"/>
<direct name="direct2" input="lut3[0:0].out" output="ff[0:0].D">
<!-- Advanced user option that tells CAD tool to find LUT+FF pairs in netlist -->
<pack_pattern name="ble3" in_port="lut3[0:0].out" out_port="ff[0:0].D"/>
</direct>
<direct name="direct3" input="ble3.clk" output="ff[0:0].clk"/>
<mux name="mux1" input="ff[0:0].Q lut3.out[0:0]" output="ble3.out[0:0]">
<!-- LUT to output is faster than FF to output on a Stratix IV -->
<delay_constant max="${LUT3_OUT_TO_FLE_OUT_DELAY}" in_port="lut3.out[0:0]" out_port="ble3.out[0:0]"/>
<delay_constant max="${FF1_Q_TO_FLE_OUT_DELAY}" in_port="ff[0:0].Q" out_port="ble3.out[0:0]"/>
</mux>
</interconnect>
</pb_type>
<interconnect>
<direct name="direct1" input="lut3inter.in" output="ble3[0:0].in"/>
<direct name="direct2" input="lut3inter.in" output="ble3[1:1].in"/>
<direct name="direct3" input="ble3[1:0].out" output="lut3inter.out"/>
<complete name="complete1" input="lut3inter.clk" output="ble3[1:0].clk"/>
</interconnect>
</pb_type>
<interconnect>
<direct name="direct1" input="fle.in[2:0]" output="lut3inter.in"/>
<direct name="direct2" input="lut3inter.out" output="fle.out"/>
<direct name="direct3" input="fle.clk" output="lut3inter.clk"/>
</interconnect>
</mode>
<!-- Dual 3-LUT mode definition end -->
<!-- 4-LUT mode definition begin -->
<mode name="n1_lut4">
<!-- Define 4-LUT mode -->
<pb_type name="ble4" num_pb="1">
<input name="in" num_pins="4"/>
<output name="out" num_pins="1"/>
<clock name="clk" num_pins="1"/>
<!-- Define LUT -->
<pb_type name="lut4" blif_model=".names" num_pb="1" class="lut">
<input name="in" num_pins="4" port_class="lut_in"/>
<output name="out" num_pins="1" port_class="lut_out"/>
<!-- LUT timing using delay matrix -->
<delay_matrix type="max" in_port="lut4.in" out_port="lut4.out">
${LUT4_DELAY}
${LUT4_DELAY}
${LUT4_DELAY}
${LUT4_DELAY}
</delay_matrix>
</pb_type>
<!-- Define flip-flop -->
<pb_type name="ff" blif_model=".latch" num_pb="1" class="flipflop">
<input name="D" num_pins="1" port_class="D"/>
<output name="Q" num_pins="1" port_class="Q"/>
<clock name="clk" num_pins="1" port_class="clock"/>
<T_setup value="${FF_T_SETUP}" port="ff.D" clock="clk"/>
<T_clock_to_Q max="${FF_T_CLK2Q}" port="ff.Q" clock="clk"/>
</pb_type>
<interconnect>
<direct name="direct1" input="ble4.in" output="lut4[0:0].in"/>
<direct name="direct2" input="lut4.out" output="ff.D">
<!-- Advanced user option that tells CAD tool to find LUT+FF pairs in netlist -->
<pack_pattern name="ble4" in_port="lut4.out" out_port="ff.D"/>
<delay_constant max="${LUT_OUT0_TO_FF_D_DELAY}" in_port="lut4.out" out_port="ff.D"/>
</direct>
<direct name="direct3" input="ble4.clk" output="ff.clk"/>
<mux name="mux1" input="ff.Q lut4.out" output="ble4.out">
<!-- LUT to output is faster than FF to output on a Stratix IV -->
<delay_constant max="${LUT4_OUT_TO_FLE_OUT_DELAY}" in_port="lut4.out" out_port="ble4.out"/>
<delay_constant max="${FF0_Q_TO_FLE_OUT_DELAY}" in_port="ff.Q" out_port="ble4.out"/>
</mux>
</interconnect>
</pb_type>
<interconnect>
<direct name="direct1" input="fle.in" output="ble4.in"/>
<direct name="direct2" input="ble4.out" output="fle.out[0:0]"/>
<direct name="direct3" input="fle.clk" output="ble4.clk"/>
</interconnect>
</mode>
<!-- 4-LUT mode definition end -->
<!-- Define shift register begin -->
<mode name="shift_register">
<pb_type name="shift_reg" num_pb="1">
<input name="reg_in" num_pins="1"/>
<output name="ff_out" num_pins="2"/>
<output name="reg_out" num_pins="1"/>
<clock name="clk" num_pins="1"/>
<pb_type name="ff" blif_model=".latch" num_pb="2" class="flipflop">
<input name="D" num_pins="1" port_class="D"/>
<output name="Q" num_pins="1" port_class="Q"/>
<clock name="clk" num_pins="1" port_class="clock"/>
<T_setup value="${FF_T_SETUP}" port="ff.D" clock="clk"/>
<T_clock_to_Q max="${FF_T_CLK2Q}" port="ff.Q" clock="clk"/>
</pb_type>
<interconnect>
<direct name="direct1" input="shift_reg.reg_in" output="ff[0].D">
<delay_constant max="${LUT_OUT0_TO_FF_D_DELAY}" in_port="shift_reg.reg_in" out_port="ff[0].D"/>
</direct>
<direct name="direct2" input="ff[0].Q" output="ff[1].D">
<delay_constant max="${FF0_TO_FF1_DELAY}" in_port="ff[0].Q" out_port="ff[1].D"/>
</direct>
<direct name="direct3" input="ff[1].Q" output="shift_reg.reg_out"/>
<direct name="direct4" input="ff[0].Q" output="shift_reg.ff_out[0:0]">
<delay_constant max="${FF0_Q_TO_FLE_OUT_DELAY}" in_port="ff[0].Q" out_port="shift_reg.ff_out[0:0]"/>
</direct>
<direct name="direct5" input="ff[1].Q" output="shift_reg.ff_out[1:1]">
<delay_constant max="${FF1_Q_TO_FLE_OUT_DELAY}" in_port="ff[1].Q" out_port="shift_reg.ff_out[1:1]"/>
</direct>
<complete name="complete1" input="shift_reg.clk" output="ff.clk"/>
</interconnect>
</pb_type>
<interconnect>
<direct name="direct1" input="fle.reg_in" output="shift_reg.reg_in"/>
<direct name="direct2" input="shift_reg.reg_out" output="fle.reg_out"/>
<direct name="direct3" input="shift_reg.ff_out" output="fle.out"/>
<direct name="direct4" input="fle.clk" output="shift_reg.clk"/>
</interconnect>
</mode>
<!-- Define shift register end -->
</pb_type>
<interconnect>
<!-- We use direct connections to reduce the area to the most
The global local routing is going to compensate the loss in routability
-->
<!-- FIXME: The implicit port definition results in I0[0] connected to
in[2]. Such twisted connection is not expected.
I[0] should be connected to in[0]
-->
<direct name="direct_fle0" input="clb.I0[0:1]" output="fle[0:0].in[0:1]">
</direct>
<direct name="direct_fle0i" input="clb.I0i[0:1]" output="fle[0:0].in[2:3]">
</direct>
<direct name="direct_fle1" input="clb.I1[0:1]" output="fle[1:1].in[0:1]">
</direct>
<direct name="direct_fle1i" input="clb.I1i[0:1]" output="fle[1:1].in[2:3]">
</direct>
<direct name="direct_fle2" input="clb.I2[0:1]" output="fle[2:2].in[0:1]">
</direct>
<direct name="direct_fle2i" input="clb.I2i[0:1]" output="fle[2:2].in[2:3]">
</direct>
<direct name="direct_fle3" input="clb.I3[0:1]" output="fle[3:3].in[0:1]">
</direct>
<direct name="direct_fle3i" input="clb.I3i[0:1]" output="fle[3:3].in[2:3]">
</direct>
<direct name="direct_fle4" input="clb.I4[0:1]" output="fle[4:4].in[0:1]">
</direct>
<direct name="direct_fle4i" input="clb.I4i[0:1]" output="fle[4:4].in[2:3]">
</direct>
<direct name="direct_fle5" input="clb.I5[0:1]" output="fle[5:5].in[0:1]">
</direct>
<direct name="direct_fle5i" input="clb.I5i[0:1]" output="fle[5:5].in[2:3]">
</direct>
<direct name="direct_fle6" input="clb.I6[0:1]" output="fle[6:6].in[0:1]">
</direct>
<direct name="direct_fle6i" input="clb.I6i[0:1]" output="fle[6:6].in[2:3]">
</direct>
<direct name="direct_fle7" input="clb.I7[0:1]" output="fle[7:7].in[0:1]">
</direct>
<direct name="direct_fle7i" input="clb.I7i[0:1]" output="fle[7:7].in[2:3]">
</direct>
<complete name="clks" input="clb.clk" output="fle[7:0].clk">
</complete>
<complete name="resets" input="clb.reset" output="fle[7:0].reset">
</complete>
<!-- This way of specifying direct connection to clb outputs is important because this architecture uses automatic spreading of opins.
By grouping to output pins in this fashion, if a logic block is completely filled by 6-LUTs,
then the outputs those 6-LUTs take get evenly distributed across all four sides of the CLB instead of clumped on two sides (which is what happens with a more
naive specification).
-->
<direct name="clbouts1" input="fle[3:0].out[0:1]" output="clb.O[7:0]"/>
<direct name="clbouts2" input="fle[7:4].out[0:1]" output="clb.O[15:8]"/>
<!-- Shift register chain links -->
<direct name="shift_register_in" input="clb.reg_in" output="fle[0:0].reg_in">
<!-- Put all inter-block carry chain delay on this one edge -->
<delay_constant max="0" in_port="clb.reg_in" out_port="fle[0:0].reg_in"/>
<!--pack_pattern name="chain" in_port="clb.reg_in" out_port="fle[0:0].reg_in"/-->
</direct>
<direct name="shift_register_out" input="fle[7:7].reg_out" output="clb.reg_out">
<!--pack_pattern name="chain" in_port="fle[7:7].reg_out" out_port="clb.reg_out"/-->
</direct>
<direct name="shift_register_link" input="fle[6:0].reg_out" output="fle[7:1].reg_in">
<!--pack_pattern name="chain" in_port="fle[6:0].reg_out" out_port="fle[7:1].reg_in"/-->
</direct>
<!-- Scan chain links -->
<direct name="scan_chain_in" input="clb.sc_in" output="fle[0:0].sc_in">
<!-- Put all inter-block carry chain delay on this one edge -->
<delay_constant max="0" in_port="clb.sc_in" out_port="fle[0:0].sc_in"/>
</direct>
<direct name="scan_chain_out" input="fle[7:7].sc_out" output="clb.sc_out">
</direct>
<direct name="scan_chain_link" input="fle[6:0].sc_out" output="fle[7:1].sc_in">
</direct>
<!-- Carry chain links -->
<direct name="carry_chain_in" input="clb.cin" output="fle[0:0].cin">
<!-- Put all inter-block carry chain delay on this one edge -->
<delay_constant max="0" in_port="clb.cin" out_port="fle[0:0].cin"/>
</direct>
<direct name="carry_chain_out" input="fle[7:7].cout" output="clb.cout">
</direct>
<direct name="carry_chain_link" input="fle[6:0].cout" output="fle[7:1].cin">
</direct>
</interconnect>
<!-- Every input pin is driven by 15% of the tracks in a channel, every output pin is driven by 10% of the tracks in a channel -->
<!-- Place this general purpose logic block in any unspecified column -->
</pb_type>
<!-- Define general purpose logic block (CLB) ends -->
</complexblocklist>
</architecture>

54
SOFA_A/SOFA_A_task/config/task_benchmarks.conf Normal file
View File

@ -0,0 +1,54 @@
# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
# Configuration file for running experiments
# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
# timeout_each_job : FPGA Task script splits fpga flow into multiple jobs
# Each job execute fpga_flow script on combination of architecture & benchmark
# timeout_each_job is timeout for each job
# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
[GENERAL]
run_engine=openfpga_shell
power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml
power_analysis = true
spice_output=false
verilog_output=true
timeout_each_job = 1*60
fpga_flow=yosys_vpr
arch_variable_file=${PATH:TASK_DIR}/design_variables.yml
[OpenFPGA_SHELL]
openfpga_shell_template=${PATH:TASK_DIR}/generate_testbench.openfpga
openfpga_arch_file=${PATH:TASK_DIR}/arch/openfpga_arch.xml
openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml
external_fabric_key_file=${PATH:TASK_DIR}/arch/fabric_key.xml
openfpga_vpr_device_layout=12x12
openfpga_vpr_route_chan_width=60
[ARCHITECTURES]
arch0=${PATH:TASK_DIR}/arch/vpr_arch.xml
[BENCHMARKS]
bench0=${PATH:TASK_DIR}/BENCHMARK/and2/and2.v
bench1=${PATH:TASK_DIR}/BENCHMARK/and2_latch/and2_latch.v
bench2=${PATH:TASK_DIR}/BENCHMARK/bin2bcd/bin2bcd.v
bench3=${PATH:TASK_DIR}/BENCHMARK/counter/counter.v
bench4=${PATH:TASK_DIR}/BENCHMARK/routing_test/routing_test.v
# RS decoder needs 1.5k LUT4, exceeding device capacity
#bench5=${PATH:TASK_DIR}/BENCHMARK/rs_decoder/rtl/rs_decoder.v
bench6=${PATH:TASK_DIR}/BENCHMARK/simon_bit_serial/rtl/*.v
bench7=${PATH:TASK_DIR}/BENCHMARK/and2_or2/and2_or2.v
[SYNTHESIS_PARAM]
bench0_top = and2
bench1_top = and2_latch
bench2_top = bin2bcd
bench3_top = counter
bench4_top = routing_test
# RS decoder needs 1.5k LUT4, exceeding device capacity
#bench5_top = rs_decoder_top
bench6_top = top_module
bench7_top = and2_or2
[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH]
#end_flow_with_test=

39
SOFA_A/SOFA_A_task/config/task_generation.conf Normal file
View File

@ -0,0 +1,39 @@
# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
# Configuration file for running experiments
# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
# timeout_each_job : FPGA Task script splits fpga flow into multiple jobs
# Each job execute fpga_flow script on combination of architecture & benchmark
# timeout_each_job is timeout for each job
# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
[GENERAL]
run_engine=openfpga_shell
power_analysis = false
spice_output=false
verilog_output=true
timeout_each_job = 20*60
fpga_flow=vpr_blif
arch_variable_file=${PATH:TASK_DIR}/design_variables.yml
[OpenFPGA_SHELL]
openfpga_shell_template=${PATH:TASK_DIR}/generate_fabric.openfpga
openfpga_arch_file=${PATH:TASK_DIR}/arch/openfpga_arch.xml
openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml
external_fabric_key_file=${PATH:TASK_DIR}/arch/fabric_key.xml
openfpga_vpr_device_layout=12x12
openfpga_vpr_route_chan_width=60
[ARCHITECTURES]
arch0=${PATH:TASK_DIR}/arch/vpr_arch.xml
[BENCHMARKS]
bench0=${PATH:TASK_DIR}/micro_benchmark/and.blif
[SYNTHESIS_PARAM]
bench0_top = top
bench0_act = ${PATH:TASK_DIR}/micro_benchmark/and.act
bench0_verilog = ${PATH:TASK_DIR}/micro_benchmark/and.v
[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH]
vpr_fpga_verilog_formal_verification_top_netlist=

38
SOFA_A/SOFA_A_task/config/task_simulation.conf Normal file
View File

@ -0,0 +1,38 @@
# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
# Configuration file for running experiments
# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
# timeout_each_job : FPGA Task script splits fpga flow into multiple jobs
# Each job execute fpga_flow script on combination of architecture & benchmark
# timeout_each_job is timeout for each job
# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
[GENERAL]
run_engine=openfpga_shell
power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml
power_analysis = true
spice_output=false
verilog_output=true
timeout_each_job = 1*60
fpga_flow=yosys_vpr
arch_variable_file=${PATH:TASK_DIR}/design_variables.yml
[OpenFPGA_SHELL]
openfpga_shell_template=${PATH:TASK_DIR}/generate_testbench.openfpga
openfpga_arch_file=${PATH:TASK_DIR}/arch/openfpga_arch.xml
openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml
external_fabric_key_file=${PATH:TASK_DIR}/arch/fabric_key.xml
openfpga_vpr_device_layout=12x12
openfpga_vpr_route_chan_width=60
[ARCHITECTURES]
arch0=${PATH:TASK_DIR}/arch/vpr_arch.xml
[BENCHMARKS]
bench0=${PATH:TASK_DIR}/BENCHMARK/counter/counter.v
[SYNTHESIS_PARAM]
bench0_top = counter
[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH]
#end_flow_with_test=

26
SOFA_A/SOFA_A_task/design_variables.yml Normal file
View File

@ -0,0 +1,26 @@
L1_SB_MUX_DELAY: 1.44e-9
L2_SB_MUX_DELAY: 1.44e-9
L4_SB_MUX_DELAY: 1.44e-9
CB_MUX_DELAY: 1.38e-9
L1_WIRE_R: 100
L1_WIRE_C: 1e-12
L2_WIRE_R: 100
L2_WIRE_C: 1e-12
L4_WIRE_R: 100
L4_WIRE_C: 1e-12
INPAD_DELAY: 0.11e-9
OUTPAD_DELAY: 0.11e-9
FF_T_SETUP: 0.39e-9
FF_T_CLK2Q: 0.43e-9
LUT_OUT0_TO_FF_D_DELAY: 1.14e-9
LUT_OUT1_TO_FF_D_DELAY: 0.56e-9
LUT_OUT0_TO_FLE_OUT_DELAY: 0.89e-9
FF0_Q_TO_FLE_OUT_DELAY: 0.88e-9
LUT_OUT1_TO_FLE_OUT_DELAY: 0.78e-9
FF1_Q_TO_FLE_OUT_DELAY: 0.89e-9
LUT3_DELAY: 0.92e-9
LUT3_OUT_TO_FLE_OUT_DELAY: 1.44e-9
LUT4_DELAY: 1.21e-9
LUT4_OUT_TO_FLE_OUT_DELAY: 1.46e-9
REGIN_TO_FF0_DELAY: 1.12e-9
FF0_TO_FF1_DELAY: 0.56e-9

76
SOFA_A/SOFA_A_task/generate_fabric.openfpga Normal file
View File

@ -0,0 +1,76 @@
# Run VPR for the 'and' design
#--write_rr_graph example_rr_graph.xml
vpr ${VPR_ARCH_FILE} ${VPR_TESTBENCH_BLIF} --clock_modeling route
# Read OpenFPGA architecture definition
read_openfpga_arch -f ${OPENFPGA_ARCH_FILE}
# Read OpenFPGA simulation settings
read_openfpga_simulation_setting -f ${OPENFPGA_SIM_SETTING_FILE}
# Annotate the OpenFPGA architecture to VPR data base
# to debug use --verbose options
link_openfpga_arch --activity_file ${ACTIVITY_FILE} --sort_gsb_chan_node_in_edges
# Check and correct any naming conflicts in the BLIF netlist
check_netlist_naming_conflict --fix --report ./netlist_renaming.xml
# Apply fix-up to clustering nets based on routing results
pb_pin_fixup --verbose
# Apply fix-up to Look-Up Table truth tables based on packing results
lut_truth_table_fixup
# Build the module graph
# - Enabled compression on routing architecture modules
# - Enable pin duplication on grid modules
build_fabric --compress_routing #--verbose
# Write the fabric hierarchy of module graph to a file
# This is used by hierarchical PnR flows
write_fabric_hierarchy --file ./fabric_hierarchy.txt
# Repack the netlist to physical pbs
# This must be done before bitstream generator and testbench generation
# Strongly recommend it is done after all the fix-up have been applied
repack #--verbose
# Build the bitstream
# - Output the fabric-independent bitstream to a file
build_architecture_bitstream --verbose --write_file fabric_independent_bitstream.xml
# Build fabric-dependent bitstream
build_fabric_bitstream --verbose
# Write fabric-dependent bitstream
write_fabric_bitstream --file fabric_bitstream.bit --format plain_text
# Write the Verilog netlist for FPGA fabric
# - Enable the use of explicit port mapping in Verilog netlist
write_fabric_verilog --file ./SRC --explicit_port_mapping --include_timing --print_user_defined_template --verbose
# Write the Verilog testbench for FPGA fabric
# - We suggest the use of same output directory as fabric Verilog netlists
# - Must specify the reference benchmark file if you want to output any testbenches
# - Enable top-level testbench which is a full verification including programming circuit and core logic of FPGA
# - Enable pre-configured top-level testbench which is a fast verification skipping programming phase
# - Simulation ini file is optional and is needed only when you need to interface different HDL simulators using openfpga flow-run scripts
write_full_testbench --file ./SRC --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} --explicit_port_mapping --include_signal_init --bitstream fabric_bitstream.bit
write_preconfigured_fabric_wrapper --embed_bitstream iverilog --file ./SRC --explicit_port_mapping
write_preconfigured_testbench --file ./SRC --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} --explicit_port_mapping
# Write the SDC files for PnR backend
# - Turn on every options here
write_pnr_sdc --file ./SDC
# Write SDC to disable timing for configure ports
write_sdc_disable_timing_configure_ports --file ./SDC/disable_configure_ports.sdc
# Write the SDC to run timing analysis for a mapped FPGA fabric
write_analysis_sdc --file ./SDC_analysis
# Finish and exit OpenFPGA
exit
# Note :
# To run verification at the end of the flow maintain source in ./SRC directory

74
SOFA_A/SOFA_A_task/generate_testbench.openfpga Normal file
View File

@ -0,0 +1,74 @@
# This script is designed to generate Verilog testbenches
# with a fixed device layout
# It will only output netlists to be used by verification tools
# including
# - Verilog testbenches, used by ModelSim
# - SDC for a mapped FPGA fabric, used by Synopsys PrimeTime
#
#--write_rr_graph example_rr_graph.xml
vpr ${VPR_ARCH_FILE} ${VPR_TESTBENCH_BLIF} --clock_modeling ideal --device ${OPENFPGA_VPR_DEVICE_LAYOUT} --route_chan_width ${OPENFPGA_VPR_ROUTE_CHAN_WIDTH} --absorb_buffer_luts off
# Read OpenFPGA architecture definition
read_openfpga_arch -f ${OPENFPGA_ARCH_FILE}
# Read OpenFPGA simulation settings
read_openfpga_simulation_setting -f ${OPENFPGA_SIM_SETTING_FILE}
# Annotate the OpenFPGA architecture to VPR data base
# to debug use --verbose options
link_openfpga_arch --activity_file ${ACTIVITY_FILE} --sort_gsb_chan_node_in_edges
# Check and correct any naming conflicts in the BLIF netlist
check_netlist_naming_conflict --fix --report ./netlist_renaming.xml
# Apply fix-up to clustering nets based on routing results
pb_pin_fixup --verbose
# Apply fix-up to Look-Up Table truth tables based on packing results
lut_truth_table_fixup
# Build the module graph
# - Enabled compression on routing architecture modules
# - Enable pin duplication on grid modules
build_fabric --compress_routing --duplicate_grid_pin --load_fabric_key ${EXTERNAL_FABRIC_KEY_FILE} #--verbose
# Repack the netlist to physical pbs
# This must be done before bitstream generator and testbench generation
# Strongly recommend it is done after all the fix-up have been applied
repack #--verbose
# Build the bitstream
# - Output the fabric-independent bitstream to a file
build_architecture_bitstream --verbose --write_file arch_bitstream.xml
# Build fabric-dependent bitstream
build_fabric_bitstream --verbose
# Write fabric-dependent bitstream
write_fabric_bitstream --file fabric_bitstream.xml --format xml
write_fabric_bitstream --file fabric_bitstream.bit --format plain_text
# Write the Verilog testbench for FPGA fabric
# - We suggest the use of same output directory as fabric Verilog netlists
# - Must specify the reference benchmark file if you want to output any testbenches
# - Enable top-level testbench which is a full verification including programming circuit and core logic of FPGA
# - Enable pre-configured top-level testbench which is a fast verification skipping programming phase
# - Simulation ini file is optional and is needed only when you need to interface different HDL simulators using openfpga flow-run scripts
write_verilog_testbench --file ./SRC \
--reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} \
--print_top_testbench \
--print_preconfig_top_testbench \
--print_simulation_ini ./SimulationDeck/simulation_deck.ini \
--explicit_port_mapping
# Exclude signal initialization since it does not help simulator converge
# due to the lack of reset pins for flip-flops
#--include_signal_init
# Write the SDC to run timing analysis for a mapped FPGA fabric
write_analysis_sdc --file ./SDC_analysis
# Finish and exit OpenFPGA
exit
# Note :
# To run verification at the end of the flow maintain source in ./SRC directory

3
SOFA_A/SOFA_A_task/micro_benchmark/and.act Normal file
View File

@ -0,0 +1,3 @@
a 0.5 0.5
b 0.5 0.5
c 0.25 0.25

8
SOFA_A/SOFA_A_task/micro_benchmark/and.blif Normal file
View File

@ -0,0 +1,8 @@
.model top
.inputs a b
.outputs c
.names a b c
11 1
.end

14
SOFA_A/SOFA_A_task/micro_benchmark/and.v Normal file
View File

@ -0,0 +1,14 @@
`timescale 1ns / 1ps
module top(
a,
b,
c);
input wire a;
input wire b;
output wire c;
assign c = a & b;
endmodule

46
SOFA_A/SOFA_A_task/process_top_def.sh Normal file
View File

@ -0,0 +1,46 @@
#!/bin/bash
cp user_project_wrapper_template.def user_project_wrapper_empty.def
sed -i '/^SPECIALNETS/,/END SPECIALNETS/d' user_project_wrapper_empty.def
sed -i '/^VIAS/,/END VIAS/d' user_project_wrapper_empty.def
sed -i '/^ROW ROW/d' user_project_wrapper_empty.def
sed -i '/^TRACKS/d' user_project_wrapper_empty.def
sed -i 's/user_project_wrapper/fpga_top/' user_project_wrapper_empty.def
VDD_LINES=$(grep "\- vdda\|vccd" user_project_wrapper_empty.def)
VSS_LINES=$(grep "\- vssa\|vssd" user_project_wrapper_empty.def)
sed -i '/^ - v.*$/d' user_project_wrapper_empty.def
X="2920000"
Y="3520000"
VDD_LINES=$(echo "${VDD_LINES}" | sed "s/\-.*\(FIXED.*\) ;/+ PORT + \1/g")
VDD_LINES=$(echo "${VDD_LINES}" | sed "s/^.*met.*[0-9]\{6,\}.*//")
VDD_LINES=$(echo "${VDD_LINES}" | sed "s/\(.*met5\).*) ( \([0-9]*\) \([0-9]*\) )/\1 ( -5000 -\3 ) ( 5000 \3 )/g")
VDD_LINES=$(echo "${VDD_LINES}" | sed "s/\(.*met4\).*) ( \([0-9]*\) \([0-9]*\) )/\1 ( -\2 -5000 ) ( \2 5000 )/g")
VDD_LINES=$(echo "${VDD_LINES}" | sed "s/FIXED ( \([0-9]*\) \([0-9]*\)\(.*met5\)/FIXED ( 2920000 \2 \3/g")
VDD_LINES=$(echo "${VDD_LINES}" | sed "s/FIXED ( \(-[0-9]*\) \([0-9]*\)\(.*met5\)/FIXED ( 0 \2 \3/g")
VDD_LINES=$(echo "${VDD_LINES}" | sed "s/FIXED ( \([0-9]*\) \([0-9]*\) )\(.*met4\)/FIXED ( \1 3520000 ) \3/g")
VDD_LINES=$(echo "${VDD_LINES}" | sed "s/FIXED ( \([0-9]*\) \(-[0-9]*\) )\(.*met4\)/FIXED ( \1 0 ) \3/g")
VSS_LINES=$(echo "${VSS_LINES}" | sed "s/\-.*\(FIXED.*\) ;/+ PORT + \1/g")
VSS_LINES=$(echo "${VSS_LINES}" | sed "s/^.*met.*[0-9]\{6,\}.*//")
VSS_LINES=$(echo "${VSS_LINES}" | sed "s/\(.*met5\).*) ( \([0-9]*\) \([0-9]*\) )/\1 ( -5000 -\3 ) ( 5000 \3 )/g")
VSS_LINES=$(echo "${VSS_LINES}" | sed "s/\(.*met4\).*) ( \([0-9]*\) \([0-9]*\) )/\1 ( -\2 -5000 ) ( \2 5000 )/g")
VSS_LINES=$(echo "${VSS_LINES}" | sed "s/FIXED ( \([0-9]*\) \([0-9]*\)\(.*met5\)/FIXED ( 2920000 \2 \3/g")
VSS_LINES=$(echo "${VSS_LINES}" | sed "s/FIXED ( \(-[0-9]*\) \([0-9]*\)\(.*met5\)/FIXED ( 0 \2 \3/g")
VSS_LINES=$(echo "${VSS_LINES}" | sed "s/FIXED ( \([0-9]*\) \([0-9]*\) )\(.*met4\)/FIXED ( \1 3520000 ) \3/g")
VSS_LINES=$(echo "${VSS_LINES}" | sed "s/FIXED ( \([0-9]*\) \(-[0-9]*\) )\(.*met4\)/FIXED ( \1 0 ) \3/g")
sed -i '/END PINS/d' user_project_wrapper_empty.def
sed -i '/END DESIGN/d' user_project_wrapper_empty.def
echo " - VDD + NET VDD + SPECIAL + DIRECTION INPUT + USE POWER" >> user_project_wrapper_empty.def
printf "${VDD_LINES} ;\n" >> user_project_wrapper_empty.def
echo "- VSS + NET VSS + SPECIAL + DIRECTION INPUT + USE GROUND" >> user_project_wrapper_empty.def
printf "${VSS_LINES} ;\n" >> user_project_wrapper_empty.def
echo "END PINS" >> user_project_wrapper_empty.def
echo "END DESIGN" >> user_project_wrapper_empty.def

55
SOFA_A/SOFA_A_task/sc_verilog/digital_io_hd.v Normal file
View File

@ -0,0 +1,55 @@
`timescale 1ns/1ps
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
module EMBEDDED_IO_HD (
input SOC_IN, //
output SOC_OUT, //
output SOC_DIR, //
output FPGA_IN, //
input FPGA_OUT, //
input FPGA_DIR, //
input IO_ISOL_N //
);
wire SOC_DIR_N;
//
sky130_fd_sc_hd__or2b_4 ISOL_EN_GATE (.B_N(IO_ISOL_N),
.A(FPGA_DIR),
.X(SOC_DIR)
);
//
sky130_fd_sc_hd__inv_1 INV_SOC_DIR (.A(SOC_DIR), .Y(SOC_DIR_N));
sky130_fd_sc_hd__ebufn_4 IN_PROTECT_GATE (.TE_B(SOC_DIR_N),
.A(SOC_IN),
.Z(FPGA_IN)
);
//
sky130_fd_sc_hd__ebufn_4 OUT_PROTECT_GATE (.TE_B(SOC_DIR),
.A(FPGA_OUT),
.Z(SOC_OUT)
);
endmodule

483
SOFA_A/SOFA_A_task/sc_verilog/fpga_top.v Normal file
View File

@ -0,0 +1,483 @@
/*
*-------------------------------------------------------------
*
* A wrapper for the FPGA IP to fit the I/O interface of Caravel SoC
*
* The wrapper is a technology mapped netlist where the mode-switch
* multiplexers are mapped to the Skywater 130nm
* High-Density (HD) standard cells
*
*-------------------------------------------------------------
*/
module fpga_top (
//
//
inout vdda1, //
inout vdda2, //
inout vssa1, //
inout vssa2, //
inout vccd1, //
inout vccd2, //
inout vssd1, //
inout vssd2, //
//
input wb_clk_i,
input wb_rst_i,
input wbs_stb_i,
input wbs_cyc_i,
input wbs_we_i,
input [3:0] wbs_sel_i,
input [31:0] wbs_dat_i,
input [31:0] wbs_adr_i,
output wbs_ack_o,
output [31:0] wbs_dat_o,
//
input [127:0] la_data_in,
output [127:0] la_data_out,
input [127:0] la_oen,
//
input [37:0] io_in,
output [37:0] io_out,
output [37:0] io_oeb
);
//
//
//
//
//
//
//
//
wire prog_clk;
wire Test_en;
wire IO_ISOL_N;
wire clk;
wire [0:143] gfpga_pad_EMBEDDED_IO_HD_SOC_IN;
wire [0:143] gfpga_pad_EMBEDDED_IO_HD_SOC_OUT;
wire [0:143] gfpga_pad_EMBEDDED_IO_HD_SOC_DIR;
wire ccff_head;
wire ccff_tail;
wire sc_head;
wire sc_tail;
wire pReset;
wire Reset;
//
wire wb_la_switch;
wire wb_la_switch_b;
//
//
//
sky130_fd_sc_hd__inv_8 WB_LA_SWITCH_INV (.A(wb_la_switch), .Y(wb_la_switch_b));
//
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[0] = io_in[24];
assign io_out[24] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[0];
assign io_oeb[24] = gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[0];
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[1] = io_in[23];
assign io_out[23] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[1];
assign io_oeb[23] = gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[1];
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[2] = io_in[22];
assign io_out[22] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[2];
assign io_oeb[22] = gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[2];
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[3] = io_in[21];
assign io_out[21] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[3];
assign io_oeb[21] = gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[3];
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[4] = io_in[20];
assign io_out[20] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[4];
assign io_oeb[20] = gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[4];
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[5] = io_in[19];
assign io_out[19] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[5];
assign io_oeb[19] = gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[5];
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[6] = io_in[18];
assign io_out[18] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[6];
assign io_oeb[18] = gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[6];
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[7] = io_in[17];
assign io_out[17] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[7];
assign io_oeb[17] = gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[7];
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[8] = io_in[16];
assign io_out[16] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[8];
assign io_oeb[16] = gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[8];
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[9] = io_in[15];
assign io_out[15] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[9];
assign io_oeb[15] = gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[9];
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[10] = io_in[14];
assign io_out[14] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[10];
assign io_oeb[14] = gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[10];
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[11] = io_in[13];
assign io_out[13] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[11];
assign io_oeb[13] = gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[11];
assign ccff_head = io_in[12];
assign io_out[12] = 1'b0;
assign io_oeb[12] = 1'b1;
assign io_out[11] = sc_tail;
assign io_oeb[11] = 1'b0;
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[12] = io_in[10];
assign io_out[10] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[12];
assign io_oeb[10] = gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[12];
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[13] = io_in[9];
assign io_out[9] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[13];
assign io_oeb[9] = gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[13];
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[14] = io_in[8];
assign io_out[8] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[14];
assign io_oeb[8] = gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[14];
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[15] = io_in[7];
assign io_out[7] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[15];
assign io_oeb[7] = gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[15];
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[16] = io_in[6];
assign io_out[6] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[16];
assign io_oeb[6] = gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[16];
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[17] = io_in[5];
assign io_out[5] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[17];
assign io_oeb[5] = gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[17];
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[18] = io_in[4];
assign io_out[4] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[18];
assign io_oeb[4] = gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[18];
assign pReset = io_in[3];
assign io_out[3] = 1'b0;
assign io_oeb[3] = 1'b1;
assign Reset = io_in[2];
assign io_out[2] = 1'b0;
assign io_oeb[2] = 1'b1;
assign IO_ISOL_N = io_in[1];
assign io_out[1] = 1'b0;
assign io_oeb[1] = 1'b1;
assign Test_en = io_in[0];
assign io_out[0] = 1'b0;
assign io_oeb[0] = 1'b1;
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[19] = la_data_in[127];
assign la_data_out[127] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[19];
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[20] = la_data_in[126];
assign la_data_out[126] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[20];
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[21] = la_data_in[125];
assign la_data_out[125] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[21];
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[22] = la_data_in[124];
assign la_data_out[124] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[22];
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[23] = la_data_in[123];
assign la_data_out[123] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[23];
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[24] = la_data_in[122];
assign la_data_out[122] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[24];
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[25] = la_data_in[121];
assign la_data_out[121] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[25];
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[26] = la_data_in[120];
assign la_data_out[120] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[26];
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[27] = la_data_in[119];
assign la_data_out[119] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[27];
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[28] = la_data_in[118];
assign la_data_out[118] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[28];
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[29] = la_data_in[117];
assign la_data_out[117] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[29];
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[30] = la_data_in[116];
sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_30_DEMUX_WB (.TE_B(wb_la_switch_b), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[30]), .Z(wbs_dat_o[0]));
sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_30_DEMUX_LA (.TE_B(wb_la_switch), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[30]), .Z(la_data_out[116]));
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[31] = la_data_in[115];
sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_31_DEMUX_WB (.TE_B(wb_la_switch_b), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[31]), .Z(wbs_dat_o[1]));
sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_31_DEMUX_LA (.TE_B(wb_la_switch), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[31]), .Z(la_data_out[115]));
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[32] = la_data_in[114];
sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_32_DEMUX_WB (.TE_B(wb_la_switch_b), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[32]), .Z(wbs_dat_o[2]));
sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_32_DEMUX_LA (.TE_B(wb_la_switch), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[32]), .Z(la_data_out[114]));
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[33] = la_data_in[113];
sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_33_DEMUX_WB (.TE_B(wb_la_switch_b), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[33]), .Z(wbs_dat_o[3]));
sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_33_DEMUX_LA (.TE_B(wb_la_switch), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[33]), .Z(la_data_out[113]));
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[34] = la_data_in[112];
sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_34_DEMUX_WB (.TE_B(wb_la_switch_b), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[34]), .Z(wbs_dat_o[4]));
sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_34_DEMUX_LA (.TE_B(wb_la_switch), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[34]), .Z(la_data_out[112]));
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[35] = la_data_in[111];
sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_35_DEMUX_WB (.TE_B(wb_la_switch_b), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[35]), .Z(wbs_dat_o[5]));
sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_35_DEMUX_LA (.TE_B(wb_la_switch), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[35]), .Z(la_data_out[111]));
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[36] = la_data_in[110];
sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_36_DEMUX_WB (.TE_B(wb_la_switch_b), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[36]), .Z(wbs_dat_o[6]));
sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_36_DEMUX_LA (.TE_B(wb_la_switch), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[36]), .Z(la_data_out[110]));
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[37] = la_data_in[109];
sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_37_DEMUX_WB (.TE_B(wb_la_switch_b), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[37]), .Z(wbs_dat_o[7]));
sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_37_DEMUX_LA (.TE_B(wb_la_switch), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[37]), .Z(la_data_out[109]));
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[38] = la_data_in[108];
sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_38_DEMUX_WB (.TE_B(wb_la_switch_b), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[38]), .Z(wbs_dat_o[8]));
sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_38_DEMUX_LA (.TE_B(wb_la_switch), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[38]), .Z(la_data_out[108]));
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[39] = la_data_in[107];
sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_39_DEMUX_WB (.TE_B(wb_la_switch_b), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[39]), .Z(wbs_dat_o[9]));
sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_39_DEMUX_LA (.TE_B(wb_la_switch), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[39]), .Z(la_data_out[107]));
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[40] = la_data_in[106];
sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_40_DEMUX_WB (.TE_B(wb_la_switch_b), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[40]), .Z(wbs_dat_o[10]));
sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_40_DEMUX_LA (.TE_B(wb_la_switch), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[40]), .Z(la_data_out[106]));
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[41] = la_data_in[105];
sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_41_DEMUX_WB (.TE_B(wb_la_switch_b), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[41]), .Z(wbs_dat_o[11]));
sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_41_DEMUX_LA (.TE_B(wb_la_switch), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[41]), .Z(la_data_out[105]));
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[42] = la_data_in[104];
sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_42_DEMUX_WB (.TE_B(wb_la_switch_b), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[42]), .Z(wbs_dat_o[12]));
sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_42_DEMUX_LA (.TE_B(wb_la_switch), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[42]), .Z(la_data_out[104]));
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[43] = la_data_in[103];
sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_43_DEMUX_WB (.TE_B(wb_la_switch_b), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[43]), .Z(wbs_dat_o[13]));
sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_43_DEMUX_LA (.TE_B(wb_la_switch), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[43]), .Z(la_data_out[103]));
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[44] = la_data_in[102];
sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_44_DEMUX_WB (.TE_B(wb_la_switch_b), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[44]), .Z(wbs_dat_o[14]));
sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_44_DEMUX_LA (.TE_B(wb_la_switch), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[44]), .Z(la_data_out[102]));
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[45] = la_data_in[101];
sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_45_DEMUX_WB (.TE_B(wb_la_switch_b), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[45]), .Z(wbs_dat_o[15]));
sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_45_DEMUX_LA (.TE_B(wb_la_switch), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[45]), .Z(la_data_out[101]));
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[46] = la_data_in[100];
sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_46_DEMUX_WB (.TE_B(wb_la_switch_b), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[46]), .Z(wbs_dat_o[16]));
sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_46_DEMUX_LA (.TE_B(wb_la_switch), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[46]), .Z(la_data_out[100]));
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[47] = la_data_in[99];
sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_47_DEMUX_WB (.TE_B(wb_la_switch_b), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[47]), .Z(wbs_dat_o[17]));
sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_47_DEMUX_LA (.TE_B(wb_la_switch), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[47]), .Z(la_data_out[99]));
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[48] = la_data_in[98];
sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_48_DEMUX_WB (.TE_B(wb_la_switch_b), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[48]), .Z(wbs_dat_o[18]));
sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_48_DEMUX_LA (.TE_B(wb_la_switch), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[48]), .Z(la_data_out[98]));
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[49] = la_data_in[97];
sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_49_DEMUX_WB (.TE_B(wb_la_switch_b), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[49]), .Z(wbs_dat_o[19]));
sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_49_DEMUX_LA (.TE_B(wb_la_switch), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[49]), .Z(la_data_out[97]));
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[50] = la_data_in[96];
sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_50_DEMUX_WB (.TE_B(wb_la_switch_b), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[50]), .Z(wbs_dat_o[20]));
sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_50_DEMUX_LA (.TE_B(wb_la_switch), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[50]), .Z(la_data_out[96]));
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[51] = la_data_in[95];
sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_51_DEMUX_WB (.TE_B(wb_la_switch_b), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[51]), .Z(wbs_dat_o[21]));
sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_51_DEMUX_LA (.TE_B(wb_la_switch), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[51]), .Z(la_data_out[95]));
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[52] = la_data_in[94];
sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_52_DEMUX_WB (.TE_B(wb_la_switch_b), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[52]), .Z(wbs_dat_o[22]));
sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_52_DEMUX_LA (.TE_B(wb_la_switch), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[52]), .Z(la_data_out[94]));
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[53] = la_data_in[93];
sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_53_DEMUX_WB (.TE_B(wb_la_switch_b), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[53]), .Z(wbs_dat_o[23]));
sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_53_DEMUX_LA (.TE_B(wb_la_switch), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[53]), .Z(la_data_out[93]));
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[54] = la_data_in[92];
sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_54_DEMUX_WB (.TE_B(wb_la_switch_b), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[54]), .Z(wbs_dat_o[24]));
sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_54_DEMUX_LA (.TE_B(wb_la_switch), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[54]), .Z(la_data_out[92]));
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[55] = la_data_in[91];
sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_55_DEMUX_WB (.TE_B(wb_la_switch_b), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[55]), .Z(wbs_dat_o[25]));
sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_55_DEMUX_LA (.TE_B(wb_la_switch), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[55]), .Z(la_data_out[91]));
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[56] = la_data_in[90];
sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_56_DEMUX_WB (.TE_B(wb_la_switch_b), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[56]), .Z(wbs_dat_o[26]));
sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_56_DEMUX_LA (.TE_B(wb_la_switch), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[56]), .Z(la_data_out[90]));
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[57] = la_data_in[89];
sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_57_DEMUX_WB (.TE_B(wb_la_switch_b), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[57]), .Z(wbs_dat_o[27]));
sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_57_DEMUX_LA (.TE_B(wb_la_switch), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[57]), .Z(la_data_out[89]));
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[58] = la_data_in[88];
sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_58_DEMUX_WB (.TE_B(wb_la_switch_b), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[58]), .Z(wbs_dat_o[28]));
sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_58_DEMUX_LA (.TE_B(wb_la_switch), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[58]), .Z(la_data_out[88]));
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[59] = la_data_in[87];
sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_59_DEMUX_WB (.TE_B(wb_la_switch_b), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[59]), .Z(wbs_dat_o[29]));
sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_59_DEMUX_LA (.TE_B(wb_la_switch), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[59]), .Z(la_data_out[87]));
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[60] = la_data_in[86];
sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_60_DEMUX_WB (.TE_B(wb_la_switch_b), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[60]), .Z(wbs_dat_o[30]));
sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_60_DEMUX_LA (.TE_B(wb_la_switch), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[60]), .Z(la_data_out[86]));
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[61] = la_data_in[85];
sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_61_DEMUX_WB (.TE_B(wb_la_switch_b), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[61]), .Z(wbs_dat_o[31]));
sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_61_DEMUX_LA (.TE_B(wb_la_switch), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[61]), .Z(la_data_out[85]));
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_62_MUX (.S(wb_la_switch), .A1(wbs_dat_i[0]), .A0(la_data_in[84]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[62]));
assign la_data_out[84] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[62];
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_63_MUX (.S(wb_la_switch), .A1(wbs_dat_i[1]), .A0(la_data_in[83]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[63]));
assign la_data_out[83] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[63];
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_64_MUX (.S(wb_la_switch), .A1(wbs_dat_i[2]), .A0(la_data_in[82]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[64]));
assign la_data_out[82] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[64];
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_65_MUX (.S(wb_la_switch), .A1(wbs_dat_i[3]), .A0(la_data_in[81]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[65]));
assign la_data_out[81] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[65];
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_66_MUX (.S(wb_la_switch), .A1(wbs_dat_i[4]), .A0(la_data_in[80]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[66]));
assign la_data_out[80] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[66];
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_67_MUX (.S(wb_la_switch), .A1(wbs_dat_i[5]), .A0(la_data_in[79]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[67]));
assign la_data_out[79] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[67];
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_68_MUX (.S(wb_la_switch), .A1(wbs_dat_i[6]), .A0(la_data_in[78]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[68]));
assign la_data_out[78] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[68];
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_69_MUX (.S(wb_la_switch), .A1(wbs_dat_i[7]), .A0(la_data_in[77]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[69]));
assign la_data_out[77] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[69];
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_70_MUX (.S(wb_la_switch), .A1(wbs_dat_i[8]), .A0(la_data_in[76]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[70]));
assign la_data_out[76] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[70];
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_71_MUX (.S(wb_la_switch), .A1(wbs_dat_i[9]), .A0(la_data_in[75]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[71]));
assign la_data_out[75] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[71];
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_72_MUX (.S(wb_la_switch), .A1(wbs_dat_i[10]), .A0(la_data_in[74]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[72]));
assign la_data_out[74] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[72];
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_73_MUX (.S(wb_la_switch), .A1(wbs_dat_i[11]), .A0(la_data_in[73]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[73]));
assign la_data_out[73] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[73];
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_74_MUX (.S(wb_la_switch), .A1(wbs_dat_i[12]), .A0(la_data_in[72]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[74]));
assign la_data_out[72] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[74];
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_75_MUX (.S(wb_la_switch), .A1(wbs_dat_i[13]), .A0(la_data_in[71]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[75]));
assign la_data_out[71] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[75];
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_76_MUX (.S(wb_la_switch), .A1(wbs_dat_i[14]), .A0(la_data_in[70]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[76]));
assign la_data_out[70] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[76];
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_77_MUX (.S(wb_la_switch), .A1(wbs_dat_i[15]), .A0(la_data_in[69]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[77]));
assign la_data_out[69] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[77];
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_78_MUX (.S(wb_la_switch), .A1(wbs_dat_i[16]), .A0(la_data_in[68]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[78]));
assign la_data_out[68] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[78];
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_79_MUX (.S(wb_la_switch), .A1(wbs_dat_i[17]), .A0(la_data_in[67]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[79]));
assign la_data_out[67] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[79];
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_80_MUX (.S(wb_la_switch), .A1(wbs_dat_i[18]), .A0(la_data_in[66]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[80]));
assign la_data_out[66] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[80];
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_81_MUX (.S(wb_la_switch), .A1(wbs_dat_i[19]), .A0(la_data_in[65]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[81]));
assign la_data_out[65] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[81];
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_82_MUX (.S(wb_la_switch), .A1(wbs_dat_i[20]), .A0(la_data_in[64]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[82]));
assign la_data_out[64] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[82];
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_83_MUX (.S(wb_la_switch), .A1(wbs_dat_i[21]), .A0(la_data_in[63]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[83]));
assign la_data_out[63] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[83];
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_84_MUX (.S(wb_la_switch), .A1(wbs_dat_i[22]), .A0(la_data_in[62]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[84]));
assign la_data_out[62] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[84];
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_85_MUX (.S(wb_la_switch), .A1(wbs_dat_i[23]), .A0(la_data_in[61]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[85]));
assign la_data_out[61] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[85];
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_86_MUX (.S(wb_la_switch), .A1(wbs_dat_i[24]), .A0(la_data_in[60]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[86]));
assign la_data_out[60] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[86];
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_87_MUX (.S(wb_la_switch), .A1(wbs_dat_i[25]), .A0(la_data_in[59]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[87]));
assign la_data_out[59] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[87];
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_88_MUX (.S(wb_la_switch), .A1(wbs_dat_i[26]), .A0(la_data_in[58]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[88]));
assign la_data_out[58] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[88];
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_89_MUX (.S(wb_la_switch), .A1(wbs_dat_i[27]), .A0(la_data_in[57]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[89]));
assign la_data_out[57] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[89];
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_90_MUX (.S(wb_la_switch), .A1(wbs_dat_i[28]), .A0(la_data_in[56]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[90]));
assign la_data_out[56] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[90];
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_91_MUX (.S(wb_la_switch), .A1(wbs_dat_i[29]), .A0(la_data_in[55]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[91]));
assign la_data_out[55] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[91];
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_92_MUX (.S(wb_la_switch), .A1(wbs_dat_i[30]), .A0(la_data_in[54]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[92]));
assign la_data_out[54] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[92];
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_93_MUX (.S(wb_la_switch), .A1(wbs_dat_i[31]), .A0(la_data_in[53]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[93]));
assign la_data_out[53] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[93];
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_94_MUX (.S(wb_la_switch), .A1(wbs_adr_i[0]), .A0(la_data_in[52]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[94]));
assign la_data_out[52] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[94];
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_95_MUX (.S(wb_la_switch), .A1(wbs_adr_i[1]), .A0(la_data_in[51]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[95]));
assign la_data_out[51] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[95];
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_96_MUX (.S(wb_la_switch), .A1(wbs_adr_i[2]), .A0(la_data_in[50]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[96]));
assign la_data_out[50] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[96];
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_97_MUX (.S(wb_la_switch), .A1(wbs_adr_i[3]), .A0(la_data_in[49]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[97]));
assign la_data_out[49] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[97];
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_98_MUX (.S(wb_la_switch), .A1(wbs_adr_i[4]), .A0(la_data_in[48]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[98]));
assign la_data_out[48] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[98];
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_99_MUX (.S(wb_la_switch), .A1(wbs_adr_i[5]), .A0(la_data_in[47]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[99]));
assign la_data_out[47] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[99];
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_100_MUX (.S(wb_la_switch), .A1(wbs_adr_i[6]), .A0(la_data_in[46]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[100]));
assign la_data_out[46] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[100];
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_101_MUX (.S(wb_la_switch), .A1(wbs_adr_i[7]), .A0(la_data_in[45]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[101]));
assign la_data_out[45] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[101];
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_102_MUX (.S(wb_la_switch), .A1(wbs_adr_i[8]), .A0(la_data_in[44]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[102]));
assign la_data_out[44] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[102];
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_103_MUX (.S(wb_la_switch), .A1(wbs_adr_i[9]), .A0(la_data_in[43]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[103]));
assign la_data_out[43] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[103];
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_104_MUX (.S(wb_la_switch), .A1(wbs_adr_i[10]), .A0(la_data_in[42]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[104]));
assign la_data_out[42] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[104];
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_105_MUX (.S(wb_la_switch), .A1(wbs_adr_i[11]), .A0(la_data_in[41]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[105]));
assign la_data_out[41] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[105];
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_106_MUX (.S(wb_la_switch), .A1(wbs_adr_i[12]), .A0(la_data_in[40]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[106]));
assign la_data_out[40] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[106];
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_107_MUX (.S(wb_la_switch), .A1(wbs_adr_i[13]), .A0(la_data_in[39]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[107]));
assign la_data_out[39] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[107];
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_108_MUX (.S(wb_la_switch), .A1(wbs_adr_i[14]), .A0(la_data_in[38]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[108]));
assign la_data_out[38] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[108];
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_109_MUX (.S(wb_la_switch), .A1(wbs_adr_i[15]), .A0(la_data_in[37]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[109]));
assign la_data_out[37] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[109];
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_110_MUX (.S(wb_la_switch), .A1(wbs_adr_i[16]), .A0(la_data_in[36]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[110]));
assign la_data_out[36] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[110];
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_111_MUX (.S(wb_la_switch), .A1(wbs_adr_i[17]), .A0(la_data_in[35]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[111]));
assign la_data_out[35] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[111];
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_112_MUX (.S(wb_la_switch), .A1(wbs_adr_i[18]), .A0(la_data_in[34]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[112]));
assign la_data_out[34] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[112];
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_113_MUX (.S(wb_la_switch), .A1(wbs_adr_i[19]), .A0(la_data_in[33]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[113]));
assign la_data_out[33] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[113];
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_114_MUX (.S(wb_la_switch), .A1(wbs_adr_i[20]), .A0(la_data_in[32]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[114]));
assign la_data_out[32] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[114];
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_115_MUX (.S(wb_la_switch), .A1(wbs_adr_i[21]), .A0(la_data_in[31]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[115]));
assign la_data_out[31] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[115];
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_116_MUX (.S(wb_la_switch), .A1(wbs_adr_i[22]), .A0(la_data_in[30]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[116]));
assign la_data_out[30] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[116];
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_117_MUX (.S(wb_la_switch), .A1(wbs_adr_i[23]), .A0(la_data_in[29]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[117]));
assign la_data_out[29] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[117];
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_118_MUX (.S(wb_la_switch), .A1(wbs_adr_i[24]), .A0(la_data_in[28]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[118]));
assign la_data_out[28] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[118];
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_119_MUX (.S(wb_la_switch), .A1(wbs_adr_i[25]), .A0(la_data_in[27]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[119]));
assign la_data_out[27] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[119];
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_120_MUX (.S(wb_la_switch), .A1(wbs_adr_i[26]), .A0(la_data_in[26]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[120]));
assign la_data_out[26] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[120];
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_121_MUX (.S(wb_la_switch), .A1(wbs_adr_i[27]), .A0(la_data_in[25]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[121]));
assign la_data_out[25] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[121];
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_122_MUX (.S(wb_la_switch), .A1(wbs_adr_i[28]), .A0(la_data_in[24]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[122]));
assign la_data_out[24] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[122];
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_123_MUX (.S(wb_la_switch), .A1(wbs_adr_i[29]), .A0(la_data_in[23]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[123]));
assign la_data_out[23] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[123];
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_124_MUX (.S(wb_la_switch), .A1(wbs_adr_i[30]), .A0(la_data_in[22]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[124]));
assign la_data_out[22] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[124];
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_125_MUX (.S(wb_la_switch), .A1(wbs_adr_i[31]), .A0(la_data_in[21]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[125]));
assign la_data_out[21] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[125];
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_126_MUX (.S(wb_la_switch), .A1(wbs_sel_i[0]), .A0(la_data_in[20]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[126]));
assign la_data_out[20] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[126];
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_127_MUX (.S(wb_la_switch), .A1(wbs_sel_i[1]), .A0(la_data_in[19]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[127]));
assign la_data_out[19] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[127];
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_128_MUX (.S(wb_la_switch), .A1(wbs_sel_i[2]), .A0(la_data_in[18]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[128]));
assign la_data_out[18] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[128];
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_129_MUX (.S(wb_la_switch), .A1(wbs_sel_i[3]), .A0(la_data_in[17]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[129]));
assign la_data_out[17] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[129];
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_130_MUX (.S(wb_la_switch), .A1(wbs_we_i), .A0(la_data_in[16]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[130]));
assign la_data_out[16] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[130];
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_131_MUX (.S(wb_la_switch), .A1(wbs_stb_i), .A0(la_data_in[15]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[131]));
assign la_data_out[15] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[131];
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_132_MUX (.S(wb_la_switch), .A1(wbs_cyc_i), .A0(la_data_in[14]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[132]));
assign la_data_out[14] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[132];
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[133] = la_data_in[13];
sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_133_DEMUX_WB (.TE_B(wb_la_switch_b), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[133]), .Z(wbs_ack_o));
sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_133_DEMUX_LA (.TE_B(wb_la_switch), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[133]), .Z(la_data_out[13]));
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_134_MUX (.S(wb_la_switch), .A1(wb_rst_i), .A0(la_data_in[12]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[134]));
assign la_data_out[12] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[134];
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_135_MUX (.S(wb_la_switch), .A1(wb_clk_i), .A0(la_data_in[11]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[135]));
assign la_data_out[11] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[135];
assign prog_clk = io_in[37];
assign io_out[37] = 1'b0;
assign io_oeb[37] = 1'b1;
assign clk = io_in[36];
assign io_out[36] = 1'b0;
assign io_oeb[36] = 1'b1;
assign io_out[35] = ccff_tail;
assign io_oeb[35] = 1'b0;
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[136] = io_in[34];
assign io_out[34] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[136];
assign io_oeb[34] = gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[136];
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[137] = io_in[33];
assign io_out[33] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[137];
assign io_oeb[33] = gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[137];
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[138] = io_in[32];
assign io_out[32] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[138];
assign io_oeb[32] = gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[138];
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[139] = io_in[31];
assign io_out[31] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[139];
assign io_oeb[31] = gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[139];
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[140] = io_in[30];
assign io_out[30] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[140];
assign io_oeb[30] = gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[140];
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[141] = io_in[29];
assign io_out[29] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[141];
assign io_oeb[29] = gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[141];
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[142] = io_in[28];
assign io_out[28] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[142];
assign io_oeb[28] = gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[142];
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[143] = io_in[27];
assign io_out[27] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[143];
assign io_oeb[27] = gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[143];
assign sc_head = io_in[26];
assign io_out[26] = 1'b0;
assign io_oeb[26] = 1'b1;
//
//
//
assign wb_la_switch = io_in[25];
assign io_out[25] = 1'b0;
assign io_oeb[25] = 1'b1;
//
fpga_core fpga_core_uut(
.prog_clk(prog_clk),
.Test_en(Test_en),
.clk(clk),
.IO_ISOL_N(IO_ISOL_N),
.gfpga_pad_EMBEDDED_IO_HD_SOC_IN(gfpga_pad_EMBEDDED_IO_HD_SOC_IN),
.gfpga_pad_EMBEDDED_IO_HD_SOC_OUT(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT),
.gfpga_pad_EMBEDDED_IO_HD_SOC_DIR(gfpga_pad_EMBEDDED_IO_HD_SOC_DIR),
.ccff_head(ccff_head),
.ccff_tail(ccff_tail),
.sc_head(sc_head),
.sc_tail(sc_tail),
.pReset(pReset),
.Reset(Reset)
);
endmodule

20
SOFA_A/SOFA_A_task/sc_verilog/sky130_fd_sc_hd_wrapper .v Normal file
View File

@ -0,0 +1,20 @@
`timescale 1ns/1ps
//
//
//
module sky130_fd_sc_hd__mux2_1_wrapper (
input A0,
input A1,
input S,
output X
);
sky130_fd_sc_hd__mux2_1 MUX2 (.A0(A0),
.A1(A1),
.S(S),
.X(X)
);
endmodule

1219
SOFA_A/SOFA_A_task/user_project_wrapper_empty.def Normal file
View File

File diff suppressed because it is too large Load Diff

3768
SOFA_A/SOFA_A_task/user_project_wrapper_template.def Normal file
View File

File diff suppressed because it is too large Load Diff

64
SOFA_A/SOFA_A_verilog/fabric_netlists.v Normal file
View File

@ -0,0 +1,64 @@
//-------------------------------------------
// FPGA Synthesizable Verilog Netlist
// Description: Fabric Netlist Summary
// Author: Xifan TANG
// Organization: University of Utah
// Date: Sun Feb 19 10:53:27 2023
//-------------------------------------------
//----- Time scale -----
`timescale 1ns / 1ps
// ------ Include defines: preproc flags -----
`include "./SRC/fpga_defines.v"
// ------ Include user-defined netlists -----
`include "/research/ece/lnis/Share/OpenFPGA_VTR/openfpga_flow/tasks/FPGA22_HIER_SKY_PNR/skywater/libraries/sky130_fd_sc_hd/latest/cells/inv/sky130_fd_sc_hd__inv_1.v"
`include "/research/ece/lnis/Share/OpenFPGA_VTR/openfpga_flow/tasks/FPGA22_HIER_SKY_PNR/skywater/libraries/sky130_fd_sc_hd/latest/cells/buf/sky130_fd_sc_hd__buf_2.v"
`include "/research/ece/lnis/Share/OpenFPGA_VTR/openfpga_flow/tasks/FPGA22_HIER_SKY_PNR/skywater/libraries/sky130_fd_sc_hd/latest/cells/buf/sky130_fd_sc_hd__buf_4.v"
`include "/research/ece/lnis/Share/OpenFPGA_VTR/openfpga_flow/tasks/FPGA22_HIER_SKY_PNR/skywater/libraries/sky130_fd_sc_hd/latest/cells/inv/sky130_fd_sc_hd__inv_2.v"
`include "/research/ece/lnis/Share/OpenFPGA_VTR/openfpga_flow/tasks/FPGA22_HIER_SKY_PNR/skywater/libraries/sky130_fd_sc_hd/latest/cells/or2/sky130_fd_sc_hd__or2_1.v"
`include "/research/ece/lnis/Share/OpenFPGA_VTR/openfpga_flow/tasks/FPGA22_HIER_SKY_PNR/skywater/libraries/sky130_fd_sc_hd/latest/cells/mux2/sky130_fd_sc_hd__mux2_1.v"
`include "/research/ece/lnis/Share/OpenFPGA_VTR/openfpga_flow/tasks/FPGA22_HIER_SKY_PNR/skywater/libraries/sky130_fd_sc_hd/latest/cells/sdfrtp/sky130_fd_sc_hd__sdfrtp_1.v"
`include "/research/ece/lnis/Share/OpenFPGA_VTR/openfpga_flow/tasks/FPGA22_HIER_SKY_PNR/skywater/libraries/sky130_fd_sc_hd/latest/cells/dfrtp/sky130_fd_sc_hd__dfrtp_1.v"
`include "/research/ece/lnis/Share/OpenFPGA_VTR/openfpga_flow/tasks/FPGA22_HIER_SKY_PNR/sc_verilog/digital_io_hd.v"
`include "/research/ece/lnis/Share/OpenFPGA_VTR/openfpga_flow/tasks/FPGA22_HIER_SKY_PNR/sc_verilog/sky130_fd_sc_hd_wrapper.v"
// ------ Include primitive module netlists -----
`include "./SRC/sub_module/inv_buf_passgate.v"
`include "./SRC/sub_module/arch_encoder.v"
`include "./SRC/sub_module/local_encoder.v"
`include "./SRC/sub_module/mux_primitives.v"
`include "./SRC/sub_module/muxes.v"
`include "./SRC/sub_module/luts.v"
`include "./SRC/sub_module/wires.v"
`include "./SRC/sub_module/memories.v"
`include "./SRC/sub_module/shift_register_banks.v"
// ------ Include logic block netlists -----
`include "./SRC/lb/logical_tile_io_mode_physical__iopad.v"
`include "./SRC/lb/logical_tile_io_mode_io_.v"
`include "./SRC/lb/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4.v"
`include "./SRC/lb/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__carry_follower.v"
`include "./SRC/lb/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic.v"
`include "./SRC/lb/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff.v"
`include "./SRC/lb/logical_tile_clb_mode_default__fle_mode_physical__fabric.v"
`include "./SRC/lb/logical_tile_clb_mode_default__fle.v"
`include "./SRC/lb/logical_tile_clb_mode_clb_.v"
`include "./SRC/lb/grid_io_top_top.v"
`include "./SRC/lb/grid_io_right_right.v"
`include "./SRC/lb/grid_io_bottom_bottom.v"
`include "./SRC/lb/grid_io_left_left.v"
`include "./SRC/lb/grid_clb.v"
// ------ Include routing module netlists -----
`include "./SRC/routing/sb_0__0_.v"
`include "./SRC/routing/sb_0__1_.v"
`include "./SRC/routing/sb_1__0_.v"
`include "./SRC/routing/sb_1__1_.v"
`include "./SRC/routing/cbx_1__0_.v"
`include "./SRC/routing/cbx_1__1_.v"
`include "./SRC/routing/cby_0__1_.v"
`include "./SRC/routing/cby_1__1_.v"
// ------ Include fabric top-level netlists -----
`include "./SRC/fpga_top.v"

12
SOFA_A/SOFA_A_verilog/fpga_defines.v Normal file
View File

@ -0,0 +1,12 @@
//-------------------------------------------
// FPGA Synthesizable Verilog Netlist
// Description: Preprocessing flags to enable/disable features in FPGA Verilog modules
// Author: Xifan TANG
// Organization: University of Utah
// Date: Sun Feb 19 10:53:27 2023
//-------------------------------------------
//----- Time scale -----
`timescale 1ns / 1ps
`define ENABLE_TIMING 1

580
SOFA_A/SOFA_A_verilog/fpga_top.v Normal file
View File

@ -0,0 +1,580 @@
//-------------------------------------------
// FPGA Synthesizable Verilog Netlist
// Description: Top-level Verilog module for FPGA
// Author: Xifan TANG
// Organization: University of Utah
// Date: Sun Feb 19 10:53:27 2023
//-------------------------------------------
//----- Time scale -----
`timescale 1ns / 1ps
//----- Default net type -----
`default_nettype none
// ----- Verilog module for fpga_top -----
module fpga_top(clk,
Reset,
IO_ISOL_N,
pReset,
prog_clk,
Test_en,
gfpga_pad_EMBEDDED_IO_HD_SOC_IN,
gfpga_pad_EMBEDDED_IO_HD_SOC_OUT,
gfpga_pad_EMBEDDED_IO_HD_SOC_DIR,
ccff_head,
ccff_tail);
//----- GLOBAL PORTS -----
input [0:0] clk;
//----- GLOBAL PORTS -----
input [0:0] Reset;
//----- GLOBAL PORTS -----
input [0:0] IO_ISOL_N;
//----- GLOBAL PORTS -----
input [0:0] pReset;
//----- GLOBAL PORTS -----
input [0:0] prog_clk;
//----- GLOBAL PORTS -----
input [0:0] Test_en;
//----- GPIN PORTS -----
input [0:25] gfpga_pad_EMBEDDED_IO_HD_SOC_IN;
//----- GPOUT PORTS -----
output [0:25] gfpga_pad_EMBEDDED_IO_HD_SOC_OUT;
//----- GPOUT PORTS -----
output [0:25] gfpga_pad_EMBEDDED_IO_HD_SOC_DIR;
//----- INPUT PORTS -----
input [0:0] ccff_head;
//----- OUTPUT PORTS -----
output [0:0] ccff_tail;
//----- BEGIN wire-connection ports -----
//----- END wire-connection ports -----
//----- BEGIN Registered ports -----
//----- END Registered ports -----
wire [0:0] cbx_1__0__0_bottom_grid_top_width_0_height_0_subtile_0__pin_outpad_0_;
wire [0:0] cbx_1__0__0_bottom_grid_top_width_0_height_0_subtile_1__pin_outpad_0_;
wire [0:0] cbx_1__0__0_bottom_grid_top_width_0_height_0_subtile_2__pin_outpad_0_;
wire [0:0] cbx_1__0__0_bottom_grid_top_width_0_height_0_subtile_3__pin_outpad_0_;
wire [0:0] cbx_1__0__0_bottom_grid_top_width_0_height_0_subtile_4__pin_outpad_0_;
wire [0:0] cbx_1__0__0_bottom_grid_top_width_0_height_0_subtile_5__pin_outpad_0_;
wire [0:0] cbx_1__0__0_bottom_grid_top_width_0_height_0_subtile_6__pin_outpad_0_;
wire [0:0] cbx_1__0__0_bottom_grid_top_width_0_height_0_subtile_7__pin_outpad_0_;
wire [0:0] cbx_1__0__0_bottom_grid_top_width_0_height_0_subtile_8__pin_outpad_0_;
wire [0:0] cbx_1__0__0_ccff_tail;
wire [0:10] cbx_1__0__0_chanx_left_out;
wire [0:10] cbx_1__0__0_chanx_right_out;
wire [0:0] cbx_1__1__0_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_;
wire [0:0] cbx_1__1__0_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_;
wire [0:0] cbx_1__1__0_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_;
wire [0:0] cbx_1__1__0_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_;
wire [0:0] cbx_1__1__0_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_;
wire [0:0] cbx_1__1__0_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_;
wire [0:0] cbx_1__1__0_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_;
wire [0:0] cbx_1__1__0_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_;
wire [0:0] cbx_1__1__0_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_;
wire [0:0] cbx_1__1__0_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_;
wire [0:0] cbx_1__1__0_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_;
wire [0:0] cbx_1__1__0_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_;
wire [0:0] cbx_1__1__0_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_;
wire [0:0] cbx_1__1__0_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_;
wire [0:0] cbx_1__1__0_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_;
wire [0:0] cbx_1__1__0_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_;
wire [0:0] cbx_1__1__0_ccff_tail;
wire [0:10] cbx_1__1__0_chanx_left_out;
wire [0:10] cbx_1__1__0_chanx_right_out;
wire [0:0] cbx_1__1__0_top_grid_bottom_width_0_height_0_subtile_0__pin_outpad_0_;
wire [0:0] cbx_1__1__0_top_grid_bottom_width_0_height_0_subtile_1__pin_outpad_0_;
wire [0:0] cbx_1__1__0_top_grid_bottom_width_0_height_0_subtile_2__pin_outpad_0_;
wire [0:0] cbx_1__1__0_top_grid_bottom_width_0_height_0_subtile_3__pin_outpad_0_;
wire [0:0] cbx_1__1__0_top_grid_bottom_width_0_height_0_subtile_4__pin_outpad_0_;
wire [0:0] cbx_1__1__0_top_grid_bottom_width_0_height_0_subtile_5__pin_outpad_0_;
wire [0:0] cbx_1__1__0_top_grid_bottom_width_0_height_0_subtile_6__pin_outpad_0_;
wire [0:0] cbx_1__1__0_top_grid_bottom_width_0_height_0_subtile_7__pin_outpad_0_;
wire [0:0] cby_0__1__0_ccff_tail;
wire [0:10] cby_0__1__0_chany_bottom_out;
wire [0:10] cby_0__1__0_chany_top_out;
wire [0:0] cby_0__1__0_left_grid_right_width_0_height_0_subtile_0__pin_outpad_0_;
wire [0:0] cby_1__1__0_ccff_tail;
wire [0:10] cby_1__1__0_chany_bottom_out;
wire [0:10] cby_1__1__0_chany_top_out;
wire [0:0] cby_1__1__0_left_grid_right_width_0_height_0_subtile_0__pin_I4_0_;
wire [0:0] cby_1__1__0_left_grid_right_width_0_height_0_subtile_0__pin_I4_1_;
wire [0:0] cby_1__1__0_left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_;
wire [0:0] cby_1__1__0_left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_;
wire [0:0] cby_1__1__0_left_grid_right_width_0_height_0_subtile_0__pin_I5_0_;
wire [0:0] cby_1__1__0_left_grid_right_width_0_height_0_subtile_0__pin_I5_1_;
wire [0:0] cby_1__1__0_left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_;
wire [0:0] cby_1__1__0_left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_;
wire [0:0] cby_1__1__0_left_grid_right_width_0_height_0_subtile_0__pin_I6_0_;
wire [0:0] cby_1__1__0_left_grid_right_width_0_height_0_subtile_0__pin_I6_1_;
wire [0:0] cby_1__1__0_left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_;
wire [0:0] cby_1__1__0_left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_;
wire [0:0] cby_1__1__0_left_grid_right_width_0_height_0_subtile_0__pin_I7_0_;
wire [0:0] cby_1__1__0_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_;
wire [0:0] cby_1__1__0_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_;
wire [0:0] cby_1__1__0_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_;
wire [0:0] cby_1__1__0_right_grid_left_width_0_height_0_subtile_0__pin_outpad_0_;
wire [0:0] cby_1__1__0_right_grid_left_width_0_height_0_subtile_1__pin_outpad_0_;
wire [0:0] cby_1__1__0_right_grid_left_width_0_height_0_subtile_2__pin_outpad_0_;
wire [0:0] cby_1__1__0_right_grid_left_width_0_height_0_subtile_3__pin_outpad_0_;
wire [0:0] cby_1__1__0_right_grid_left_width_0_height_0_subtile_4__pin_outpad_0_;
wire [0:0] cby_1__1__0_right_grid_left_width_0_height_0_subtile_5__pin_outpad_0_;
wire [0:0] cby_1__1__0_right_grid_left_width_0_height_0_subtile_6__pin_outpad_0_;
wire [0:0] cby_1__1__0_right_grid_left_width_0_height_0_subtile_7__pin_outpad_0_;
wire [0:0] grid_clb_0_right_width_0_height_0_subtile_0__pin_O_10_;
wire [0:0] grid_clb_0_right_width_0_height_0_subtile_0__pin_O_11_;
wire [0:0] grid_clb_0_right_width_0_height_0_subtile_0__pin_O_12_;
wire [0:0] grid_clb_0_right_width_0_height_0_subtile_0__pin_O_13_;
wire [0:0] grid_clb_0_right_width_0_height_0_subtile_0__pin_O_14_;
wire [0:0] grid_clb_0_right_width_0_height_0_subtile_0__pin_O_8_;
wire [0:0] grid_clb_0_right_width_0_height_0_subtile_0__pin_O_9_;
wire [0:0] grid_clb_0_top_width_0_height_0_subtile_0__pin_O_0_;
wire [0:0] grid_clb_0_top_width_0_height_0_subtile_0__pin_O_1_;
wire [0:0] grid_clb_0_top_width_0_height_0_subtile_0__pin_O_2_;
wire [0:0] grid_clb_0_top_width_0_height_0_subtile_0__pin_O_3_;
wire [0:0] grid_clb_0_top_width_0_height_0_subtile_0__pin_O_4_;
wire [0:0] grid_clb_0_top_width_0_height_0_subtile_0__pin_O_5_;
wire [0:0] grid_clb_0_top_width_0_height_0_subtile_0__pin_O_6_;
wire [0:0] grid_clb_0_top_width_0_height_0_subtile_0__pin_O_7_;
wire [0:0] grid_clb_1__1__undriven_bottom_width_0_height_0_subtile_0__pin_cout_0_;
wire [0:0] grid_clb_1__1__undriven_bottom_width_0_height_0_subtile_0__pin_reg_out_0_;
wire [0:0] grid_clb_1__1__undriven_bottom_width_0_height_0_subtile_0__pin_sc_out_0_;
wire [0:0] grid_clb_1__1__undriven_right_width_0_height_0_subtile_0__pin_O_15_;
wire [0:0] grid_clb_1__1__undriven_top_width_0_height_0_subtile_0__pin_cin_0_;
wire [0:0] grid_clb_1__1__undriven_top_width_0_height_0_subtile_0__pin_reg_in_0_;
wire [0:0] grid_clb_1__1__undriven_top_width_0_height_0_subtile_0__pin_sc_in_0_;
wire [0:0] grid_io_bottom_bottom_0_ccff_tail;
wire [0:0] grid_io_bottom_bottom_0_top_width_0_height_0_subtile_0__pin_inpad_0_;
wire [0:0] grid_io_bottom_bottom_0_top_width_0_height_0_subtile_1__pin_inpad_0_;
wire [0:0] grid_io_bottom_bottom_0_top_width_0_height_0_subtile_2__pin_inpad_0_;
wire [0:0] grid_io_bottom_bottom_0_top_width_0_height_0_subtile_3__pin_inpad_0_;
wire [0:0] grid_io_bottom_bottom_0_top_width_0_height_0_subtile_4__pin_inpad_0_;
wire [0:0] grid_io_bottom_bottom_0_top_width_0_height_0_subtile_5__pin_inpad_0_;
wire [0:0] grid_io_bottom_bottom_0_top_width_0_height_0_subtile_6__pin_inpad_0_;
wire [0:0] grid_io_bottom_bottom_0_top_width_0_height_0_subtile_7__pin_inpad_0_;
wire [0:0] grid_io_bottom_bottom_0_top_width_0_height_0_subtile_8__pin_inpad_0_;
wire [0:0] grid_io_left_left_0_ccff_tail;
wire [0:0] grid_io_left_left_0_right_width_0_height_0_subtile_0__pin_inpad_0_;
wire [0:0] grid_io_right_right_0_ccff_tail;
wire [0:0] grid_io_right_right_0_left_width_0_height_0_subtile_0__pin_inpad_0_;
wire [0:0] grid_io_right_right_0_left_width_0_height_0_subtile_1__pin_inpad_0_;
wire [0:0] grid_io_right_right_0_left_width_0_height_0_subtile_2__pin_inpad_0_;
wire [0:0] grid_io_right_right_0_left_width_0_height_0_subtile_3__pin_inpad_0_;
wire [0:0] grid_io_right_right_0_left_width_0_height_0_subtile_4__pin_inpad_0_;
wire [0:0] grid_io_right_right_0_left_width_0_height_0_subtile_5__pin_inpad_0_;
wire [0:0] grid_io_right_right_0_left_width_0_height_0_subtile_6__pin_inpad_0_;
wire [0:0] grid_io_right_right_0_left_width_0_height_0_subtile_7__pin_inpad_0_;
wire [0:0] grid_io_top_top_0_bottom_width_0_height_0_subtile_0__pin_inpad_0_;
wire [0:0] grid_io_top_top_0_bottom_width_0_height_0_subtile_1__pin_inpad_0_;
wire [0:0] grid_io_top_top_0_bottom_width_0_height_0_subtile_2__pin_inpad_0_;
wire [0:0] grid_io_top_top_0_bottom_width_0_height_0_subtile_3__pin_inpad_0_;
wire [0:0] grid_io_top_top_0_bottom_width_0_height_0_subtile_4__pin_inpad_0_;
wire [0:0] grid_io_top_top_0_bottom_width_0_height_0_subtile_5__pin_inpad_0_;
wire [0:0] grid_io_top_top_0_bottom_width_0_height_0_subtile_6__pin_inpad_0_;
wire [0:0] grid_io_top_top_0_bottom_width_0_height_0_subtile_7__pin_inpad_0_;
wire [0:0] grid_io_top_top_0_ccff_tail;
wire [0:0] sb_0__0__0_ccff_tail;
wire [0:10] sb_0__0__0_chanx_right_out;
wire [0:10] sb_0__0__0_chany_top_out;
wire [0:0] sb_0__1__0_ccff_tail;
wire [0:10] sb_0__1__0_chanx_right_out;
wire [0:10] sb_0__1__0_chany_bottom_out;
wire [0:0] sb_1__0__0_ccff_tail;
wire [0:10] sb_1__0__0_chanx_left_out;
wire [0:10] sb_1__0__0_chany_top_out;
wire [0:0] sb_1__1__0_ccff_tail;
wire [0:10] sb_1__1__0_chanx_left_out;
wire [0:10] sb_1__1__0_chany_bottom_out;
// ----- BEGIN Local short connections -----
// ----- END Local short connections -----
// ----- BEGIN Local output short connections -----
// ----- END Local output short connections -----
grid_io_top_top grid_io_top_top_1__2_ (
.IO_ISOL_N(IO_ISOL_N),
.pReset(pReset),
.prog_clk(prog_clk),
.gfpga_pad_EMBEDDED_IO_HD_SOC_IN(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[0:7]),
.gfpga_pad_EMBEDDED_IO_HD_SOC_OUT(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[0:7]),
.gfpga_pad_EMBEDDED_IO_HD_SOC_DIR(gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[0:7]),
.bottom_width_0_height_0_subtile_0__pin_outpad_0_(cbx_1__1__0_top_grid_bottom_width_0_height_0_subtile_0__pin_outpad_0_),
.bottom_width_0_height_0_subtile_1__pin_outpad_0_(cbx_1__1__0_top_grid_bottom_width_0_height_0_subtile_1__pin_outpad_0_),
.bottom_width_0_height_0_subtile_2__pin_outpad_0_(cbx_1__1__0_top_grid_bottom_width_0_height_0_subtile_2__pin_outpad_0_),
.bottom_width_0_height_0_subtile_3__pin_outpad_0_(cbx_1__1__0_top_grid_bottom_width_0_height_0_subtile_3__pin_outpad_0_),
.bottom_width_0_height_0_subtile_4__pin_outpad_0_(cbx_1__1__0_top_grid_bottom_width_0_height_0_subtile_4__pin_outpad_0_),
.bottom_width_0_height_0_subtile_5__pin_outpad_0_(cbx_1__1__0_top_grid_bottom_width_0_height_0_subtile_5__pin_outpad_0_),
.bottom_width_0_height_0_subtile_6__pin_outpad_0_(cbx_1__1__0_top_grid_bottom_width_0_height_0_subtile_6__pin_outpad_0_),
.bottom_width_0_height_0_subtile_7__pin_outpad_0_(cbx_1__1__0_top_grid_bottom_width_0_height_0_subtile_7__pin_outpad_0_),
.ccff_head(cbx_1__1__0_ccff_tail),
.bottom_width_0_height_0_subtile_0__pin_inpad_0_(grid_io_top_top_0_bottom_width_0_height_0_subtile_0__pin_inpad_0_),
.bottom_width_0_height_0_subtile_1__pin_inpad_0_(grid_io_top_top_0_bottom_width_0_height_0_subtile_1__pin_inpad_0_),
.bottom_width_0_height_0_subtile_2__pin_inpad_0_(grid_io_top_top_0_bottom_width_0_height_0_subtile_2__pin_inpad_0_),
.bottom_width_0_height_0_subtile_3__pin_inpad_0_(grid_io_top_top_0_bottom_width_0_height_0_subtile_3__pin_inpad_0_),
.bottom_width_0_height_0_subtile_4__pin_inpad_0_(grid_io_top_top_0_bottom_width_0_height_0_subtile_4__pin_inpad_0_),
.bottom_width_0_height_0_subtile_5__pin_inpad_0_(grid_io_top_top_0_bottom_width_0_height_0_subtile_5__pin_inpad_0_),
.bottom_width_0_height_0_subtile_6__pin_inpad_0_(grid_io_top_top_0_bottom_width_0_height_0_subtile_6__pin_inpad_0_),
.bottom_width_0_height_0_subtile_7__pin_inpad_0_(grid_io_top_top_0_bottom_width_0_height_0_subtile_7__pin_inpad_0_),
.ccff_tail(grid_io_top_top_0_ccff_tail));
grid_io_right_right grid_io_right_right_2__1_ (
.IO_ISOL_N(IO_ISOL_N),
.pReset(pReset),
.prog_clk(prog_clk),
.gfpga_pad_EMBEDDED_IO_HD_SOC_IN(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[8:15]),
.gfpga_pad_EMBEDDED_IO_HD_SOC_OUT(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[8:15]),
.gfpga_pad_EMBEDDED_IO_HD_SOC_DIR(gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[8:15]),
.left_width_0_height_0_subtile_0__pin_outpad_0_(cby_1__1__0_right_grid_left_width_0_height_0_subtile_0__pin_outpad_0_),
.left_width_0_height_0_subtile_1__pin_outpad_0_(cby_1__1__0_right_grid_left_width_0_height_0_subtile_1__pin_outpad_0_),
.left_width_0_height_0_subtile_2__pin_outpad_0_(cby_1__1__0_right_grid_left_width_0_height_0_subtile_2__pin_outpad_0_),
.left_width_0_height_0_subtile_3__pin_outpad_0_(cby_1__1__0_right_grid_left_width_0_height_0_subtile_3__pin_outpad_0_),
.left_width_0_height_0_subtile_4__pin_outpad_0_(cby_1__1__0_right_grid_left_width_0_height_0_subtile_4__pin_outpad_0_),
.left_width_0_height_0_subtile_5__pin_outpad_0_(cby_1__1__0_right_grid_left_width_0_height_0_subtile_5__pin_outpad_0_),
.left_width_0_height_0_subtile_6__pin_outpad_0_(cby_1__1__0_right_grid_left_width_0_height_0_subtile_6__pin_outpad_0_),
.left_width_0_height_0_subtile_7__pin_outpad_0_(cby_1__1__0_right_grid_left_width_0_height_0_subtile_7__pin_outpad_0_),
.ccff_head(grid_io_bottom_bottom_0_ccff_tail),
.left_width_0_height_0_subtile_0__pin_inpad_0_(grid_io_right_right_0_left_width_0_height_0_subtile_0__pin_inpad_0_),
.left_width_0_height_0_subtile_1__pin_inpad_0_(grid_io_right_right_0_left_width_0_height_0_subtile_1__pin_inpad_0_),
.left_width_0_height_0_subtile_2__pin_inpad_0_(grid_io_right_right_0_left_width_0_height_0_subtile_2__pin_inpad_0_),
.left_width_0_height_0_subtile_3__pin_inpad_0_(grid_io_right_right_0_left_width_0_height_0_subtile_3__pin_inpad_0_),
.left_width_0_height_0_subtile_4__pin_inpad_0_(grid_io_right_right_0_left_width_0_height_0_subtile_4__pin_inpad_0_),
.left_width_0_height_0_subtile_5__pin_inpad_0_(grid_io_right_right_0_left_width_0_height_0_subtile_5__pin_inpad_0_),
.left_width_0_height_0_subtile_6__pin_inpad_0_(grid_io_right_right_0_left_width_0_height_0_subtile_6__pin_inpad_0_),
.left_width_0_height_0_subtile_7__pin_inpad_0_(grid_io_right_right_0_left_width_0_height_0_subtile_7__pin_inpad_0_),
.ccff_tail(grid_io_right_right_0_ccff_tail));
grid_io_bottom_bottom grid_io_bottom_bottom_1__0_ (
.IO_ISOL_N(IO_ISOL_N),
.pReset(pReset),
.prog_clk(prog_clk),
.gfpga_pad_EMBEDDED_IO_HD_SOC_IN(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[16:24]),
.gfpga_pad_EMBEDDED_IO_HD_SOC_OUT(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[16:24]),
.gfpga_pad_EMBEDDED_IO_HD_SOC_DIR(gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[16:24]),
.top_width_0_height_0_subtile_0__pin_outpad_0_(cbx_1__0__0_bottom_grid_top_width_0_height_0_subtile_0__pin_outpad_0_),
.top_width_0_height_0_subtile_1__pin_outpad_0_(cbx_1__0__0_bottom_grid_top_width_0_height_0_subtile_1__pin_outpad_0_),
.top_width_0_height_0_subtile_2__pin_outpad_0_(cbx_1__0__0_bottom_grid_top_width_0_height_0_subtile_2__pin_outpad_0_),
.top_width_0_height_0_subtile_3__pin_outpad_0_(cbx_1__0__0_bottom_grid_top_width_0_height_0_subtile_3__pin_outpad_0_),
.top_width_0_height_0_subtile_4__pin_outpad_0_(cbx_1__0__0_bottom_grid_top_width_0_height_0_subtile_4__pin_outpad_0_),
.top_width_0_height_0_subtile_5__pin_outpad_0_(cbx_1__0__0_bottom_grid_top_width_0_height_0_subtile_5__pin_outpad_0_),
.top_width_0_height_0_subtile_6__pin_outpad_0_(cbx_1__0__0_bottom_grid_top_width_0_height_0_subtile_6__pin_outpad_0_),
.top_width_0_height_0_subtile_7__pin_outpad_0_(cbx_1__0__0_bottom_grid_top_width_0_height_0_subtile_7__pin_outpad_0_),
.top_width_0_height_0_subtile_8__pin_outpad_0_(cbx_1__0__0_bottom_grid_top_width_0_height_0_subtile_8__pin_outpad_0_),
.ccff_head(ccff_head),
.top_width_0_height_0_subtile_0__pin_inpad_0_(grid_io_bottom_bottom_0_top_width_0_height_0_subtile_0__pin_inpad_0_),
.top_width_0_height_0_subtile_1__pin_inpad_0_(grid_io_bottom_bottom_0_top_width_0_height_0_subtile_1__pin_inpad_0_),
.top_width_0_height_0_subtile_2__pin_inpad_0_(grid_io_bottom_bottom_0_top_width_0_height_0_subtile_2__pin_inpad_0_),
.top_width_0_height_0_subtile_3__pin_inpad_0_(grid_io_bottom_bottom_0_top_width_0_height_0_subtile_3__pin_inpad_0_),
.top_width_0_height_0_subtile_4__pin_inpad_0_(grid_io_bottom_bottom_0_top_width_0_height_0_subtile_4__pin_inpad_0_),
.top_width_0_height_0_subtile_5__pin_inpad_0_(grid_io_bottom_bottom_0_top_width_0_height_0_subtile_5__pin_inpad_0_),
.top_width_0_height_0_subtile_6__pin_inpad_0_(grid_io_bottom_bottom_0_top_width_0_height_0_subtile_6__pin_inpad_0_),
.top_width_0_height_0_subtile_7__pin_inpad_0_(grid_io_bottom_bottom_0_top_width_0_height_0_subtile_7__pin_inpad_0_),
.top_width_0_height_0_subtile_8__pin_inpad_0_(grid_io_bottom_bottom_0_top_width_0_height_0_subtile_8__pin_inpad_0_),
.ccff_tail(grid_io_bottom_bottom_0_ccff_tail));
grid_io_left_left grid_io_left_left_0__1_ (
.IO_ISOL_N(IO_ISOL_N),
.pReset(pReset),
.prog_clk(prog_clk),
.gfpga_pad_EMBEDDED_IO_HD_SOC_IN(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[25]),
.gfpga_pad_EMBEDDED_IO_HD_SOC_OUT(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[25]),
.gfpga_pad_EMBEDDED_IO_HD_SOC_DIR(gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[25]),
.right_width_0_height_0_subtile_0__pin_outpad_0_(cby_0__1__0_left_grid_right_width_0_height_0_subtile_0__pin_outpad_0_),
.ccff_head(cby_0__1__0_ccff_tail),
.right_width_0_height_0_subtile_0__pin_inpad_0_(grid_io_left_left_0_right_width_0_height_0_subtile_0__pin_inpad_0_),
.ccff_tail(grid_io_left_left_0_ccff_tail));
grid_clb grid_clb_1__1_ (
.pReset(pReset),
.prog_clk(prog_clk),
.Test_en(Test_en),
.top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__1__0_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_),
.top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__1__0_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_),
.top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__1__0_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_),
.top_width_0_height_0_subtile_0__pin_I0i_1_(cbx_1__1__0_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_),
.top_width_0_height_0_subtile_0__pin_I1_0_(cbx_1__1__0_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_),
.top_width_0_height_0_subtile_0__pin_I1_1_(cbx_1__1__0_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_),
.top_width_0_height_0_subtile_0__pin_I1i_0_(cbx_1__1__0_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_),
.top_width_0_height_0_subtile_0__pin_I1i_1_(cbx_1__1__0_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_),
.top_width_0_height_0_subtile_0__pin_I2_0_(cbx_1__1__0_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_),
.top_width_0_height_0_subtile_0__pin_I2_1_(cbx_1__1__0_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_),
.top_width_0_height_0_subtile_0__pin_I2i_0_(cbx_1__1__0_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_),
.top_width_0_height_0_subtile_0__pin_I2i_1_(cbx_1__1__0_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_),
.top_width_0_height_0_subtile_0__pin_I3_0_(cbx_1__1__0_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_),
.top_width_0_height_0_subtile_0__pin_I3_1_(cbx_1__1__0_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_),
.top_width_0_height_0_subtile_0__pin_I3i_0_(cbx_1__1__0_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_),
.top_width_0_height_0_subtile_0__pin_I3i_1_(cbx_1__1__0_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_),
.top_width_0_height_0_subtile_0__pin_reg_in_0_(grid_clb_1__1__undriven_top_width_0_height_0_subtile_0__pin_reg_in_0_),
.top_width_0_height_0_subtile_0__pin_sc_in_0_(grid_clb_1__1__undriven_top_width_0_height_0_subtile_0__pin_sc_in_0_),
.top_width_0_height_0_subtile_0__pin_cin_0_(grid_clb_1__1__undriven_top_width_0_height_0_subtile_0__pin_cin_0_),
.right_width_0_height_0_subtile_0__pin_I4_0_(cby_1__1__0_left_grid_right_width_0_height_0_subtile_0__pin_I4_0_),
.right_width_0_height_0_subtile_0__pin_I4_1_(cby_1__1__0_left_grid_right_width_0_height_0_subtile_0__pin_I4_1_),
.right_width_0_height_0_subtile_0__pin_I4i_0_(cby_1__1__0_left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_),
.right_width_0_height_0_subtile_0__pin_I4i_1_(cby_1__1__0_left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_),
.right_width_0_height_0_subtile_0__pin_I5_0_(cby_1__1__0_left_grid_right_width_0_height_0_subtile_0__pin_I5_0_),
.right_width_0_height_0_subtile_0__pin_I5_1_(cby_1__1__0_left_grid_right_width_0_height_0_subtile_0__pin_I5_1_),
.right_width_0_height_0_subtile_0__pin_I5i_0_(cby_1__1__0_left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_),
.right_width_0_height_0_subtile_0__pin_I5i_1_(cby_1__1__0_left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_),
.right_width_0_height_0_subtile_0__pin_I6_0_(cby_1__1__0_left_grid_right_width_0_height_0_subtile_0__pin_I6_0_),
.right_width_0_height_0_subtile_0__pin_I6_1_(cby_1__1__0_left_grid_right_width_0_height_0_subtile_0__pin_I6_1_),
.right_width_0_height_0_subtile_0__pin_I6i_0_(cby_1__1__0_left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_),
.right_width_0_height_0_subtile_0__pin_I6i_1_(cby_1__1__0_left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_),
.right_width_0_height_0_subtile_0__pin_I7_0_(cby_1__1__0_left_grid_right_width_0_height_0_subtile_0__pin_I7_0_),
.right_width_0_height_0_subtile_0__pin_I7_1_(cby_1__1__0_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_),
.right_width_0_height_0_subtile_0__pin_I7i_0_(cby_1__1__0_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_),
.right_width_0_height_0_subtile_0__pin_I7i_1_(cby_1__1__0_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_),
.left_width_0_height_0_subtile_0__pin_reset_0_(Reset),
.left_width_0_height_0_subtile_0__pin_clk_0_(clk),
.ccff_head(cby_1__1__0_ccff_tail),
.top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_0_top_width_0_height_0_subtile_0__pin_O_0_),
.top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_0_top_width_0_height_0_subtile_0__pin_O_1_),
.top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_0_top_width_0_height_0_subtile_0__pin_O_2_),
.top_width_0_height_0_subtile_0__pin_O_3_(grid_clb_0_top_width_0_height_0_subtile_0__pin_O_3_),
.top_width_0_height_0_subtile_0__pin_O_4_(grid_clb_0_top_width_0_height_0_subtile_0__pin_O_4_),
.top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_0_top_width_0_height_0_subtile_0__pin_O_5_),
.top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_0_top_width_0_height_0_subtile_0__pin_O_6_),
.top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_0_top_width_0_height_0_subtile_0__pin_O_7_),
.right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_0_right_width_0_height_0_subtile_0__pin_O_8_),
.right_width_0_height_0_subtile_0__pin_O_9_(grid_clb_0_right_width_0_height_0_subtile_0__pin_O_9_),
.right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_0_right_width_0_height_0_subtile_0__pin_O_10_),
.right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_0_right_width_0_height_0_subtile_0__pin_O_11_),
.right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_0_right_width_0_height_0_subtile_0__pin_O_12_),
.right_width_0_height_0_subtile_0__pin_O_13_(grid_clb_0_right_width_0_height_0_subtile_0__pin_O_13_),
.right_width_0_height_0_subtile_0__pin_O_14_(grid_clb_0_right_width_0_height_0_subtile_0__pin_O_14_),
.right_width_0_height_0_subtile_0__pin_O_15_(grid_clb_1__1__undriven_right_width_0_height_0_subtile_0__pin_O_15_),
.bottom_width_0_height_0_subtile_0__pin_reg_out_0_(grid_clb_1__1__undriven_bottom_width_0_height_0_subtile_0__pin_reg_out_0_),
.bottom_width_0_height_0_subtile_0__pin_sc_out_0_(grid_clb_1__1__undriven_bottom_width_0_height_0_subtile_0__pin_sc_out_0_),
.bottom_width_0_height_0_subtile_0__pin_cout_0_(grid_clb_1__1__undriven_bottom_width_0_height_0_subtile_0__pin_cout_0_),
.ccff_tail(ccff_tail));
sb_0__0_ sb_0__0_ (
.pReset(pReset),
.prog_clk(prog_clk),
.chany_top_in(cby_0__1__0_chany_bottom_out[0:10]),
.top_left_grid_right_width_0_height_0_subtile_0__pin_inpad_0_(grid_io_left_left_0_right_width_0_height_0_subtile_0__pin_inpad_0_),
.chanx_right_in(cbx_1__0__0_chanx_left_out[0:10]),
.right_bottom_grid_top_width_0_height_0_subtile_0__pin_inpad_0_(grid_io_bottom_bottom_0_top_width_0_height_0_subtile_0__pin_inpad_0_),
.right_bottom_grid_top_width_0_height_0_subtile_1__pin_inpad_0_(grid_io_bottom_bottom_0_top_width_0_height_0_subtile_1__pin_inpad_0_),
.right_bottom_grid_top_width_0_height_0_subtile_2__pin_inpad_0_(grid_io_bottom_bottom_0_top_width_0_height_0_subtile_2__pin_inpad_0_),
.right_bottom_grid_top_width_0_height_0_subtile_3__pin_inpad_0_(grid_io_bottom_bottom_0_top_width_0_height_0_subtile_3__pin_inpad_0_),
.right_bottom_grid_top_width_0_height_0_subtile_4__pin_inpad_0_(grid_io_bottom_bottom_0_top_width_0_height_0_subtile_4__pin_inpad_0_),
.right_bottom_grid_top_width_0_height_0_subtile_5__pin_inpad_0_(grid_io_bottom_bottom_0_top_width_0_height_0_subtile_5__pin_inpad_0_),
.right_bottom_grid_top_width_0_height_0_subtile_6__pin_inpad_0_(grid_io_bottom_bottom_0_top_width_0_height_0_subtile_6__pin_inpad_0_),
.right_bottom_grid_top_width_0_height_0_subtile_7__pin_inpad_0_(grid_io_bottom_bottom_0_top_width_0_height_0_subtile_7__pin_inpad_0_),
.right_bottom_grid_top_width_0_height_0_subtile_8__pin_inpad_0_(grid_io_bottom_bottom_0_top_width_0_height_0_subtile_8__pin_inpad_0_),
.ccff_head(sb_0__1__0_ccff_tail),
.chany_top_out(sb_0__0__0_chany_top_out[0:10]),
.chanx_right_out(sb_0__0__0_chanx_right_out[0:10]),
.ccff_tail(sb_0__0__0_ccff_tail));
sb_0__1_ sb_0__1_ (
.pReset(pReset),
.prog_clk(prog_clk),
.chanx_right_in(cbx_1__1__0_chanx_left_out[0:10]),
.right_top_grid_bottom_width_0_height_0_subtile_0__pin_inpad_0_(grid_io_top_top_0_bottom_width_0_height_0_subtile_0__pin_inpad_0_),
.right_top_grid_bottom_width_0_height_0_subtile_1__pin_inpad_0_(grid_io_top_top_0_bottom_width_0_height_0_subtile_1__pin_inpad_0_),
.right_top_grid_bottom_width_0_height_0_subtile_2__pin_inpad_0_(grid_io_top_top_0_bottom_width_0_height_0_subtile_2__pin_inpad_0_),
.right_top_grid_bottom_width_0_height_0_subtile_3__pin_inpad_0_(grid_io_top_top_0_bottom_width_0_height_0_subtile_3__pin_inpad_0_),
.right_top_grid_bottom_width_0_height_0_subtile_4__pin_inpad_0_(grid_io_top_top_0_bottom_width_0_height_0_subtile_4__pin_inpad_0_),
.right_top_grid_bottom_width_0_height_0_subtile_5__pin_inpad_0_(grid_io_top_top_0_bottom_width_0_height_0_subtile_5__pin_inpad_0_),
.right_top_grid_bottom_width_0_height_0_subtile_6__pin_inpad_0_(grid_io_top_top_0_bottom_width_0_height_0_subtile_6__pin_inpad_0_),
.right_top_grid_bottom_width_0_height_0_subtile_7__pin_inpad_0_(grid_io_top_top_0_bottom_width_0_height_0_subtile_7__pin_inpad_0_),
.right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_0_top_width_0_height_0_subtile_0__pin_O_0_),
.right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_0_top_width_0_height_0_subtile_0__pin_O_1_),
.right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_0_top_width_0_height_0_subtile_0__pin_O_2_),
.right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_(grid_clb_0_top_width_0_height_0_subtile_0__pin_O_3_),
.right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_(grid_clb_0_top_width_0_height_0_subtile_0__pin_O_4_),
.right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_0_top_width_0_height_0_subtile_0__pin_O_5_),
.right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_0_top_width_0_height_0_subtile_0__pin_O_6_),
.right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_0_top_width_0_height_0_subtile_0__pin_O_7_),
.chany_bottom_in(cby_0__1__0_chany_top_out[0:10]),
.bottom_left_grid_right_width_0_height_0_subtile_0__pin_inpad_0_(grid_io_left_left_0_right_width_0_height_0_subtile_0__pin_inpad_0_),
.ccff_head(grid_io_top_top_0_ccff_tail),
.chanx_right_out(sb_0__1__0_chanx_right_out[0:10]),
.chany_bottom_out(sb_0__1__0_chany_bottom_out[0:10]),
.ccff_tail(sb_0__1__0_ccff_tail));
sb_1__0_ sb_1__0_ (
.pReset(pReset),
.prog_clk(prog_clk),
.chany_top_in(cby_1__1__0_chany_bottom_out[0:10]),
.top_left_grid_right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_0_right_width_0_height_0_subtile_0__pin_O_8_),
.top_left_grid_right_width_0_height_0_subtile_0__pin_O_9_(grid_clb_0_right_width_0_height_0_subtile_0__pin_O_9_),
.top_left_grid_right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_0_right_width_0_height_0_subtile_0__pin_O_10_),
.top_left_grid_right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_0_right_width_0_height_0_subtile_0__pin_O_11_),
.top_left_grid_right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_0_right_width_0_height_0_subtile_0__pin_O_12_),
.top_left_grid_right_width_0_height_0_subtile_0__pin_O_13_(grid_clb_0_right_width_0_height_0_subtile_0__pin_O_13_),
.top_left_grid_right_width_0_height_0_subtile_0__pin_O_14_(grid_clb_0_right_width_0_height_0_subtile_0__pin_O_14_),
.top_right_grid_left_width_0_height_0_subtile_0__pin_inpad_0_(grid_io_right_right_0_left_width_0_height_0_subtile_0__pin_inpad_0_),
.top_right_grid_left_width_0_height_0_subtile_1__pin_inpad_0_(grid_io_right_right_0_left_width_0_height_0_subtile_1__pin_inpad_0_),
.top_right_grid_left_width_0_height_0_subtile_2__pin_inpad_0_(grid_io_right_right_0_left_width_0_height_0_subtile_2__pin_inpad_0_),
.top_right_grid_left_width_0_height_0_subtile_3__pin_inpad_0_(grid_io_right_right_0_left_width_0_height_0_subtile_3__pin_inpad_0_),
.top_right_grid_left_width_0_height_0_subtile_4__pin_inpad_0_(grid_io_right_right_0_left_width_0_height_0_subtile_4__pin_inpad_0_),
.top_right_grid_left_width_0_height_0_subtile_5__pin_inpad_0_(grid_io_right_right_0_left_width_0_height_0_subtile_5__pin_inpad_0_),
.top_right_grid_left_width_0_height_0_subtile_6__pin_inpad_0_(grid_io_right_right_0_left_width_0_height_0_subtile_6__pin_inpad_0_),
.top_right_grid_left_width_0_height_0_subtile_7__pin_inpad_0_(grid_io_right_right_0_left_width_0_height_0_subtile_7__pin_inpad_0_),
.chanx_left_in(cbx_1__0__0_chanx_right_out[0:10]),
.left_bottom_grid_top_width_0_height_0_subtile_0__pin_inpad_0_(grid_io_bottom_bottom_0_top_width_0_height_0_subtile_0__pin_inpad_0_),
.left_bottom_grid_top_width_0_height_0_subtile_1__pin_inpad_0_(grid_io_bottom_bottom_0_top_width_0_height_0_subtile_1__pin_inpad_0_),
.left_bottom_grid_top_width_0_height_0_subtile_2__pin_inpad_0_(grid_io_bottom_bottom_0_top_width_0_height_0_subtile_2__pin_inpad_0_),
.left_bottom_grid_top_width_0_height_0_subtile_3__pin_inpad_0_(grid_io_bottom_bottom_0_top_width_0_height_0_subtile_3__pin_inpad_0_),
.left_bottom_grid_top_width_0_height_0_subtile_4__pin_inpad_0_(grid_io_bottom_bottom_0_top_width_0_height_0_subtile_4__pin_inpad_0_),
.left_bottom_grid_top_width_0_height_0_subtile_5__pin_inpad_0_(grid_io_bottom_bottom_0_top_width_0_height_0_subtile_5__pin_inpad_0_),
.left_bottom_grid_top_width_0_height_0_subtile_6__pin_inpad_0_(grid_io_bottom_bottom_0_top_width_0_height_0_subtile_6__pin_inpad_0_),
.left_bottom_grid_top_width_0_height_0_subtile_7__pin_inpad_0_(grid_io_bottom_bottom_0_top_width_0_height_0_subtile_7__pin_inpad_0_),
.left_bottom_grid_top_width_0_height_0_subtile_8__pin_inpad_0_(grid_io_bottom_bottom_0_top_width_0_height_0_subtile_8__pin_inpad_0_),
.ccff_head(grid_io_left_left_0_ccff_tail),
.chany_top_out(sb_1__0__0_chany_top_out[0:10]),
.chanx_left_out(sb_1__0__0_chanx_left_out[0:10]),
.ccff_tail(sb_1__0__0_ccff_tail));
sb_1__1_ sb_1__1_ (
.pReset(pReset),
.prog_clk(prog_clk),
.chany_bottom_in(cby_1__1__0_chany_top_out[0:10]),
.bottom_right_grid_left_width_0_height_0_subtile_0__pin_inpad_0_(grid_io_right_right_0_left_width_0_height_0_subtile_0__pin_inpad_0_),
.bottom_right_grid_left_width_0_height_0_subtile_1__pin_inpad_0_(grid_io_right_right_0_left_width_0_height_0_subtile_1__pin_inpad_0_),
.bottom_right_grid_left_width_0_height_0_subtile_2__pin_inpad_0_(grid_io_right_right_0_left_width_0_height_0_subtile_2__pin_inpad_0_),
.bottom_right_grid_left_width_0_height_0_subtile_3__pin_inpad_0_(grid_io_right_right_0_left_width_0_height_0_subtile_3__pin_inpad_0_),
.bottom_right_grid_left_width_0_height_0_subtile_4__pin_inpad_0_(grid_io_right_right_0_left_width_0_height_0_subtile_4__pin_inpad_0_),
.bottom_right_grid_left_width_0_height_0_subtile_5__pin_inpad_0_(grid_io_right_right_0_left_width_0_height_0_subtile_5__pin_inpad_0_),
.bottom_right_grid_left_width_0_height_0_subtile_6__pin_inpad_0_(grid_io_right_right_0_left_width_0_height_0_subtile_6__pin_inpad_0_),
.bottom_right_grid_left_width_0_height_0_subtile_7__pin_inpad_0_(grid_io_right_right_0_left_width_0_height_0_subtile_7__pin_inpad_0_),
.bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_0_right_width_0_height_0_subtile_0__pin_O_8_),
.bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_9_(grid_clb_0_right_width_0_height_0_subtile_0__pin_O_9_),
.bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_0_right_width_0_height_0_subtile_0__pin_O_10_),
.bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_0_right_width_0_height_0_subtile_0__pin_O_11_),
.bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_0_right_width_0_height_0_subtile_0__pin_O_12_),
.bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_13_(grid_clb_0_right_width_0_height_0_subtile_0__pin_O_13_),
.bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_14_(grid_clb_0_right_width_0_height_0_subtile_0__pin_O_14_),
.chanx_left_in(cbx_1__1__0_chanx_right_out[0:10]),
.left_top_grid_bottom_width_0_height_0_subtile_0__pin_inpad_0_(grid_io_top_top_0_bottom_width_0_height_0_subtile_0__pin_inpad_0_),
.left_top_grid_bottom_width_0_height_0_subtile_1__pin_inpad_0_(grid_io_top_top_0_bottom_width_0_height_0_subtile_1__pin_inpad_0_),
.left_top_grid_bottom_width_0_height_0_subtile_2__pin_inpad_0_(grid_io_top_top_0_bottom_width_0_height_0_subtile_2__pin_inpad_0_),
.left_top_grid_bottom_width_0_height_0_subtile_3__pin_inpad_0_(grid_io_top_top_0_bottom_width_0_height_0_subtile_3__pin_inpad_0_),
.left_top_grid_bottom_width_0_height_0_subtile_4__pin_inpad_0_(grid_io_top_top_0_bottom_width_0_height_0_subtile_4__pin_inpad_0_),
.left_top_grid_bottom_width_0_height_0_subtile_5__pin_inpad_0_(grid_io_top_top_0_bottom_width_0_height_0_subtile_5__pin_inpad_0_),
.left_top_grid_bottom_width_0_height_0_subtile_6__pin_inpad_0_(grid_io_top_top_0_bottom_width_0_height_0_subtile_6__pin_inpad_0_),
.left_top_grid_bottom_width_0_height_0_subtile_7__pin_inpad_0_(grid_io_top_top_0_bottom_width_0_height_0_subtile_7__pin_inpad_0_),
.left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_0_top_width_0_height_0_subtile_0__pin_O_0_),
.left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_0_top_width_0_height_0_subtile_0__pin_O_1_),
.left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_0_top_width_0_height_0_subtile_0__pin_O_2_),
.left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_(grid_clb_0_top_width_0_height_0_subtile_0__pin_O_3_),
.left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_(grid_clb_0_top_width_0_height_0_subtile_0__pin_O_4_),
.left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_0_top_width_0_height_0_subtile_0__pin_O_5_),
.left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_0_top_width_0_height_0_subtile_0__pin_O_6_),
.left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_0_top_width_0_height_0_subtile_0__pin_O_7_),
.ccff_head(grid_io_right_right_0_ccff_tail),
.chany_bottom_out(sb_1__1__0_chany_bottom_out[0:10]),
.chanx_left_out(sb_1__1__0_chanx_left_out[0:10]),
.ccff_tail(sb_1__1__0_ccff_tail));
cbx_1__0_ cbx_1__0_ (
.pReset(pReset),
.prog_clk(prog_clk),
.chanx_left_in(sb_0__0__0_chanx_right_out[0:10]),
.chanx_right_in(sb_1__0__0_chanx_left_out[0:10]),
.ccff_head(sb_1__0__0_ccff_tail),
.chanx_left_out(cbx_1__0__0_chanx_left_out[0:10]),
.chanx_right_out(cbx_1__0__0_chanx_right_out[0:10]),
.bottom_grid_top_width_0_height_0_subtile_0__pin_outpad_0_(cbx_1__0__0_bottom_grid_top_width_0_height_0_subtile_0__pin_outpad_0_),
.bottom_grid_top_width_0_height_0_subtile_1__pin_outpad_0_(cbx_1__0__0_bottom_grid_top_width_0_height_0_subtile_1__pin_outpad_0_),
.bottom_grid_top_width_0_height_0_subtile_2__pin_outpad_0_(cbx_1__0__0_bottom_grid_top_width_0_height_0_subtile_2__pin_outpad_0_),
.bottom_grid_top_width_0_height_0_subtile_3__pin_outpad_0_(cbx_1__0__0_bottom_grid_top_width_0_height_0_subtile_3__pin_outpad_0_),
.bottom_grid_top_width_0_height_0_subtile_4__pin_outpad_0_(cbx_1__0__0_bottom_grid_top_width_0_height_0_subtile_4__pin_outpad_0_),
.bottom_grid_top_width_0_height_0_subtile_5__pin_outpad_0_(cbx_1__0__0_bottom_grid_top_width_0_height_0_subtile_5__pin_outpad_0_),
.bottom_grid_top_width_0_height_0_subtile_6__pin_outpad_0_(cbx_1__0__0_bottom_grid_top_width_0_height_0_subtile_6__pin_outpad_0_),
.bottom_grid_top_width_0_height_0_subtile_7__pin_outpad_0_(cbx_1__0__0_bottom_grid_top_width_0_height_0_subtile_7__pin_outpad_0_),
.bottom_grid_top_width_0_height_0_subtile_8__pin_outpad_0_(cbx_1__0__0_bottom_grid_top_width_0_height_0_subtile_8__pin_outpad_0_),
.ccff_tail(cbx_1__0__0_ccff_tail));
cbx_1__1_ cbx_1__1_ (
.pReset(pReset),
.prog_clk(prog_clk),
.chanx_left_in(sb_0__1__0_chanx_right_out[0:10]),
.chanx_right_in(sb_1__1__0_chanx_left_out[0:10]),
.ccff_head(sb_1__1__0_ccff_tail),
.chanx_left_out(cbx_1__1__0_chanx_left_out[0:10]),
.chanx_right_out(cbx_1__1__0_chanx_right_out[0:10]),
.top_grid_bottom_width_0_height_0_subtile_0__pin_outpad_0_(cbx_1__1__0_top_grid_bottom_width_0_height_0_subtile_0__pin_outpad_0_),
.top_grid_bottom_width_0_height_0_subtile_1__pin_outpad_0_(cbx_1__1__0_top_grid_bottom_width_0_height_0_subtile_1__pin_outpad_0_),
.top_grid_bottom_width_0_height_0_subtile_2__pin_outpad_0_(cbx_1__1__0_top_grid_bottom_width_0_height_0_subtile_2__pin_outpad_0_),
.top_grid_bottom_width_0_height_0_subtile_3__pin_outpad_0_(cbx_1__1__0_top_grid_bottom_width_0_height_0_subtile_3__pin_outpad_0_),
.top_grid_bottom_width_0_height_0_subtile_4__pin_outpad_0_(cbx_1__1__0_top_grid_bottom_width_0_height_0_subtile_4__pin_outpad_0_),
.top_grid_bottom_width_0_height_0_subtile_5__pin_outpad_0_(cbx_1__1__0_top_grid_bottom_width_0_height_0_subtile_5__pin_outpad_0_),
.top_grid_bottom_width_0_height_0_subtile_6__pin_outpad_0_(cbx_1__1__0_top_grid_bottom_width_0_height_0_subtile_6__pin_outpad_0_),
.top_grid_bottom_width_0_height_0_subtile_7__pin_outpad_0_(cbx_1__1__0_top_grid_bottom_width_0_height_0_subtile_7__pin_outpad_0_),
.bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__1__0_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_),
.bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__1__0_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_),
.bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__1__0_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_),
.bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_(cbx_1__1__0_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_),
.bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_(cbx_1__1__0_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_),
.bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_(cbx_1__1__0_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_),
.bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_(cbx_1__1__0_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_),
.bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_(cbx_1__1__0_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_),
.bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_(cbx_1__1__0_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_),
.bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_(cbx_1__1__0_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_),
.bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_(cbx_1__1__0_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_),
.bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_(cbx_1__1__0_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_),
.bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_(cbx_1__1__0_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_),
.bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_(cbx_1__1__0_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_),
.bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_(cbx_1__1__0_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_),
.bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_(cbx_1__1__0_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_),
.ccff_tail(cbx_1__1__0_ccff_tail));
cby_0__1_ cby_0__1_ (
.pReset(pReset),
.prog_clk(prog_clk),
.chany_bottom_in(sb_0__0__0_chany_top_out[0:10]),
.chany_top_in(sb_0__1__0_chany_bottom_out[0:10]),
.ccff_head(sb_0__0__0_ccff_tail),
.chany_bottom_out(cby_0__1__0_chany_bottom_out[0:10]),
.chany_top_out(cby_0__1__0_chany_top_out[0:10]),
.left_grid_right_width_0_height_0_subtile_0__pin_outpad_0_(cby_0__1__0_left_grid_right_width_0_height_0_subtile_0__pin_outpad_0_),
.ccff_tail(cby_0__1__0_ccff_tail));
cby_1__1_ cby_1__1_ (
.pReset(pReset),
.prog_clk(prog_clk),
.chany_bottom_in(sb_1__0__0_chany_top_out[0:10]),
.chany_top_in(sb_1__1__0_chany_bottom_out[0:10]),
.ccff_head(cbx_1__0__0_ccff_tail),
.chany_bottom_out(cby_1__1__0_chany_bottom_out[0:10]),
.chany_top_out(cby_1__1__0_chany_top_out[0:10]),
.right_grid_left_width_0_height_0_subtile_0__pin_outpad_0_(cby_1__1__0_right_grid_left_width_0_height_0_subtile_0__pin_outpad_0_),
.right_grid_left_width_0_height_0_subtile_1__pin_outpad_0_(cby_1__1__0_right_grid_left_width_0_height_0_subtile_1__pin_outpad_0_),
.right_grid_left_width_0_height_0_subtile_2__pin_outpad_0_(cby_1__1__0_right_grid_left_width_0_height_0_subtile_2__pin_outpad_0_),
.right_grid_left_width_0_height_0_subtile_3__pin_outpad_0_(cby_1__1__0_right_grid_left_width_0_height_0_subtile_3__pin_outpad_0_),
.right_grid_left_width_0_height_0_subtile_4__pin_outpad_0_(cby_1__1__0_right_grid_left_width_0_height_0_subtile_4__pin_outpad_0_),
.right_grid_left_width_0_height_0_subtile_5__pin_outpad_0_(cby_1__1__0_right_grid_left_width_0_height_0_subtile_5__pin_outpad_0_),
.right_grid_left_width_0_height_0_subtile_6__pin_outpad_0_(cby_1__1__0_right_grid_left_width_0_height_0_subtile_6__pin_outpad_0_),
.right_grid_left_width_0_height_0_subtile_7__pin_outpad_0_(cby_1__1__0_right_grid_left_width_0_height_0_subtile_7__pin_outpad_0_),
.left_grid_right_width_0_height_0_subtile_0__pin_I4_0_(cby_1__1__0_left_grid_right_width_0_height_0_subtile_0__pin_I4_0_),
.left_grid_right_width_0_height_0_subtile_0__pin_I4_1_(cby_1__1__0_left_grid_right_width_0_height_0_subtile_0__pin_I4_1_),
.left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_(cby_1__1__0_left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_),
.left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_(cby_1__1__0_left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_),
.left_grid_right_width_0_height_0_subtile_0__pin_I5_0_(cby_1__1__0_left_grid_right_width_0_height_0_subtile_0__pin_I5_0_),
.left_grid_right_width_0_height_0_subtile_0__pin_I5_1_(cby_1__1__0_left_grid_right_width_0_height_0_subtile_0__pin_I5_1_),
.left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_(cby_1__1__0_left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_),
.left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_(cby_1__1__0_left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_),
.left_grid_right_width_0_height_0_subtile_0__pin_I6_0_(cby_1__1__0_left_grid_right_width_0_height_0_subtile_0__pin_I6_0_),
.left_grid_right_width_0_height_0_subtile_0__pin_I6_1_(cby_1__1__0_left_grid_right_width_0_height_0_subtile_0__pin_I6_1_),
.left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_(cby_1__1__0_left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_),
.left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_(cby_1__1__0_left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_),
.left_grid_right_width_0_height_0_subtile_0__pin_I7_0_(cby_1__1__0_left_grid_right_width_0_height_0_subtile_0__pin_I7_0_),
.left_grid_right_width_0_height_0_subtile_0__pin_I7_1_(cby_1__1__0_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_),
.left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_(cby_1__1__0_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_),
.left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_(cby_1__1__0_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_),
.ccff_tail(cby_1__1__0_ccff_tail));
endmodule
// ----- END Verilog module for fpga_top -----
//----- Default net type -----
`default_nettype none

255
SOFA_A/SOFA_A_verilog/lb/grid_clb.v Normal file
View File

@ -0,0 +1,255 @@
//-------------------------------------------
// FPGA Synthesizable Verilog Netlist
// Description: Verilog modules for physical tile: clb]
// Author: Xifan TANG
// Organization: University of Utah
// Date: Sun Feb 19 10:53:27 2023
//-------------------------------------------
//----- Time scale -----
`timescale 1ns / 1ps
// ----- BEGIN Grid Verilog module: grid_clb -----
//----- Default net type -----
`default_nettype none
// ----- Verilog module for grid_clb -----
module grid_clb(pReset,
prog_clk,
Test_en,
top_width_0_height_0_subtile_0__pin_I0_0_,
top_width_0_height_0_subtile_0__pin_I0_1_,
top_width_0_height_0_subtile_0__pin_I0i_0_,
top_width_0_height_0_subtile_0__pin_I0i_1_,
top_width_0_height_0_subtile_0__pin_I1_0_,
top_width_0_height_0_subtile_0__pin_I1_1_,
top_width_0_height_0_subtile_0__pin_I1i_0_,
top_width_0_height_0_subtile_0__pin_I1i_1_,
top_width_0_height_0_subtile_0__pin_I2_0_,
top_width_0_height_0_subtile_0__pin_I2_1_,
top_width_0_height_0_subtile_0__pin_I2i_0_,
top_width_0_height_0_subtile_0__pin_I2i_1_,
top_width_0_height_0_subtile_0__pin_I3_0_,
top_width_0_height_0_subtile_0__pin_I3_1_,
top_width_0_height_0_subtile_0__pin_I3i_0_,
top_width_0_height_0_subtile_0__pin_I3i_1_,
top_width_0_height_0_subtile_0__pin_reg_in_0_,
top_width_0_height_0_subtile_0__pin_sc_in_0_,
top_width_0_height_0_subtile_0__pin_cin_0_,
right_width_0_height_0_subtile_0__pin_I4_0_,
right_width_0_height_0_subtile_0__pin_I4_1_,
right_width_0_height_0_subtile_0__pin_I4i_0_,
right_width_0_height_0_subtile_0__pin_I4i_1_,
right_width_0_height_0_subtile_0__pin_I5_0_,
right_width_0_height_0_subtile_0__pin_I5_1_,
right_width_0_height_0_subtile_0__pin_I5i_0_,
right_width_0_height_0_subtile_0__pin_I5i_1_,
right_width_0_height_0_subtile_0__pin_I6_0_,
right_width_0_height_0_subtile_0__pin_I6_1_,
right_width_0_height_0_subtile_0__pin_I6i_0_,
right_width_0_height_0_subtile_0__pin_I6i_1_,
right_width_0_height_0_subtile_0__pin_I7_0_,
right_width_0_height_0_subtile_0__pin_I7_1_,
right_width_0_height_0_subtile_0__pin_I7i_0_,
right_width_0_height_0_subtile_0__pin_I7i_1_,
left_width_0_height_0_subtile_0__pin_reset_0_,
left_width_0_height_0_subtile_0__pin_clk_0_,
ccff_head,
top_width_0_height_0_subtile_0__pin_O_0_,
top_width_0_height_0_subtile_0__pin_O_1_,
top_width_0_height_0_subtile_0__pin_O_2_,
top_width_0_height_0_subtile_0__pin_O_3_,
top_width_0_height_0_subtile_0__pin_O_4_,
top_width_0_height_0_subtile_0__pin_O_5_,
top_width_0_height_0_subtile_0__pin_O_6_,
top_width_0_height_0_subtile_0__pin_O_7_,
right_width_0_height_0_subtile_0__pin_O_8_,
right_width_0_height_0_subtile_0__pin_O_9_,
right_width_0_height_0_subtile_0__pin_O_10_,
right_width_0_height_0_subtile_0__pin_O_11_,
right_width_0_height_0_subtile_0__pin_O_12_,
right_width_0_height_0_subtile_0__pin_O_13_,
right_width_0_height_0_subtile_0__pin_O_14_,
right_width_0_height_0_subtile_0__pin_O_15_,
bottom_width_0_height_0_subtile_0__pin_reg_out_0_,
bottom_width_0_height_0_subtile_0__pin_sc_out_0_,
bottom_width_0_height_0_subtile_0__pin_cout_0_,
ccff_tail);
//----- GLOBAL PORTS -----
input [0:0] pReset;
//----- GLOBAL PORTS -----
input [0:0] prog_clk;
//----- GLOBAL PORTS -----
input [0:0] Test_en;
//----- INPUT PORTS -----
input [0:0] top_width_0_height_0_subtile_0__pin_I0_0_;
//----- INPUT PORTS -----
input [0:0] top_width_0_height_0_subtile_0__pin_I0_1_;
//----- INPUT PORTS -----
input [0:0] top_width_0_height_0_subtile_0__pin_I0i_0_;
//----- INPUT PORTS -----
input [0:0] top_width_0_height_0_subtile_0__pin_I0i_1_;
//----- INPUT PORTS -----
input [0:0] top_width_0_height_0_subtile_0__pin_I1_0_;
//----- INPUT PORTS -----
input [0:0] top_width_0_height_0_subtile_0__pin_I1_1_;
//----- INPUT PORTS -----
input [0:0] top_width_0_height_0_subtile_0__pin_I1i_0_;
//----- INPUT PORTS -----
input [0:0] top_width_0_height_0_subtile_0__pin_I1i_1_;
//----- INPUT PORTS -----
input [0:0] top_width_0_height_0_subtile_0__pin_I2_0_;
//----- INPUT PORTS -----
input [0:0] top_width_0_height_0_subtile_0__pin_I2_1_;
//----- INPUT PORTS -----
input [0:0] top_width_0_height_0_subtile_0__pin_I2i_0_;
//----- INPUT PORTS -----
input [0:0] top_width_0_height_0_subtile_0__pin_I2i_1_;
//----- INPUT PORTS -----
input [0:0] top_width_0_height_0_subtile_0__pin_I3_0_;
//----- INPUT PORTS -----
input [0:0] top_width_0_height_0_subtile_0__pin_I3_1_;
//----- INPUT PORTS -----
input [0:0] top_width_0_height_0_subtile_0__pin_I3i_0_;
//----- INPUT PORTS -----
input [0:0] top_width_0_height_0_subtile_0__pin_I3i_1_;
//----- INPUT PORTS -----
input [0:0] top_width_0_height_0_subtile_0__pin_reg_in_0_;
//----- INPUT PORTS -----
input [0:0] top_width_0_height_0_subtile_0__pin_sc_in_0_;
//----- INPUT PORTS -----
input [0:0] top_width_0_height_0_subtile_0__pin_cin_0_;
//----- INPUT PORTS -----
input [0:0] right_width_0_height_0_subtile_0__pin_I4_0_;
//----- INPUT PORTS -----
input [0:0] right_width_0_height_0_subtile_0__pin_I4_1_;
//----- INPUT PORTS -----
input [0:0] right_width_0_height_0_subtile_0__pin_I4i_0_;
//----- INPUT PORTS -----
input [0:0] right_width_0_height_0_subtile_0__pin_I4i_1_;
//----- INPUT PORTS -----
input [0:0] right_width_0_height_0_subtile_0__pin_I5_0_;
//----- INPUT PORTS -----
input [0:0] right_width_0_height_0_subtile_0__pin_I5_1_;
//----- INPUT PORTS -----
input [0:0] right_width_0_height_0_subtile_0__pin_I5i_0_;
//----- INPUT PORTS -----
input [0:0] right_width_0_height_0_subtile_0__pin_I5i_1_;
//----- INPUT PORTS -----
input [0:0] right_width_0_height_0_subtile_0__pin_I6_0_;
//----- INPUT PORTS -----
input [0:0] right_width_0_height_0_subtile_0__pin_I6_1_;
//----- INPUT PORTS -----
input [0:0] right_width_0_height_0_subtile_0__pin_I6i_0_;
//----- INPUT PORTS -----
input [0:0] right_width_0_height_0_subtile_0__pin_I6i_1_;
//----- INPUT PORTS -----
input [0:0] right_width_0_height_0_subtile_0__pin_I7_0_;
//----- INPUT PORTS -----
input [0:0] right_width_0_height_0_subtile_0__pin_I7_1_;
//----- INPUT PORTS -----
input [0:0] right_width_0_height_0_subtile_0__pin_I7i_0_;
//----- INPUT PORTS -----
input [0:0] right_width_0_height_0_subtile_0__pin_I7i_1_;
//----- INPUT PORTS -----
input [0:0] left_width_0_height_0_subtile_0__pin_reset_0_;
//----- INPUT PORTS -----
input [0:0] left_width_0_height_0_subtile_0__pin_clk_0_;
//----- INPUT PORTS -----
input [0:0] ccff_head;
//----- OUTPUT PORTS -----
output [0:0] top_width_0_height_0_subtile_0__pin_O_0_;
//----- OUTPUT PORTS -----
output [0:0] top_width_0_height_0_subtile_0__pin_O_1_;
//----- OUTPUT PORTS -----
output [0:0] top_width_0_height_0_subtile_0__pin_O_2_;
//----- OUTPUT PORTS -----
output [0:0] top_width_0_height_0_subtile_0__pin_O_3_;
//----- OUTPUT PORTS -----
output [0:0] top_width_0_height_0_subtile_0__pin_O_4_;
//----- OUTPUT PORTS -----
output [0:0] top_width_0_height_0_subtile_0__pin_O_5_;
//----- OUTPUT PORTS -----
output [0:0] top_width_0_height_0_subtile_0__pin_O_6_;
//----- OUTPUT PORTS -----
output [0:0] top_width_0_height_0_subtile_0__pin_O_7_;
//----- OUTPUT PORTS -----
output [0:0] right_width_0_height_0_subtile_0__pin_O_8_;
//----- OUTPUT PORTS -----
output [0:0] right_width_0_height_0_subtile_0__pin_O_9_;
//----- OUTPUT PORTS -----
output [0:0] right_width_0_height_0_subtile_0__pin_O_10_;
//----- OUTPUT PORTS -----
output [0:0] right_width_0_height_0_subtile_0__pin_O_11_;
//----- OUTPUT PORTS -----
output [0:0] right_width_0_height_0_subtile_0__pin_O_12_;
//----- OUTPUT PORTS -----
output [0:0] right_width_0_height_0_subtile_0__pin_O_13_;
//----- OUTPUT PORTS -----
output [0:0] right_width_0_height_0_subtile_0__pin_O_14_;
//----- OUTPUT PORTS -----
output [0:0] right_width_0_height_0_subtile_0__pin_O_15_;
//----- OUTPUT PORTS -----
output [0:0] bottom_width_0_height_0_subtile_0__pin_reg_out_0_;
//----- OUTPUT PORTS -----
output [0:0] bottom_width_0_height_0_subtile_0__pin_sc_out_0_;
//----- OUTPUT PORTS -----
output [0:0] bottom_width_0_height_0_subtile_0__pin_cout_0_;
//----- OUTPUT PORTS -----
output [0:0] ccff_tail;
//----- BEGIN wire-connection ports -----
//----- END wire-connection ports -----
//----- BEGIN Registered ports -----
//----- END Registered ports -----
// ----- BEGIN Local short connections -----
// ----- END Local short connections -----
// ----- BEGIN Local output short connections -----
// ----- END Local output short connections -----
logical_tile_clb_mode_clb_ logical_tile_clb_mode_clb__0 (
.pReset(pReset),
.prog_clk(prog_clk),
.Test_en(Test_en),
.clb_I0({top_width_0_height_0_subtile_0__pin_I0_0_, top_width_0_height_0_subtile_0__pin_I0_1_}),
.clb_I0i({top_width_0_height_0_subtile_0__pin_I0i_0_, top_width_0_height_0_subtile_0__pin_I0i_1_}),
.clb_I1({top_width_0_height_0_subtile_0__pin_I1_0_, top_width_0_height_0_subtile_0__pin_I1_1_}),
.clb_I1i({top_width_0_height_0_subtile_0__pin_I1i_0_, top_width_0_height_0_subtile_0__pin_I1i_1_}),
.clb_I2({top_width_0_height_0_subtile_0__pin_I2_0_, top_width_0_height_0_subtile_0__pin_I2_1_}),
.clb_I2i({top_width_0_height_0_subtile_0__pin_I2i_0_, top_width_0_height_0_subtile_0__pin_I2i_1_}),
.clb_I3({top_width_0_height_0_subtile_0__pin_I3_0_, top_width_0_height_0_subtile_0__pin_I3_1_}),
.clb_I3i({top_width_0_height_0_subtile_0__pin_I3i_0_, top_width_0_height_0_subtile_0__pin_I3i_1_}),
.clb_I4({right_width_0_height_0_subtile_0__pin_I4_0_, right_width_0_height_0_subtile_0__pin_I4_1_}),
.clb_I4i({right_width_0_height_0_subtile_0__pin_I4i_0_, right_width_0_height_0_subtile_0__pin_I4i_1_}),
.clb_I5({right_width_0_height_0_subtile_0__pin_I5_0_, right_width_0_height_0_subtile_0__pin_I5_1_}),
.clb_I5i({right_width_0_height_0_subtile_0__pin_I5i_0_, right_width_0_height_0_subtile_0__pin_I5i_1_}),
.clb_I6({right_width_0_height_0_subtile_0__pin_I6_0_, right_width_0_height_0_subtile_0__pin_I6_1_}),
.clb_I6i({right_width_0_height_0_subtile_0__pin_I6i_0_, right_width_0_height_0_subtile_0__pin_I6i_1_}),
.clb_I7({right_width_0_height_0_subtile_0__pin_I7_0_, right_width_0_height_0_subtile_0__pin_I7_1_}),
.clb_I7i({right_width_0_height_0_subtile_0__pin_I7i_0_, right_width_0_height_0_subtile_0__pin_I7i_1_}),
.clb_reg_in(top_width_0_height_0_subtile_0__pin_reg_in_0_),
.clb_sc_in(top_width_0_height_0_subtile_0__pin_sc_in_0_),
.clb_cin(top_width_0_height_0_subtile_0__pin_cin_0_),
.clb_reset(left_width_0_height_0_subtile_0__pin_reset_0_),
.clb_clk(left_width_0_height_0_subtile_0__pin_clk_0_),
.ccff_head(ccff_head),
.clb_O({top_width_0_height_0_subtile_0__pin_O_0_, top_width_0_height_0_subtile_0__pin_O_1_, top_width_0_height_0_subtile_0__pin_O_2_, top_width_0_height_0_subtile_0__pin_O_3_, top_width_0_height_0_subtile_0__pin_O_4_, top_width_0_height_0_subtile_0__pin_O_5_, top_width_0_height_0_subtile_0__pin_O_6_, top_width_0_height_0_subtile_0__pin_O_7_, right_width_0_height_0_subtile_0__pin_O_8_, right_width_0_height_0_subtile_0__pin_O_9_, right_width_0_height_0_subtile_0__pin_O_10_, right_width_0_height_0_subtile_0__pin_O_11_, right_width_0_height_0_subtile_0__pin_O_12_, right_width_0_height_0_subtile_0__pin_O_13_, right_width_0_height_0_subtile_0__pin_O_14_, right_width_0_height_0_subtile_0__pin_O_15_}),
.clb_reg_out(bottom_width_0_height_0_subtile_0__pin_reg_out_0_),
.clb_sc_out(bottom_width_0_height_0_subtile_0__pin_sc_out_0_),
.clb_cout(bottom_width_0_height_0_subtile_0__pin_cout_0_),
.ccff_tail(ccff_tail));
endmodule
// ----- END Verilog module for grid_clb -----
//----- Default net type -----
`default_nettype none
// ----- END Grid Verilog module: grid_clb -----

234
SOFA_A/SOFA_A_verilog/lb/grid_io_bottom_bottom.v Normal file
View File

@ -0,0 +1,234 @@
//-------------------------------------------
// FPGA Synthesizable Verilog Netlist
// Description: Verilog modules for physical tile: io_bottom]
// Author: Xifan TANG
// Organization: University of Utah
// Date: Sun Feb 19 10:53:27 2023
//-------------------------------------------
//----- Time scale -----
`timescale 1ns / 1ps
// ----- BEGIN Grid Verilog module: grid_io_bottom_bottom -----
//----- Default net type -----
`default_nettype none
// ----- Verilog module for grid_io_bottom_bottom -----
module grid_io_bottom_bottom(IO_ISOL_N,
pReset,
prog_clk,
gfpga_pad_EMBEDDED_IO_HD_SOC_IN,
gfpga_pad_EMBEDDED_IO_HD_SOC_OUT,
gfpga_pad_EMBEDDED_IO_HD_SOC_DIR,
top_width_0_height_0_subtile_0__pin_outpad_0_,
top_width_0_height_0_subtile_1__pin_outpad_0_,
top_width_0_height_0_subtile_2__pin_outpad_0_,
top_width_0_height_0_subtile_3__pin_outpad_0_,
top_width_0_height_0_subtile_4__pin_outpad_0_,
top_width_0_height_0_subtile_5__pin_outpad_0_,
top_width_0_height_0_subtile_6__pin_outpad_0_,
top_width_0_height_0_subtile_7__pin_outpad_0_,
top_width_0_height_0_subtile_8__pin_outpad_0_,
ccff_head,
top_width_0_height_0_subtile_0__pin_inpad_0_,
top_width_0_height_0_subtile_1__pin_inpad_0_,
top_width_0_height_0_subtile_2__pin_inpad_0_,
top_width_0_height_0_subtile_3__pin_inpad_0_,
top_width_0_height_0_subtile_4__pin_inpad_0_,
top_width_0_height_0_subtile_5__pin_inpad_0_,
top_width_0_height_0_subtile_6__pin_inpad_0_,
top_width_0_height_0_subtile_7__pin_inpad_0_,
top_width_0_height_0_subtile_8__pin_inpad_0_,
ccff_tail);
//----- GLOBAL PORTS -----
input [0:0] IO_ISOL_N;
//----- GLOBAL PORTS -----
input [0:0] pReset;
//----- GLOBAL PORTS -----
input [0:0] prog_clk;
//----- GPIN PORTS -----
input [0:8] gfpga_pad_EMBEDDED_IO_HD_SOC_IN;
//----- GPOUT PORTS -----
output [0:8] gfpga_pad_EMBEDDED_IO_HD_SOC_OUT;
//----- GPOUT PORTS -----
output [0:8] gfpga_pad_EMBEDDED_IO_HD_SOC_DIR;
//----- INPUT PORTS -----
input [0:0] top_width_0_height_0_subtile_0__pin_outpad_0_;
//----- INPUT PORTS -----
input [0:0] top_width_0_height_0_subtile_1__pin_outpad_0_;
//----- INPUT PORTS -----
input [0:0] top_width_0_height_0_subtile_2__pin_outpad_0_;
//----- INPUT PORTS -----
input [0:0] top_width_0_height_0_subtile_3__pin_outpad_0_;
//----- INPUT PORTS -----
input [0:0] top_width_0_height_0_subtile_4__pin_outpad_0_;
//----- INPUT PORTS -----
input [0:0] top_width_0_height_0_subtile_5__pin_outpad_0_;
//----- INPUT PORTS -----
input [0:0] top_width_0_height_0_subtile_6__pin_outpad_0_;
//----- INPUT PORTS -----
input [0:0] top_width_0_height_0_subtile_7__pin_outpad_0_;
//----- INPUT PORTS -----
input [0:0] top_width_0_height_0_subtile_8__pin_outpad_0_;
//----- INPUT PORTS -----
input [0:0] ccff_head;
//----- OUTPUT PORTS -----
output [0:0] top_width_0_height_0_subtile_0__pin_inpad_0_;
//----- OUTPUT PORTS -----
output [0:0] top_width_0_height_0_subtile_1__pin_inpad_0_;
//----- OUTPUT PORTS -----
output [0:0] top_width_0_height_0_subtile_2__pin_inpad_0_;
//----- OUTPUT PORTS -----
output [0:0] top_width_0_height_0_subtile_3__pin_inpad_0_;
//----- OUTPUT PORTS -----
output [0:0] top_width_0_height_0_subtile_4__pin_inpad_0_;
//----- OUTPUT PORTS -----
output [0:0] top_width_0_height_0_subtile_5__pin_inpad_0_;
//----- OUTPUT PORTS -----
output [0:0] top_width_0_height_0_subtile_6__pin_inpad_0_;
//----- OUTPUT PORTS -----
output [0:0] top_width_0_height_0_subtile_7__pin_inpad_0_;
//----- OUTPUT PORTS -----
output [0:0] top_width_0_height_0_subtile_8__pin_inpad_0_;
//----- OUTPUT PORTS -----
output [0:0] ccff_tail;
//----- BEGIN wire-connection ports -----
//----- END wire-connection ports -----
//----- BEGIN Registered ports -----
//----- END Registered ports -----
wire [0:0] logical_tile_io_mode_io__0_ccff_tail;
wire [0:0] logical_tile_io_mode_io__1_ccff_tail;
wire [0:0] logical_tile_io_mode_io__2_ccff_tail;
wire [0:0] logical_tile_io_mode_io__3_ccff_tail;
wire [0:0] logical_tile_io_mode_io__4_ccff_tail;
wire [0:0] logical_tile_io_mode_io__5_ccff_tail;
wire [0:0] logical_tile_io_mode_io__6_ccff_tail;
wire [0:0] logical_tile_io_mode_io__7_ccff_tail;
// ----- BEGIN Local short connections -----
// ----- END Local short connections -----
// ----- BEGIN Local output short connections -----
// ----- END Local output short connections -----
logical_tile_io_mode_io_ logical_tile_io_mode_io__0 (
.IO_ISOL_N(IO_ISOL_N),
.pReset(pReset),
.prog_clk(prog_clk),
.gfpga_pad_EMBEDDED_IO_HD_SOC_IN(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[0]),
.gfpga_pad_EMBEDDED_IO_HD_SOC_OUT(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[0]),
.gfpga_pad_EMBEDDED_IO_HD_SOC_DIR(gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[0]),
.io_outpad(top_width_0_height_0_subtile_0__pin_outpad_0_),
.ccff_head(ccff_head),
.io_inpad(top_width_0_height_0_subtile_0__pin_inpad_0_),
.ccff_tail(logical_tile_io_mode_io__0_ccff_tail));
logical_tile_io_mode_io_ logical_tile_io_mode_io__1 (
.IO_ISOL_N(IO_ISOL_N),
.pReset(pReset),
.prog_clk(prog_clk),
.gfpga_pad_EMBEDDED_IO_HD_SOC_IN(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[1]),
.gfpga_pad_EMBEDDED_IO_HD_SOC_OUT(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[1]),
.gfpga_pad_EMBEDDED_IO_HD_SOC_DIR(gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[1]),
.io_outpad(top_width_0_height_0_subtile_1__pin_outpad_0_),
.ccff_head(logical_tile_io_mode_io__0_ccff_tail),
.io_inpad(top_width_0_height_0_subtile_1__pin_inpad_0_),
.ccff_tail(logical_tile_io_mode_io__1_ccff_tail));
logical_tile_io_mode_io_ logical_tile_io_mode_io__2 (
.IO_ISOL_N(IO_ISOL_N),
.pReset(pReset),
.prog_clk(prog_clk),
.gfpga_pad_EMBEDDED_IO_HD_SOC_IN(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[2]),
.gfpga_pad_EMBEDDED_IO_HD_SOC_OUT(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[2]),
.gfpga_pad_EMBEDDED_IO_HD_SOC_DIR(gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[2]),
.io_outpad(top_width_0_height_0_subtile_2__pin_outpad_0_),
.ccff_head(logical_tile_io_mode_io__1_ccff_tail),
.io_inpad(top_width_0_height_0_subtile_2__pin_inpad_0_),
.ccff_tail(logical_tile_io_mode_io__2_ccff_tail));
logical_tile_io_mode_io_ logical_tile_io_mode_io__3 (
.IO_ISOL_N(IO_ISOL_N),
.pReset(pReset),
.prog_clk(prog_clk),
.gfpga_pad_EMBEDDED_IO_HD_SOC_IN(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[3]),
.gfpga_pad_EMBEDDED_IO_HD_SOC_OUT(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[3]),
.gfpga_pad_EMBEDDED_IO_HD_SOC_DIR(gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[3]),
.io_outpad(top_width_0_height_0_subtile_3__pin_outpad_0_),
.ccff_head(logical_tile_io_mode_io__2_ccff_tail),
.io_inpad(top_width_0_height_0_subtile_3__pin_inpad_0_),
.ccff_tail(logical_tile_io_mode_io__3_ccff_tail));
logical_tile_io_mode_io_ logical_tile_io_mode_io__4 (
.IO_ISOL_N(IO_ISOL_N),
.pReset(pReset),
.prog_clk(prog_clk),
.gfpga_pad_EMBEDDED_IO_HD_SOC_IN(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[4]),
.gfpga_pad_EMBEDDED_IO_HD_SOC_OUT(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[4]),
.gfpga_pad_EMBEDDED_IO_HD_SOC_DIR(gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[4]),
.io_outpad(top_width_0_height_0_subtile_4__pin_outpad_0_),
.ccff_head(logical_tile_io_mode_io__3_ccff_tail),
.io_inpad(top_width_0_height_0_subtile_4__pin_inpad_0_),
.ccff_tail(logical_tile_io_mode_io__4_ccff_tail));
logical_tile_io_mode_io_ logical_tile_io_mode_io__5 (
.IO_ISOL_N(IO_ISOL_N),
.pReset(pReset),
.prog_clk(prog_clk),
.gfpga_pad_EMBEDDED_IO_HD_SOC_IN(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[5]),
.gfpga_pad_EMBEDDED_IO_HD_SOC_OUT(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[5]),
.gfpga_pad_EMBEDDED_IO_HD_SOC_DIR(gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[5]),
.io_outpad(top_width_0_height_0_subtile_5__pin_outpad_0_),
.ccff_head(logical_tile_io_mode_io__4_ccff_tail),
.io_inpad(top_width_0_height_0_subtile_5__pin_inpad_0_),
.ccff_tail(logical_tile_io_mode_io__5_ccff_tail));
logical_tile_io_mode_io_ logical_tile_io_mode_io__6 (
.IO_ISOL_N(IO_ISOL_N),
.pReset(pReset),
.prog_clk(prog_clk),
.gfpga_pad_EMBEDDED_IO_HD_SOC_IN(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[6]),
.gfpga_pad_EMBEDDED_IO_HD_SOC_OUT(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[6]),
.gfpga_pad_EMBEDDED_IO_HD_SOC_DIR(gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[6]),
.io_outpad(top_width_0_height_0_subtile_6__pin_outpad_0_),
.ccff_head(logical_tile_io_mode_io__5_ccff_tail),
.io_inpad(top_width_0_height_0_subtile_6__pin_inpad_0_),
.ccff_tail(logical_tile_io_mode_io__6_ccff_tail));
logical_tile_io_mode_io_ logical_tile_io_mode_io__7 (
.IO_ISOL_N(IO_ISOL_N),
.pReset(pReset),
.prog_clk(prog_clk),
.gfpga_pad_EMBEDDED_IO_HD_SOC_IN(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[7]),
.gfpga_pad_EMBEDDED_IO_HD_SOC_OUT(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[7]),
.gfpga_pad_EMBEDDED_IO_HD_SOC_DIR(gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[7]),
.io_outpad(top_width_0_height_0_subtile_7__pin_outpad_0_),
.ccff_head(logical_tile_io_mode_io__6_ccff_tail),
.io_inpad(top_width_0_height_0_subtile_7__pin_inpad_0_),
.ccff_tail(logical_tile_io_mode_io__7_ccff_tail));
logical_tile_io_mode_io_ logical_tile_io_mode_io__8 (
.IO_ISOL_N(IO_ISOL_N),
.pReset(pReset),
.prog_clk(prog_clk),
.gfpga_pad_EMBEDDED_IO_HD_SOC_IN(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[8]),
.gfpga_pad_EMBEDDED_IO_HD_SOC_OUT(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[8]),
.gfpga_pad_EMBEDDED_IO_HD_SOC_DIR(gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[8]),
.io_outpad(top_width_0_height_0_subtile_8__pin_outpad_0_),
.ccff_head(logical_tile_io_mode_io__7_ccff_tail),
.io_inpad(top_width_0_height_0_subtile_8__pin_inpad_0_),
.ccff_tail(ccff_tail));
endmodule
// ----- END Verilog module for grid_io_bottom_bottom -----
//----- Default net type -----
`default_nettype none
// ----- END Grid Verilog module: grid_io_bottom_bottom -----

82
SOFA_A/SOFA_A_verilog/lb/grid_io_left_left.v Normal file
View File

@ -0,0 +1,82 @@
//-------------------------------------------
// FPGA Synthesizable Verilog Netlist
// Description: Verilog modules for physical tile: io_left]
// Author: Xifan TANG
// Organization: University of Utah
// Date: Sun Feb 19 10:53:27 2023
//-------------------------------------------
//----- Time scale -----
`timescale 1ns / 1ps
// ----- BEGIN Grid Verilog module: grid_io_left_left -----
//----- Default net type -----
`default_nettype none
// ----- Verilog module for grid_io_left_left -----
module grid_io_left_left(IO_ISOL_N,
pReset,
prog_clk,
gfpga_pad_EMBEDDED_IO_HD_SOC_IN,
gfpga_pad_EMBEDDED_IO_HD_SOC_OUT,
gfpga_pad_EMBEDDED_IO_HD_SOC_DIR,
right_width_0_height_0_subtile_0__pin_outpad_0_,
ccff_head,
right_width_0_height_0_subtile_0__pin_inpad_0_,
ccff_tail);
//----- GLOBAL PORTS -----
input [0:0] IO_ISOL_N;
//----- GLOBAL PORTS -----
input [0:0] pReset;
//----- GLOBAL PORTS -----
input [0:0] prog_clk;
//----- GPIN PORTS -----
input [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_IN;
//----- GPOUT PORTS -----
output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_OUT;
//----- GPOUT PORTS -----
output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_DIR;
//----- INPUT PORTS -----
input [0:0] right_width_0_height_0_subtile_0__pin_outpad_0_;
//----- INPUT PORTS -----
input [0:0] ccff_head;
//----- OUTPUT PORTS -----
output [0:0] right_width_0_height_0_subtile_0__pin_inpad_0_;
//----- OUTPUT PORTS -----
output [0:0] ccff_tail;
//----- BEGIN wire-connection ports -----
//----- END wire-connection ports -----
//----- BEGIN Registered ports -----
//----- END Registered ports -----
// ----- BEGIN Local short connections -----
// ----- END Local short connections -----
// ----- BEGIN Local output short connections -----
// ----- END Local output short connections -----
logical_tile_io_mode_io_ logical_tile_io_mode_io__0 (
.IO_ISOL_N(IO_ISOL_N),
.pReset(pReset),
.prog_clk(prog_clk),
.gfpga_pad_EMBEDDED_IO_HD_SOC_IN(gfpga_pad_EMBEDDED_IO_HD_SOC_IN),
.gfpga_pad_EMBEDDED_IO_HD_SOC_OUT(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT),
.gfpga_pad_EMBEDDED_IO_HD_SOC_DIR(gfpga_pad_EMBEDDED_IO_HD_SOC_DIR),
.io_outpad(right_width_0_height_0_subtile_0__pin_outpad_0_),
.ccff_head(ccff_head),
.io_inpad(right_width_0_height_0_subtile_0__pin_inpad_0_),
.ccff_tail(ccff_tail));
endmodule
// ----- END Verilog module for grid_io_left_left -----
//----- Default net type -----
`default_nettype none
// ----- END Grid Verilog module: grid_io_left_left -----

215
SOFA_A/SOFA_A_verilog/lb/grid_io_right_right.v Normal file
View File

@ -0,0 +1,215 @@
//-------------------------------------------
// FPGA Synthesizable Verilog Netlist
// Description: Verilog modules for physical tile: io_right]
// Author: Xifan TANG
// Organization: University of Utah
// Date: Sun Feb 19 10:53:27 2023
//-------------------------------------------
//----- Time scale -----
`timescale 1ns / 1ps
// ----- BEGIN Grid Verilog module: grid_io_right_right -----
//----- Default net type -----
`default_nettype none
// ----- Verilog module for grid_io_right_right -----
module grid_io_right_right(IO_ISOL_N,
pReset,
prog_clk,
gfpga_pad_EMBEDDED_IO_HD_SOC_IN,
gfpga_pad_EMBEDDED_IO_HD_SOC_OUT,
gfpga_pad_EMBEDDED_IO_HD_SOC_DIR,
left_width_0_height_0_subtile_0__pin_outpad_0_,
left_width_0_height_0_subtile_1__pin_outpad_0_,
left_width_0_height_0_subtile_2__pin_outpad_0_,
left_width_0_height_0_subtile_3__pin_outpad_0_,
left_width_0_height_0_subtile_4__pin_outpad_0_,
left_width_0_height_0_subtile_5__pin_outpad_0_,
left_width_0_height_0_subtile_6__pin_outpad_0_,
left_width_0_height_0_subtile_7__pin_outpad_0_,
ccff_head,
left_width_0_height_0_subtile_0__pin_inpad_0_,
left_width_0_height_0_subtile_1__pin_inpad_0_,
left_width_0_height_0_subtile_2__pin_inpad_0_,
left_width_0_height_0_subtile_3__pin_inpad_0_,
left_width_0_height_0_subtile_4__pin_inpad_0_,
left_width_0_height_0_subtile_5__pin_inpad_0_,
left_width_0_height_0_subtile_6__pin_inpad_0_,
left_width_0_height_0_subtile_7__pin_inpad_0_,
ccff_tail);
//----- GLOBAL PORTS -----
input [0:0] IO_ISOL_N;
//----- GLOBAL PORTS -----
input [0:0] pReset;
//----- GLOBAL PORTS -----
input [0:0] prog_clk;
//----- GPIN PORTS -----
input [0:7] gfpga_pad_EMBEDDED_IO_HD_SOC_IN;
//----- GPOUT PORTS -----
output [0:7] gfpga_pad_EMBEDDED_IO_HD_SOC_OUT;
//----- GPOUT PORTS -----
output [0:7] gfpga_pad_EMBEDDED_IO_HD_SOC_DIR;
//----- INPUT PORTS -----
input [0:0] left_width_0_height_0_subtile_0__pin_outpad_0_;
//----- INPUT PORTS -----
input [0:0] left_width_0_height_0_subtile_1__pin_outpad_0_;
//----- INPUT PORTS -----
input [0:0] left_width_0_height_0_subtile_2__pin_outpad_0_;
//----- INPUT PORTS -----
input [0:0] left_width_0_height_0_subtile_3__pin_outpad_0_;
//----- INPUT PORTS -----
input [0:0] left_width_0_height_0_subtile_4__pin_outpad_0_;
//----- INPUT PORTS -----
input [0:0] left_width_0_height_0_subtile_5__pin_outpad_0_;
//----- INPUT PORTS -----
input [0:0] left_width_0_height_0_subtile_6__pin_outpad_0_;
//----- INPUT PORTS -----
input [0:0] left_width_0_height_0_subtile_7__pin_outpad_0_;
//----- INPUT PORTS -----
input [0:0] ccff_head;
//----- OUTPUT PORTS -----
output [0:0] left_width_0_height_0_subtile_0__pin_inpad_0_;
//----- OUTPUT PORTS -----
output [0:0] left_width_0_height_0_subtile_1__pin_inpad_0_;
//----- OUTPUT PORTS -----
output [0:0] left_width_0_height_0_subtile_2__pin_inpad_0_;
//----- OUTPUT PORTS -----
output [0:0] left_width_0_height_0_subtile_3__pin_inpad_0_;
//----- OUTPUT PORTS -----
output [0:0] left_width_0_height_0_subtile_4__pin_inpad_0_;
//----- OUTPUT PORTS -----
output [0:0] left_width_0_height_0_subtile_5__pin_inpad_0_;
//----- OUTPUT PORTS -----
output [0:0] left_width_0_height_0_subtile_6__pin_inpad_0_;
//----- OUTPUT PORTS -----
output [0:0] left_width_0_height_0_subtile_7__pin_inpad_0_;
//----- OUTPUT PORTS -----
output [0:0] ccff_tail;
//----- BEGIN wire-connection ports -----
//----- END wire-connection ports -----
//----- BEGIN Registered ports -----
//----- END Registered ports -----
wire [0:0] logical_tile_io_mode_io__0_ccff_tail;
wire [0:0] logical_tile_io_mode_io__1_ccff_tail;
wire [0:0] logical_tile_io_mode_io__2_ccff_tail;
wire [0:0] logical_tile_io_mode_io__3_ccff_tail;
wire [0:0] logical_tile_io_mode_io__4_ccff_tail;
wire [0:0] logical_tile_io_mode_io__5_ccff_tail;
wire [0:0] logical_tile_io_mode_io__6_ccff_tail;
// ----- BEGIN Local short connections -----
// ----- END Local short connections -----
// ----- BEGIN Local output short connections -----
// ----- END Local output short connections -----
logical_tile_io_mode_io_ logical_tile_io_mode_io__0 (
.IO_ISOL_N(IO_ISOL_N),
.pReset(pReset),
.prog_clk(prog_clk),
.gfpga_pad_EMBEDDED_IO_HD_SOC_IN(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[0]),
.gfpga_pad_EMBEDDED_IO_HD_SOC_OUT(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[0]),
.gfpga_pad_EMBEDDED_IO_HD_SOC_DIR(gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[0]),
.io_outpad(left_width_0_height_0_subtile_0__pin_outpad_0_),
.ccff_head(ccff_head),
.io_inpad(left_width_0_height_0_subtile_0__pin_inpad_0_),
.ccff_tail(logical_tile_io_mode_io__0_ccff_tail));
logical_tile_io_mode_io_ logical_tile_io_mode_io__1 (
.IO_ISOL_N(IO_ISOL_N),
.pReset(pReset),
.prog_clk(prog_clk),
.gfpga_pad_EMBEDDED_IO_HD_SOC_IN(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[1]),
.gfpga_pad_EMBEDDED_IO_HD_SOC_OUT(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[1]),
.gfpga_pad_EMBEDDED_IO_HD_SOC_DIR(gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[1]),
.io_outpad(left_width_0_height_0_subtile_1__pin_outpad_0_),
.ccff_head(logical_tile_io_mode_io__0_ccff_tail),
.io_inpad(left_width_0_height_0_subtile_1__pin_inpad_0_),
.ccff_tail(logical_tile_io_mode_io__1_ccff_tail));
logical_tile_io_mode_io_ logical_tile_io_mode_io__2 (
.IO_ISOL_N(IO_ISOL_N),
.pReset(pReset),
.prog_clk(prog_clk),
.gfpga_pad_EMBEDDED_IO_HD_SOC_IN(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[2]),
.gfpga_pad_EMBEDDED_IO_HD_SOC_OUT(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[2]),
.gfpga_pad_EMBEDDED_IO_HD_SOC_DIR(gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[2]),
.io_outpad(left_width_0_height_0_subtile_2__pin_outpad_0_),
.ccff_head(logical_tile_io_mode_io__1_ccff_tail),
.io_inpad(left_width_0_height_0_subtile_2__pin_inpad_0_),
.ccff_tail(logical_tile_io_mode_io__2_ccff_tail));
logical_tile_io_mode_io_ logical_tile_io_mode_io__3 (
.IO_ISOL_N(IO_ISOL_N),
.pReset(pReset),
.prog_clk(prog_clk),
.gfpga_pad_EMBEDDED_IO_HD_SOC_IN(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[3]),
.gfpga_pad_EMBEDDED_IO_HD_SOC_OUT(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[3]),
.gfpga_pad_EMBEDDED_IO_HD_SOC_DIR(gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[3]),
.io_outpad(left_width_0_height_0_subtile_3__pin_outpad_0_),
.ccff_head(logical_tile_io_mode_io__2_ccff_tail),
.io_inpad(left_width_0_height_0_subtile_3__pin_inpad_0_),
.ccff_tail(logical_tile_io_mode_io__3_ccff_tail));
logical_tile_io_mode_io_ logical_tile_io_mode_io__4 (
.IO_ISOL_N(IO_ISOL_N),
.pReset(pReset),
.prog_clk(prog_clk),
.gfpga_pad_EMBEDDED_IO_HD_SOC_IN(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[4]),
.gfpga_pad_EMBEDDED_IO_HD_SOC_OUT(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[4]),
.gfpga_pad_EMBEDDED_IO_HD_SOC_DIR(gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[4]),
.io_outpad(left_width_0_height_0_subtile_4__pin_outpad_0_),
.ccff_head(logical_tile_io_mode_io__3_ccff_tail),
.io_inpad(left_width_0_height_0_subtile_4__pin_inpad_0_),
.ccff_tail(logical_tile_io_mode_io__4_ccff_tail));
logical_tile_io_mode_io_ logical_tile_io_mode_io__5 (
.IO_ISOL_N(IO_ISOL_N),
.pReset(pReset),
.prog_clk(prog_clk),
.gfpga_pad_EMBEDDED_IO_HD_SOC_IN(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[5]),
.gfpga_pad_EMBEDDED_IO_HD_SOC_OUT(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[5]),
.gfpga_pad_EMBEDDED_IO_HD_SOC_DIR(gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[5]),
.io_outpad(left_width_0_height_0_subtile_5__pin_outpad_0_),
.ccff_head(logical_tile_io_mode_io__4_ccff_tail),
.io_inpad(left_width_0_height_0_subtile_5__pin_inpad_0_),
.ccff_tail(logical_tile_io_mode_io__5_ccff_tail));
logical_tile_io_mode_io_ logical_tile_io_mode_io__6 (
.IO_ISOL_N(IO_ISOL_N),
.pReset(pReset),
.prog_clk(prog_clk),
.gfpga_pad_EMBEDDED_IO_HD_SOC_IN(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[6]),
.gfpga_pad_EMBEDDED_IO_HD_SOC_OUT(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[6]),
.gfpga_pad_EMBEDDED_IO_HD_SOC_DIR(gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[6]),
.io_outpad(left_width_0_height_0_subtile_6__pin_outpad_0_),
.ccff_head(logical_tile_io_mode_io__5_ccff_tail),
.io_inpad(left_width_0_height_0_subtile_6__pin_inpad_0_),
.ccff_tail(logical_tile_io_mode_io__6_ccff_tail));
logical_tile_io_mode_io_ logical_tile_io_mode_io__7 (
.IO_ISOL_N(IO_ISOL_N),
.pReset(pReset),
.prog_clk(prog_clk),
.gfpga_pad_EMBEDDED_IO_HD_SOC_IN(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[7]),
.gfpga_pad_EMBEDDED_IO_HD_SOC_OUT(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[7]),
.gfpga_pad_EMBEDDED_IO_HD_SOC_DIR(gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[7]),
.io_outpad(left_width_0_height_0_subtile_7__pin_outpad_0_),
.ccff_head(logical_tile_io_mode_io__6_ccff_tail),
.io_inpad(left_width_0_height_0_subtile_7__pin_inpad_0_),
.ccff_tail(ccff_tail));
endmodule
// ----- END Verilog module for grid_io_right_right -----
//----- Default net type -----
`default_nettype none
// ----- END Grid Verilog module: grid_io_right_right -----

215
SOFA_A/SOFA_A_verilog/lb/grid_io_top_top.v Normal file
View File

@ -0,0 +1,215 @@
//-------------------------------------------
// FPGA Synthesizable Verilog Netlist
// Description: Verilog modules for physical tile: io_top]
// Author: Xifan TANG
// Organization: University of Utah
// Date: Sun Feb 19 10:53:27 2023
//-------------------------------------------
//----- Time scale -----
`timescale 1ns / 1ps
// ----- BEGIN Grid Verilog module: grid_io_top_top -----
//----- Default net type -----
`default_nettype none
// ----- Verilog module for grid_io_top_top -----
module grid_io_top_top(IO_ISOL_N,
pReset,
prog_clk,
gfpga_pad_EMBEDDED_IO_HD_SOC_IN,
gfpga_pad_EMBEDDED_IO_HD_SOC_OUT,
gfpga_pad_EMBEDDED_IO_HD_SOC_DIR,
bottom_width_0_height_0_subtile_0__pin_outpad_0_,
bottom_width_0_height_0_subtile_1__pin_outpad_0_,
bottom_width_0_height_0_subtile_2__pin_outpad_0_,
bottom_width_0_height_0_subtile_3__pin_outpad_0_,
bottom_width_0_height_0_subtile_4__pin_outpad_0_,
bottom_width_0_height_0_subtile_5__pin_outpad_0_,
bottom_width_0_height_0_subtile_6__pin_outpad_0_,
bottom_width_0_height_0_subtile_7__pin_outpad_0_,
ccff_head,
bottom_width_0_height_0_subtile_0__pin_inpad_0_,
bottom_width_0_height_0_subtile_1__pin_inpad_0_,
bottom_width_0_height_0_subtile_2__pin_inpad_0_,
bottom_width_0_height_0_subtile_3__pin_inpad_0_,
bottom_width_0_height_0_subtile_4__pin_inpad_0_,
bottom_width_0_height_0_subtile_5__pin_inpad_0_,
bottom_width_0_height_0_subtile_6__pin_inpad_0_,
bottom_width_0_height_0_subtile_7__pin_inpad_0_,
ccff_tail);
//----- GLOBAL PORTS -----
input [0:0] IO_ISOL_N;
//----- GLOBAL PORTS -----
input [0:0] pReset;
//----- GLOBAL PORTS -----
input [0:0] prog_clk;
//----- GPIN PORTS -----
input [0:7] gfpga_pad_EMBEDDED_IO_HD_SOC_IN;
//----- GPOUT PORTS -----
output [0:7] gfpga_pad_EMBEDDED_IO_HD_SOC_OUT;
//----- GPOUT PORTS -----
output [0:7] gfpga_pad_EMBEDDED_IO_HD_SOC_DIR;
//----- INPUT PORTS -----
input [0:0] bottom_width_0_height_0_subtile_0__pin_outpad_0_;
//----- INPUT PORTS -----
input [0:0] bottom_width_0_height_0_subtile_1__pin_outpad_0_;
//----- INPUT PORTS -----
input [0:0] bottom_width_0_height_0_subtile_2__pin_outpad_0_;
//----- INPUT PORTS -----
input [0:0] bottom_width_0_height_0_subtile_3__pin_outpad_0_;
//----- INPUT PORTS -----
input [0:0] bottom_width_0_height_0_subtile_4__pin_outpad_0_;
//----- INPUT PORTS -----
input [0:0] bottom_width_0_height_0_subtile_5__pin_outpad_0_;
//----- INPUT PORTS -----
input [0:0] bottom_width_0_height_0_subtile_6__pin_outpad_0_;
//----- INPUT PORTS -----
input [0:0] bottom_width_0_height_0_subtile_7__pin_outpad_0_;
//----- INPUT PORTS -----
input [0:0] ccff_head;
//----- OUTPUT PORTS -----
output [0:0] bottom_width_0_height_0_subtile_0__pin_inpad_0_;
//----- OUTPUT PORTS -----
output [0:0] bottom_width_0_height_0_subtile_1__pin_inpad_0_;
//----- OUTPUT PORTS -----
output [0:0] bottom_width_0_height_0_subtile_2__pin_inpad_0_;
//----- OUTPUT PORTS -----
output [0:0] bottom_width_0_height_0_subtile_3__pin_inpad_0_;
//----- OUTPUT PORTS -----
output [0:0] bottom_width_0_height_0_subtile_4__pin_inpad_0_;
//----- OUTPUT PORTS -----
output [0:0] bottom_width_0_height_0_subtile_5__pin_inpad_0_;
//----- OUTPUT PORTS -----
output [0:0] bottom_width_0_height_0_subtile_6__pin_inpad_0_;
//----- OUTPUT PORTS -----
output [0:0] bottom_width_0_height_0_subtile_7__pin_inpad_0_;
//----- OUTPUT PORTS -----
output [0:0] ccff_tail;
//----- BEGIN wire-connection ports -----
//----- END wire-connection ports -----
//----- BEGIN Registered ports -----
//----- END Registered ports -----
wire [0:0] logical_tile_io_mode_io__0_ccff_tail;
wire [0:0] logical_tile_io_mode_io__1_ccff_tail;
wire [0:0] logical_tile_io_mode_io__2_ccff_tail;
wire [0:0] logical_tile_io_mode_io__3_ccff_tail;
wire [0:0] logical_tile_io_mode_io__4_ccff_tail;
wire [0:0] logical_tile_io_mode_io__5_ccff_tail;
wire [0:0] logical_tile_io_mode_io__6_ccff_tail;
// ----- BEGIN Local short connections -----
// ----- END Local short connections -----
// ----- BEGIN Local output short connections -----
// ----- END Local output short connections -----
logical_tile_io_mode_io_ logical_tile_io_mode_io__0 (
.IO_ISOL_N(IO_ISOL_N),
.pReset(pReset),
.prog_clk(prog_clk),
.gfpga_pad_EMBEDDED_IO_HD_SOC_IN(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[0]),
.gfpga_pad_EMBEDDED_IO_HD_SOC_OUT(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[0]),
.gfpga_pad_EMBEDDED_IO_HD_SOC_DIR(gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[0]),
.io_outpad(bottom_width_0_height_0_subtile_0__pin_outpad_0_),
.ccff_head(ccff_head),
.io_inpad(bottom_width_0_height_0_subtile_0__pin_inpad_0_),
.ccff_tail(logical_tile_io_mode_io__0_ccff_tail));
logical_tile_io_mode_io_ logical_tile_io_mode_io__1 (
.IO_ISOL_N(IO_ISOL_N),
.pReset(pReset),
.prog_clk(prog_clk),
.gfpga_pad_EMBEDDED_IO_HD_SOC_IN(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[1]),
.gfpga_pad_EMBEDDED_IO_HD_SOC_OUT(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[1]),
.gfpga_pad_EMBEDDED_IO_HD_SOC_DIR(gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[1]),
.io_outpad(bottom_width_0_height_0_subtile_1__pin_outpad_0_),
.ccff_head(logical_tile_io_mode_io__0_ccff_tail),
.io_inpad(bottom_width_0_height_0_subtile_1__pin_inpad_0_),
.ccff_tail(logical_tile_io_mode_io__1_ccff_tail));
logical_tile_io_mode_io_ logical_tile_io_mode_io__2 (
.IO_ISOL_N(IO_ISOL_N),
.pReset(pReset),
.prog_clk(prog_clk),
.gfpga_pad_EMBEDDED_IO_HD_SOC_IN(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[2]),
.gfpga_pad_EMBEDDED_IO_HD_SOC_OUT(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[2]),
.gfpga_pad_EMBEDDED_IO_HD_SOC_DIR(gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[2]),
.io_outpad(bottom_width_0_height_0_subtile_2__pin_outpad_0_),
.ccff_head(logical_tile_io_mode_io__1_ccff_tail),
.io_inpad(bottom_width_0_height_0_subtile_2__pin_inpad_0_),
.ccff_tail(logical_tile_io_mode_io__2_ccff_tail));
logical_tile_io_mode_io_ logical_tile_io_mode_io__3 (
.IO_ISOL_N(IO_ISOL_N),
.pReset(pReset),
.prog_clk(prog_clk),
.gfpga_pad_EMBEDDED_IO_HD_SOC_IN(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[3]),
.gfpga_pad_EMBEDDED_IO_HD_SOC_OUT(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[3]),
.gfpga_pad_EMBEDDED_IO_HD_SOC_DIR(gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[3]),
.io_outpad(bottom_width_0_height_0_subtile_3__pin_outpad_0_),
.ccff_head(logical_tile_io_mode_io__2_ccff_tail),
.io_inpad(bottom_width_0_height_0_subtile_3__pin_inpad_0_),
.ccff_tail(logical_tile_io_mode_io__3_ccff_tail));
logical_tile_io_mode_io_ logical_tile_io_mode_io__4 (
.IO_ISOL_N(IO_ISOL_N),
.pReset(pReset),
.prog_clk(prog_clk),
.gfpga_pad_EMBEDDED_IO_HD_SOC_IN(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[4]),
.gfpga_pad_EMBEDDED_IO_HD_SOC_OUT(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[4]),
.gfpga_pad_EMBEDDED_IO_HD_SOC_DIR(gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[4]),
.io_outpad(bottom_width_0_height_0_subtile_4__pin_outpad_0_),
.ccff_head(logical_tile_io_mode_io__3_ccff_tail),
.io_inpad(bottom_width_0_height_0_subtile_4__pin_inpad_0_),
.ccff_tail(logical_tile_io_mode_io__4_ccff_tail));
logical_tile_io_mode_io_ logical_tile_io_mode_io__5 (
.IO_ISOL_N(IO_ISOL_N),
.pReset(pReset),
.prog_clk(prog_clk),
.gfpga_pad_EMBEDDED_IO_HD_SOC_IN(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[5]),
.gfpga_pad_EMBEDDED_IO_HD_SOC_OUT(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[5]),
.gfpga_pad_EMBEDDED_IO_HD_SOC_DIR(gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[5]),
.io_outpad(bottom_width_0_height_0_subtile_5__pin_outpad_0_),
.ccff_head(logical_tile_io_mode_io__4_ccff_tail),
.io_inpad(bottom_width_0_height_0_subtile_5__pin_inpad_0_),
.ccff_tail(logical_tile_io_mode_io__5_ccff_tail));
logical_tile_io_mode_io_ logical_tile_io_mode_io__6 (
.IO_ISOL_N(IO_ISOL_N),
.pReset(pReset),
.prog_clk(prog_clk),
.gfpga_pad_EMBEDDED_IO_HD_SOC_IN(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[6]),
.gfpga_pad_EMBEDDED_IO_HD_SOC_OUT(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[6]),
.gfpga_pad_EMBEDDED_IO_HD_SOC_DIR(gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[6]),
.io_outpad(bottom_width_0_height_0_subtile_6__pin_outpad_0_),
.ccff_head(logical_tile_io_mode_io__5_ccff_tail),
.io_inpad(bottom_width_0_height_0_subtile_6__pin_inpad_0_),
.ccff_tail(logical_tile_io_mode_io__6_ccff_tail));
logical_tile_io_mode_io_ logical_tile_io_mode_io__7 (
.IO_ISOL_N(IO_ISOL_N),
.pReset(pReset),
.prog_clk(prog_clk),
.gfpga_pad_EMBEDDED_IO_HD_SOC_IN(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[7]),
.gfpga_pad_EMBEDDED_IO_HD_SOC_OUT(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[7]),
.gfpga_pad_EMBEDDED_IO_HD_SOC_DIR(gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[7]),
.io_outpad(bottom_width_0_height_0_subtile_7__pin_outpad_0_),
.ccff_head(logical_tile_io_mode_io__6_ccff_tail),
.io_inpad(bottom_width_0_height_0_subtile_7__pin_inpad_0_),
.ccff_tail(ccff_tail));
endmodule
// ----- END Verilog module for grid_io_top_top -----
//----- Default net type -----
`default_nettype none
// ----- END Grid Verilog module: grid_io_top_top -----

765
SOFA_A/SOFA_A_verilog/lb/logical_tile_clb_mode_clb_.v Normal file
View File

@ -0,0 +1,765 @@
//-------------------------------------------
// FPGA Synthesizable Verilog Netlist
// Description: Verilog modules for pb_type: clb
// Author: Xifan TANG
// Organization: University of Utah
// Date: Sun Feb 19 10:53:27 2023
//-------------------------------------------
//----- Time scale -----
`timescale 1ns / 1ps
// ----- BEGIN Physical programmable logic block Verilog module: clb -----
//----- Default net type -----
`default_nettype none
// ----- Verilog module for logical_tile_clb_mode_clb_ -----
module logical_tile_clb_mode_clb_(pReset,
prog_clk,
Test_en,
clb_I0,
clb_I0i,
clb_I1,
clb_I1i,
clb_I2,
clb_I2i,
clb_I3,
clb_I3i,
clb_I4,
clb_I4i,
clb_I5,
clb_I5i,
clb_I6,
clb_I6i,
clb_I7,
clb_I7i,
clb_reg_in,
clb_sc_in,
clb_cin,
clb_reset,
clb_clk,
ccff_head,
clb_O,
clb_reg_out,
clb_sc_out,
clb_cout,
ccff_tail);
//----- GLOBAL PORTS -----
input [0:0] pReset;
//----- GLOBAL PORTS -----
input [0:0] prog_clk;
//----- GLOBAL PORTS -----
input [0:0] Test_en;
//----- INPUT PORTS -----
input [0:1] clb_I0;
//----- INPUT PORTS -----
input [0:1] clb_I0i;
//----- INPUT PORTS -----
input [0:1] clb_I1;
//----- INPUT PORTS -----
input [0:1] clb_I1i;
//----- INPUT PORTS -----
input [0:1] clb_I2;
//----- INPUT PORTS -----
input [0:1] clb_I2i;
//----- INPUT PORTS -----
input [0:1] clb_I3;
//----- INPUT PORTS -----
input [0:1] clb_I3i;
//----- INPUT PORTS -----
input [0:1] clb_I4;
//----- INPUT PORTS -----
input [0:1] clb_I4i;
//----- INPUT PORTS -----
input [0:1] clb_I5;
//----- INPUT PORTS -----
input [0:1] clb_I5i;
//----- INPUT PORTS -----
input [0:1] clb_I6;
//----- INPUT PORTS -----
input [0:1] clb_I6i;
//----- INPUT PORTS -----
input [0:1] clb_I7;
//----- INPUT PORTS -----
input [0:1] clb_I7i;
//----- INPUT PORTS -----
input [0:0] clb_reg_in;
//----- INPUT PORTS -----
input [0:0] clb_sc_in;
//----- INPUT PORTS -----
input [0:0] clb_cin;
//----- INPUT PORTS -----
input [0:0] clb_reset;
//----- INPUT PORTS -----
input [0:0] clb_clk;
//----- INPUT PORTS -----
input [0:0] ccff_head;
//----- OUTPUT PORTS -----
output [0:15] clb_O;
//----- OUTPUT PORTS -----
output [0:0] clb_reg_out;
//----- OUTPUT PORTS -----
output [0:0] clb_sc_out;
//----- OUTPUT PORTS -----
output [0:0] clb_cout;
//----- OUTPUT PORTS -----
output [0:0] ccff_tail;
//----- BEGIN wire-connection ports -----
wire [0:1] clb_I0;
wire [0:1] clb_I0i;
wire [0:1] clb_I1;
wire [0:1] clb_I1i;
wire [0:1] clb_I2;
wire [0:1] clb_I2i;
wire [0:1] clb_I3;
wire [0:1] clb_I3i;
wire [0:1] clb_I4;
wire [0:1] clb_I4i;
wire [0:1] clb_I5;
wire [0:1] clb_I5i;
wire [0:1] clb_I6;
wire [0:1] clb_I6i;
wire [0:1] clb_I7;
wire [0:1] clb_I7i;
wire [0:0] clb_reg_in;
wire [0:0] clb_sc_in;
wire [0:0] clb_cin;
wire [0:0] clb_reset;
wire [0:0] clb_clk;
wire [0:15] clb_O;
wire [0:0] clb_reg_out;
wire [0:0] clb_sc_out;
wire [0:0] clb_cout;
//----- END wire-connection ports -----
//----- BEGIN Registered ports -----
//----- END Registered ports -----
wire [0:0] direct_interc_19_out;
wire [0:0] direct_interc_20_out;
wire [0:0] direct_interc_21_out;
wire [0:0] direct_interc_22_out;
wire [0:0] direct_interc_23_out;
wire [0:0] direct_interc_24_out;
wire [0:0] direct_interc_25_out;
wire [0:0] direct_interc_26_out;
wire [0:0] direct_interc_27_out;
wire [0:0] direct_interc_28_out;
wire [0:0] direct_interc_29_out;
wire [0:0] direct_interc_30_out;
wire [0:0] direct_interc_31_out;
wire [0:0] direct_interc_32_out;
wire [0:0] direct_interc_33_out;
wire [0:0] direct_interc_34_out;
wire [0:0] direct_interc_35_out;
wire [0:0] direct_interc_36_out;
wire [0:0] direct_interc_37_out;
wire [0:0] direct_interc_38_out;
wire [0:0] direct_interc_39_out;
wire [0:0] direct_interc_40_out;
wire [0:0] direct_interc_41_out;
wire [0:0] direct_interc_42_out;
wire [0:0] direct_interc_43_out;
wire [0:0] direct_interc_44_out;
wire [0:0] direct_interc_45_out;
wire [0:0] direct_interc_46_out;
wire [0:0] direct_interc_47_out;
wire [0:0] direct_interc_48_out;
wire [0:0] direct_interc_49_out;
wire [0:0] direct_interc_50_out;
wire [0:0] direct_interc_51_out;
wire [0:0] direct_interc_52_out;
wire [0:0] direct_interc_53_out;
wire [0:0] direct_interc_54_out;
wire [0:0] direct_interc_55_out;
wire [0:0] direct_interc_56_out;
wire [0:0] direct_interc_57_out;
wire [0:0] direct_interc_58_out;
wire [0:0] direct_interc_59_out;
wire [0:0] direct_interc_60_out;
wire [0:0] direct_interc_61_out;
wire [0:0] direct_interc_62_out;
wire [0:0] direct_interc_63_out;
wire [0:0] direct_interc_64_out;
wire [0:0] direct_interc_65_out;
wire [0:0] direct_interc_66_out;
wire [0:0] direct_interc_67_out;
wire [0:0] direct_interc_68_out;
wire [0:0] direct_interc_69_out;
wire [0:0] direct_interc_70_out;
wire [0:0] direct_interc_71_out;
wire [0:0] direct_interc_72_out;
wire [0:0] direct_interc_73_out;
wire [0:0] direct_interc_74_out;
wire [0:0] direct_interc_75_out;
wire [0:0] direct_interc_76_out;
wire [0:0] direct_interc_77_out;
wire [0:0] direct_interc_78_out;
wire [0:0] direct_interc_79_out;
wire [0:0] direct_interc_80_out;
wire [0:0] direct_interc_81_out;
wire [0:0] direct_interc_82_out;
wire [0:0] direct_interc_83_out;
wire [0:0] direct_interc_84_out;
wire [0:0] direct_interc_85_out;
wire [0:0] direct_interc_86_out;
wire [0:0] direct_interc_87_out;
wire [0:0] direct_interc_88_out;
wire [0:0] direct_interc_89_out;
wire [0:0] direct_interc_90_out;
wire [0:0] logical_tile_clb_mode_default__fle_0_ccff_tail;
wire [0:0] logical_tile_clb_mode_default__fle_0_fle_cout;
wire [0:1] logical_tile_clb_mode_default__fle_0_fle_out;
wire [0:0] logical_tile_clb_mode_default__fle_0_fle_reg_out;
wire [0:0] logical_tile_clb_mode_default__fle_0_fle_sc_out;
wire [0:0] logical_tile_clb_mode_default__fle_1_ccff_tail;
wire [0:0] logical_tile_clb_mode_default__fle_1_fle_cout;
wire [0:1] logical_tile_clb_mode_default__fle_1_fle_out;
wire [0:0] logical_tile_clb_mode_default__fle_1_fle_reg_out;
wire [0:0] logical_tile_clb_mode_default__fle_1_fle_sc_out;
wire [0:0] logical_tile_clb_mode_default__fle_2_ccff_tail;
wire [0:0] logical_tile_clb_mode_default__fle_2_fle_cout;
wire [0:1] logical_tile_clb_mode_default__fle_2_fle_out;
wire [0:0] logical_tile_clb_mode_default__fle_2_fle_reg_out;
wire [0:0] logical_tile_clb_mode_default__fle_2_fle_sc_out;
wire [0:0] logical_tile_clb_mode_default__fle_3_ccff_tail;
wire [0:0] logical_tile_clb_mode_default__fle_3_fle_cout;
wire [0:1] logical_tile_clb_mode_default__fle_3_fle_out;
wire [0:0] logical_tile_clb_mode_default__fle_3_fle_reg_out;
wire [0:0] logical_tile_clb_mode_default__fle_3_fle_sc_out;
wire [0:0] logical_tile_clb_mode_default__fle_4_ccff_tail;
wire [0:0] logical_tile_clb_mode_default__fle_4_fle_cout;
wire [0:1] logical_tile_clb_mode_default__fle_4_fle_out;
wire [0:0] logical_tile_clb_mode_default__fle_4_fle_reg_out;
wire [0:0] logical_tile_clb_mode_default__fle_4_fle_sc_out;
wire [0:0] logical_tile_clb_mode_default__fle_5_ccff_tail;
wire [0:0] logical_tile_clb_mode_default__fle_5_fle_cout;
wire [0:1] logical_tile_clb_mode_default__fle_5_fle_out;
wire [0:0] logical_tile_clb_mode_default__fle_5_fle_reg_out;
wire [0:0] logical_tile_clb_mode_default__fle_5_fle_sc_out;
wire [0:0] logical_tile_clb_mode_default__fle_6_ccff_tail;
wire [0:0] logical_tile_clb_mode_default__fle_6_fle_cout;
wire [0:1] logical_tile_clb_mode_default__fle_6_fle_out;
wire [0:0] logical_tile_clb_mode_default__fle_6_fle_reg_out;
wire [0:0] logical_tile_clb_mode_default__fle_6_fle_sc_out;
wire [0:0] logical_tile_clb_mode_default__fle_7_fle_cout;
wire [0:1] logical_tile_clb_mode_default__fle_7_fle_out;
wire [0:0] logical_tile_clb_mode_default__fle_7_fle_reg_out;
wire [0:0] logical_tile_clb_mode_default__fle_7_fle_sc_out;
// ----- BEGIN Local short connections -----
// ----- END Local short connections -----
// ----- BEGIN Local output short connections -----
// ----- END Local output short connections -----
logical_tile_clb_mode_default__fle logical_tile_clb_mode_default__fle_0 (
.pReset(pReset),
.prog_clk(prog_clk),
.Test_en(Test_en),
.fle_in({direct_interc_19_out, direct_interc_20_out, direct_interc_21_out, direct_interc_22_out}),
.fle_reg_in(direct_interc_23_out),
.fle_sc_in(direct_interc_24_out),
.fle_cin(direct_interc_25_out),
.fle_reset(direct_interc_26_out),
.fle_clk(direct_interc_27_out),
.ccff_head(ccff_head),
.fle_out(logical_tile_clb_mode_default__fle_0_fle_out[0:1]),
.fle_reg_out(logical_tile_clb_mode_default__fle_0_fle_reg_out),
.fle_sc_out(logical_tile_clb_mode_default__fle_0_fle_sc_out),
.fle_cout(logical_tile_clb_mode_default__fle_0_fle_cout),
.ccff_tail(logical_tile_clb_mode_default__fle_0_ccff_tail));
logical_tile_clb_mode_default__fle logical_tile_clb_mode_default__fle_1 (
.pReset(pReset),
.prog_clk(prog_clk),
.Test_en(Test_en),
.fle_in({direct_interc_28_out, direct_interc_29_out, direct_interc_30_out, direct_interc_31_out}),
.fle_reg_in(direct_interc_32_out),
.fle_sc_in(direct_interc_33_out),
.fle_cin(direct_interc_34_out),
.fle_reset(direct_interc_35_out),
.fle_clk(direct_interc_36_out),
.ccff_head(logical_tile_clb_mode_default__fle_0_ccff_tail),
.fle_out(logical_tile_clb_mode_default__fle_1_fle_out[0:1]),
.fle_reg_out(logical_tile_clb_mode_default__fle_1_fle_reg_out),
.fle_sc_out(logical_tile_clb_mode_default__fle_1_fle_sc_out),
.fle_cout(logical_tile_clb_mode_default__fle_1_fle_cout),
.ccff_tail(logical_tile_clb_mode_default__fle_1_ccff_tail));
logical_tile_clb_mode_default__fle logical_tile_clb_mode_default__fle_2 (
.pReset(pReset),
.prog_clk(prog_clk),
.Test_en(Test_en),
.fle_in({direct_interc_37_out, direct_interc_38_out, direct_interc_39_out, direct_interc_40_out}),
.fle_reg_in(direct_interc_41_out),
.fle_sc_in(direct_interc_42_out),
.fle_cin(direct_interc_43_out),
.fle_reset(direct_interc_44_out),
.fle_clk(direct_interc_45_out),
.ccff_head(logical_tile_clb_mode_default__fle_1_ccff_tail),
.fle_out(logical_tile_clb_mode_default__fle_2_fle_out[0:1]),
.fle_reg_out(logical_tile_clb_mode_default__fle_2_fle_reg_out),
.fle_sc_out(logical_tile_clb_mode_default__fle_2_fle_sc_out),
.fle_cout(logical_tile_clb_mode_default__fle_2_fle_cout),
.ccff_tail(logical_tile_clb_mode_default__fle_2_ccff_tail));
logical_tile_clb_mode_default__fle logical_tile_clb_mode_default__fle_3 (
.pReset(pReset),
.prog_clk(prog_clk),
.Test_en(Test_en),
.fle_in({direct_interc_46_out, direct_interc_47_out, direct_interc_48_out, direct_interc_49_out}),
.fle_reg_in(direct_interc_50_out),
.fle_sc_in(direct_interc_51_out),
.fle_cin(direct_interc_52_out),
.fle_reset(direct_interc_53_out),
.fle_clk(direct_interc_54_out),
.ccff_head(logical_tile_clb_mode_default__fle_2_ccff_tail),
.fle_out(logical_tile_clb_mode_default__fle_3_fle_out[0:1]),
.fle_reg_out(logical_tile_clb_mode_default__fle_3_fle_reg_out),
.fle_sc_out(logical_tile_clb_mode_default__fle_3_fle_sc_out),
.fle_cout(logical_tile_clb_mode_default__fle_3_fle_cout),
.ccff_tail(logical_tile_clb_mode_default__fle_3_ccff_tail));
logical_tile_clb_mode_default__fle logical_tile_clb_mode_default__fle_4 (
.pReset(pReset),
.prog_clk(prog_clk),
.Test_en(Test_en),
.fle_in({direct_interc_55_out, direct_interc_56_out, direct_interc_57_out, direct_interc_58_out}),
.fle_reg_in(direct_interc_59_out),
.fle_sc_in(direct_interc_60_out),
.fle_cin(direct_interc_61_out),
.fle_reset(direct_interc_62_out),
.fle_clk(direct_interc_63_out),
.ccff_head(logical_tile_clb_mode_default__fle_3_ccff_tail),
.fle_out(logical_tile_clb_mode_default__fle_4_fle_out[0:1]),
.fle_reg_out(logical_tile_clb_mode_default__fle_4_fle_reg_out),
.fle_sc_out(logical_tile_clb_mode_default__fle_4_fle_sc_out),
.fle_cout(logical_tile_clb_mode_default__fle_4_fle_cout),
.ccff_tail(logical_tile_clb_mode_default__fle_4_ccff_tail));
logical_tile_clb_mode_default__fle logical_tile_clb_mode_default__fle_5 (
.pReset(pReset),
.prog_clk(prog_clk),
.Test_en(Test_en),
.fle_in({direct_interc_64_out, direct_interc_65_out, direct_interc_66_out, direct_interc_67_out}),
.fle_reg_in(direct_interc_68_out),
.fle_sc_in(direct_interc_69_out),
.fle_cin(direct_interc_70_out),
.fle_reset(direct_interc_71_out),
.fle_clk(direct_interc_72_out),
.ccff_head(logical_tile_clb_mode_default__fle_4_ccff_tail),
.fle_out(logical_tile_clb_mode_default__fle_5_fle_out[0:1]),
.fle_reg_out(logical_tile_clb_mode_default__fle_5_fle_reg_out),
.fle_sc_out(logical_tile_clb_mode_default__fle_5_fle_sc_out),
.fle_cout(logical_tile_clb_mode_default__fle_5_fle_cout),
.ccff_tail(logical_tile_clb_mode_default__fle_5_ccff_tail));
logical_tile_clb_mode_default__fle logical_tile_clb_mode_default__fle_6 (
.pReset(pReset),
.prog_clk(prog_clk),
.Test_en(Test_en),
.fle_in({direct_interc_73_out, direct_interc_74_out, direct_interc_75_out, direct_interc_76_out}),
.fle_reg_in(direct_interc_77_out),
.fle_sc_in(direct_interc_78_out),
.fle_cin(direct_interc_79_out),
.fle_reset(direct_interc_80_out),
.fle_clk(direct_interc_81_out),
.ccff_head(logical_tile_clb_mode_default__fle_5_ccff_tail),
.fle_out(logical_tile_clb_mode_default__fle_6_fle_out[0:1]),
.fle_reg_out(logical_tile_clb_mode_default__fle_6_fle_reg_out),
.fle_sc_out(logical_tile_clb_mode_default__fle_6_fle_sc_out),
.fle_cout(logical_tile_clb_mode_default__fle_6_fle_cout),
.ccff_tail(logical_tile_clb_mode_default__fle_6_ccff_tail));
logical_tile_clb_mode_default__fle logical_tile_clb_mode_default__fle_7 (
.pReset(pReset),
.prog_clk(prog_clk),
.Test_en(Test_en),
.fle_in({direct_interc_82_out, direct_interc_83_out, direct_interc_84_out, direct_interc_85_out}),
.fle_reg_in(direct_interc_86_out),
.fle_sc_in(direct_interc_87_out),
.fle_cin(direct_interc_88_out),
.fle_reset(direct_interc_89_out),
.fle_clk(direct_interc_90_out),
.ccff_head(logical_tile_clb_mode_default__fle_6_ccff_tail),
.fle_out(logical_tile_clb_mode_default__fle_7_fle_out[0:1]),
.fle_reg_out(logical_tile_clb_mode_default__fle_7_fle_reg_out),
.fle_sc_out(logical_tile_clb_mode_default__fle_7_fle_sc_out),
.fle_cout(logical_tile_clb_mode_default__fle_7_fle_cout),
.ccff_tail(ccff_tail));
direct_interc direct_interc_0_ (
.in(logical_tile_clb_mode_default__fle_0_fle_out[1]),
.out(clb_O[0]));
direct_interc direct_interc_1_ (
.in(logical_tile_clb_mode_default__fle_0_fle_out[0]),
.out(clb_O[1]));
direct_interc direct_interc_2_ (
.in(logical_tile_clb_mode_default__fle_1_fle_out[1]),
.out(clb_O[2]));
direct_interc direct_interc_3_ (
.in(logical_tile_clb_mode_default__fle_1_fle_out[0]),
.out(clb_O[3]));
direct_interc direct_interc_4_ (
.in(logical_tile_clb_mode_default__fle_2_fle_out[1]),
.out(clb_O[4]));
direct_interc direct_interc_5_ (
.in(logical_tile_clb_mode_default__fle_2_fle_out[0]),
.out(clb_O[5]));
direct_interc direct_interc_6_ (
.in(logical_tile_clb_mode_default__fle_3_fle_out[1]),
.out(clb_O[6]));
direct_interc direct_interc_7_ (
.in(logical_tile_clb_mode_default__fle_3_fle_out[0]),
.out(clb_O[7]));
direct_interc direct_interc_8_ (
.in(logical_tile_clb_mode_default__fle_4_fle_out[1]),
.out(clb_O[8]));
direct_interc direct_interc_9_ (
.in(logical_tile_clb_mode_default__fle_4_fle_out[0]),
.out(clb_O[9]));
direct_interc direct_interc_10_ (
.in(logical_tile_clb_mode_default__fle_5_fle_out[1]),
.out(clb_O[10]));
direct_interc direct_interc_11_ (
.in(logical_tile_clb_mode_default__fle_5_fle_out[0]),
.out(clb_O[11]));
direct_interc direct_interc_12_ (
.in(logical_tile_clb_mode_default__fle_6_fle_out[1]),
.out(clb_O[12]));
direct_interc direct_interc_13_ (
.in(logical_tile_clb_mode_default__fle_6_fle_out[0]),
.out(clb_O[13]));
direct_interc direct_interc_14_ (
.in(logical_tile_clb_mode_default__fle_7_fle_out[1]),
.out(clb_O[14]));
direct_interc direct_interc_15_ (
.in(logical_tile_clb_mode_default__fle_7_fle_out[0]),
.out(clb_O[15]));
direct_interc direct_interc_16_ (
.in(logical_tile_clb_mode_default__fle_7_fle_reg_out),
.out(clb_reg_out));
direct_interc direct_interc_17_ (
.in(logical_tile_clb_mode_default__fle_7_fle_sc_out),
.out(clb_sc_out));
direct_interc direct_interc_18_ (
.in(logical_tile_clb_mode_default__fle_7_fle_cout),
.out(clb_cout));
direct_interc direct_interc_19_ (
.in(clb_I0[0]),
.out(direct_interc_19_out));
direct_interc direct_interc_20_ (
.in(clb_I0[1]),
.out(direct_interc_20_out));
direct_interc direct_interc_21_ (
.in(clb_I0i[0]),
.out(direct_interc_21_out));
direct_interc direct_interc_22_ (
.in(clb_I0i[1]),
.out(direct_interc_22_out));
direct_interc direct_interc_23_ (
.in(clb_reg_in),
.out(direct_interc_23_out));
direct_interc direct_interc_24_ (
.in(clb_sc_in),
.out(direct_interc_24_out));
direct_interc direct_interc_25_ (
.in(clb_cin),
.out(direct_interc_25_out));
direct_interc direct_interc_26_ (
.in(clb_reset),
.out(direct_interc_26_out));
direct_interc direct_interc_27_ (
.in(clb_clk),
.out(direct_interc_27_out));
direct_interc direct_interc_28_ (
.in(clb_I1[0]),
.out(direct_interc_28_out));
direct_interc direct_interc_29_ (
.in(clb_I1[1]),
.out(direct_interc_29_out));
direct_interc direct_interc_30_ (
.in(clb_I1i[0]),
.out(direct_interc_30_out));
direct_interc direct_interc_31_ (
.in(clb_I1i[1]),
.out(direct_interc_31_out));
direct_interc direct_interc_32_ (
.in(logical_tile_clb_mode_default__fle_0_fle_reg_out),
.out(direct_interc_32_out));
direct_interc direct_interc_33_ (
.in(logical_tile_clb_mode_default__fle_0_fle_sc_out),
.out(direct_interc_33_out));
direct_interc direct_interc_34_ (
.in(logical_tile_clb_mode_default__fle_0_fle_cout),
.out(direct_interc_34_out));
direct_interc direct_interc_35_ (
.in(clb_reset),
.out(direct_interc_35_out));
direct_interc direct_interc_36_ (
.in(clb_clk),
.out(direct_interc_36_out));
direct_interc direct_interc_37_ (
.in(clb_I2[0]),
.out(direct_interc_37_out));
direct_interc direct_interc_38_ (
.in(clb_I2[1]),
.out(direct_interc_38_out));
direct_interc direct_interc_39_ (
.in(clb_I2i[0]),
.out(direct_interc_39_out));
direct_interc direct_interc_40_ (
.in(clb_I2i[1]),
.out(direct_interc_40_out));
direct_interc direct_interc_41_ (
.in(logical_tile_clb_mode_default__fle_1_fle_reg_out),
.out(direct_interc_41_out));
direct_interc direct_interc_42_ (
.in(logical_tile_clb_mode_default__fle_1_fle_sc_out),
.out(direct_interc_42_out));
direct_interc direct_interc_43_ (
.in(logical_tile_clb_mode_default__fle_1_fle_cout),
.out(direct_interc_43_out));
direct_interc direct_interc_44_ (
.in(clb_reset),
.out(direct_interc_44_out));
direct_interc direct_interc_45_ (
.in(clb_clk),
.out(direct_interc_45_out));
direct_interc direct_interc_46_ (
.in(clb_I3[0]),
.out(direct_interc_46_out));
direct_interc direct_interc_47_ (
.in(clb_I3[1]),
.out(direct_interc_47_out));
direct_interc direct_interc_48_ (
.in(clb_I3i[0]),
.out(direct_interc_48_out));
direct_interc direct_interc_49_ (
.in(clb_I3i[1]),
.out(direct_interc_49_out));
direct_interc direct_interc_50_ (
.in(logical_tile_clb_mode_default__fle_2_fle_reg_out),
.out(direct_interc_50_out));
direct_interc direct_interc_51_ (
.in(logical_tile_clb_mode_default__fle_2_fle_sc_out),
.out(direct_interc_51_out));
direct_interc direct_interc_52_ (
.in(logical_tile_clb_mode_default__fle_2_fle_cout),
.out(direct_interc_52_out));
direct_interc direct_interc_53_ (
.in(clb_reset),
.out(direct_interc_53_out));
direct_interc direct_interc_54_ (
.in(clb_clk),
.out(direct_interc_54_out));
direct_interc direct_interc_55_ (
.in(clb_I4[0]),
.out(direct_interc_55_out));
direct_interc direct_interc_56_ (
.in(clb_I4[1]),
.out(direct_interc_56_out));
direct_interc direct_interc_57_ (
.in(clb_I4i[0]),
.out(direct_interc_57_out));
direct_interc direct_interc_58_ (
.in(clb_I4i[1]),
.out(direct_interc_58_out));
direct_interc direct_interc_59_ (
.in(logical_tile_clb_mode_default__fle_3_fle_reg_out),
.out(direct_interc_59_out));
direct_interc direct_interc_60_ (
.in(logical_tile_clb_mode_default__fle_3_fle_sc_out),
.out(direct_interc_60_out));
direct_interc direct_interc_61_ (
.in(logical_tile_clb_mode_default__fle_3_fle_cout),
.out(direct_interc_61_out));
direct_interc direct_interc_62_ (
.in(clb_reset),
.out(direct_interc_62_out));
direct_interc direct_interc_63_ (
.in(clb_clk),
.out(direct_interc_63_out));
direct_interc direct_interc_64_ (
.in(clb_I5[0]),
.out(direct_interc_64_out));
direct_interc direct_interc_65_ (
.in(clb_I5[1]),
.out(direct_interc_65_out));
direct_interc direct_interc_66_ (
.in(clb_I5i[0]),
.out(direct_interc_66_out));
direct_interc direct_interc_67_ (
.in(clb_I5i[1]),
.out(direct_interc_67_out));
direct_interc direct_interc_68_ (
.in(logical_tile_clb_mode_default__fle_4_fle_reg_out),
.out(direct_interc_68_out));
direct_interc direct_interc_69_ (
.in(logical_tile_clb_mode_default__fle_4_fle_sc_out),
.out(direct_interc_69_out));
direct_interc direct_interc_70_ (
.in(logical_tile_clb_mode_default__fle_4_fle_cout),
.out(direct_interc_70_out));
direct_interc direct_interc_71_ (
.in(clb_reset),
.out(direct_interc_71_out));
direct_interc direct_interc_72_ (
.in(clb_clk),
.out(direct_interc_72_out));
direct_interc direct_interc_73_ (
.in(clb_I6[0]),
.out(direct_interc_73_out));
direct_interc direct_interc_74_ (
.in(clb_I6[1]),
.out(direct_interc_74_out));
direct_interc direct_interc_75_ (
.in(clb_I6i[0]),
.out(direct_interc_75_out));
direct_interc direct_interc_76_ (
.in(clb_I6i[1]),
.out(direct_interc_76_out));
direct_interc direct_interc_77_ (
.in(logical_tile_clb_mode_default__fle_5_fle_reg_out),
.out(direct_interc_77_out));
direct_interc direct_interc_78_ (
.in(logical_tile_clb_mode_default__fle_5_fle_sc_out),
.out(direct_interc_78_out));
direct_interc direct_interc_79_ (
.in(logical_tile_clb_mode_default__fle_5_fle_cout),
.out(direct_interc_79_out));
direct_interc direct_interc_80_ (
.in(clb_reset),
.out(direct_interc_80_out));
direct_interc direct_interc_81_ (
.in(clb_clk),
.out(direct_interc_81_out));
direct_interc direct_interc_82_ (
.in(clb_I7[0]),
.out(direct_interc_82_out));
direct_interc direct_interc_83_ (
.in(clb_I7[1]),
.out(direct_interc_83_out));
direct_interc direct_interc_84_ (
.in(clb_I7i[0]),
.out(direct_interc_84_out));
direct_interc direct_interc_85_ (
.in(clb_I7i[1]),
.out(direct_interc_85_out));
direct_interc direct_interc_86_ (
.in(logical_tile_clb_mode_default__fle_6_fle_reg_out),
.out(direct_interc_86_out));
direct_interc direct_interc_87_ (
.in(logical_tile_clb_mode_default__fle_6_fle_sc_out),
.out(direct_interc_87_out));
direct_interc direct_interc_88_ (
.in(logical_tile_clb_mode_default__fle_6_fle_cout),
.out(direct_interc_88_out));
direct_interc direct_interc_89_ (
.in(clb_reset),
.out(direct_interc_89_out));
direct_interc direct_interc_90_ (
.in(clb_clk),
.out(direct_interc_90_out));
endmodule
// ----- END Verilog module for logical_tile_clb_mode_clb_ -----
//----- Default net type -----
`default_nettype none
// ----- END Physical programmable logic block Verilog module: clb -----

180
SOFA_A/SOFA_A_verilog/lb/logical_tile_clb_mode_default__fle.v Normal file
View File

@ -0,0 +1,180 @@
//-------------------------------------------
// FPGA Synthesizable Verilog Netlist
// Description: Verilog modules for pb_type: fle
// Author: Xifan TANG
// Organization: University of Utah
// Date: Sun Feb 19 10:53:27 2023
//-------------------------------------------
//----- Time scale -----
`timescale 1ns / 1ps
// ----- BEGIN Physical programmable logic block Verilog module: fle -----
//----- Default net type -----
`default_nettype none
// ----- Verilog module for logical_tile_clb_mode_default__fle -----
module logical_tile_clb_mode_default__fle(pReset,
prog_clk,
Test_en,
fle_in,
fle_reg_in,
fle_sc_in,
fle_cin,
fle_reset,
fle_clk,
ccff_head,
fle_out,
fle_reg_out,
fle_sc_out,
fle_cout,
ccff_tail);
//----- GLOBAL PORTS -----
input [0:0] pReset;
//----- GLOBAL PORTS -----
input [0:0] prog_clk;
//----- GLOBAL PORTS -----
input [0:0] Test_en;
//----- INPUT PORTS -----
input [0:3] fle_in;
//----- INPUT PORTS -----
input [0:0] fle_reg_in;
//----- INPUT PORTS -----
input [0:0] fle_sc_in;
//----- INPUT PORTS -----
input [0:0] fle_cin;
//----- INPUT PORTS -----
input [0:0] fle_reset;
//----- INPUT PORTS -----
input [0:0] fle_clk;
//----- INPUT PORTS -----
input [0:0] ccff_head;
//----- OUTPUT PORTS -----
output [0:1] fle_out;
//----- OUTPUT PORTS -----
output [0:0] fle_reg_out;
//----- OUTPUT PORTS -----
output [0:0] fle_sc_out;
//----- OUTPUT PORTS -----
output [0:0] fle_cout;
//----- OUTPUT PORTS -----
output [0:0] ccff_tail;
//----- BEGIN wire-connection ports -----
wire [0:3] fle_in;
wire [0:0] fle_reg_in;
wire [0:0] fle_sc_in;
wire [0:0] fle_cin;
wire [0:0] fle_reset;
wire [0:0] fle_clk;
wire [0:1] fle_out;
wire [0:0] fle_reg_out;
wire [0:0] fle_sc_out;
wire [0:0] fle_cout;
//----- END wire-connection ports -----
//----- BEGIN Registered ports -----
//----- END Registered ports -----
wire [0:0] direct_interc_10_out;
wire [0:0] direct_interc_11_out;
wire [0:0] direct_interc_12_out;
wire [0:0] direct_interc_13_out;
wire [0:0] direct_interc_5_out;
wire [0:0] direct_interc_6_out;
wire [0:0] direct_interc_7_out;
wire [0:0] direct_interc_8_out;
wire [0:0] direct_interc_9_out;
wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_0_fabric_cout;
wire [0:1] logical_tile_clb_mode_default__fle_mode_physical__fabric_0_fabric_out;
wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_0_fabric_reg_out;
wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_0_fabric_sc_out;
// ----- BEGIN Local short connections -----
// ----- END Local short connections -----
// ----- BEGIN Local output short connections -----
// ----- END Local output short connections -----
logical_tile_clb_mode_default__fle_mode_physical__fabric logical_tile_clb_mode_default__fle_mode_physical__fabric_0 (
.pReset(pReset),
.prog_clk(prog_clk),
.Test_en(Test_en),
.fabric_in({direct_interc_5_out, direct_interc_6_out, direct_interc_7_out, direct_interc_8_out}),
.fabric_reg_in(direct_interc_9_out),
.fabric_sc_in(direct_interc_10_out),
.fabric_cin(direct_interc_11_out),
.fabric_reset(direct_interc_12_out),
.fabric_clk(direct_interc_13_out),
.ccff_head(ccff_head),
.fabric_out(logical_tile_clb_mode_default__fle_mode_physical__fabric_0_fabric_out[0:1]),
.fabric_reg_out(logical_tile_clb_mode_default__fle_mode_physical__fabric_0_fabric_reg_out),
.fabric_sc_out(logical_tile_clb_mode_default__fle_mode_physical__fabric_0_fabric_sc_out),
.fabric_cout(logical_tile_clb_mode_default__fle_mode_physical__fabric_0_fabric_cout),
.ccff_tail(ccff_tail));
direct_interc direct_interc_0_ (
.in(logical_tile_clb_mode_default__fle_mode_physical__fabric_0_fabric_out[0]),
.out(fle_out[0]));
direct_interc direct_interc_1_ (
.in(logical_tile_clb_mode_default__fle_mode_physical__fabric_0_fabric_out[1]),
.out(fle_out[1]));
direct_interc direct_interc_2_ (
.in(logical_tile_clb_mode_default__fle_mode_physical__fabric_0_fabric_reg_out),
.out(fle_reg_out));
direct_interc direct_interc_3_ (
.in(logical_tile_clb_mode_default__fle_mode_physical__fabric_0_fabric_sc_out),
.out(fle_sc_out));
direct_interc direct_interc_4_ (
.in(logical_tile_clb_mode_default__fle_mode_physical__fabric_0_fabric_cout),
.out(fle_cout));
direct_interc direct_interc_5_ (
.in(fle_in[0]),
.out(direct_interc_5_out));
direct_interc direct_interc_6_ (
.in(fle_in[1]),
.out(direct_interc_6_out));
direct_interc direct_interc_7_ (
.in(fle_in[2]),
.out(direct_interc_7_out));
direct_interc direct_interc_8_ (
.in(fle_in[3]),
.out(direct_interc_8_out));
direct_interc direct_interc_9_ (
.in(fle_reg_in),
.out(direct_interc_9_out));
direct_interc direct_interc_10_ (
.in(fle_sc_in),
.out(direct_interc_10_out));
direct_interc direct_interc_11_ (
.in(fle_cin),
.out(direct_interc_11_out));
direct_interc direct_interc_12_ (
.in(fle_reset),
.out(direct_interc_12_out));
direct_interc direct_interc_13_ (
.in(fle_clk),
.out(direct_interc_13_out));
endmodule
// ----- END Verilog module for logical_tile_clb_mode_default__fle -----
//----- Default net type -----
`default_nettype none
// ----- END Physical programmable logic block Verilog module: fle -----

257
SOFA_A/SOFA_A_verilog/lb/logical_tile_clb_mode_default__fle_mode_physical__fabric.v Normal file
View File

@ -0,0 +1,257 @@
//-------------------------------------------
// FPGA Synthesizable Verilog Netlist
// Description: Verilog modules for pb_type: fabric
// Author: Xifan TANG
// Organization: University of Utah
// Date: Sun Feb 19 10:53:27 2023
//-------------------------------------------
//----- Time scale -----
`timescale 1ns / 1ps
// ----- BEGIN Physical programmable logic block Verilog module: fabric -----
//----- Default net type -----
`default_nettype none
// ----- Verilog module for logical_tile_clb_mode_default__fle_mode_physical__fabric -----
module logical_tile_clb_mode_default__fle_mode_physical__fabric(pReset,
prog_clk,
Test_en,
fabric_in,
fabric_reg_in,
fabric_sc_in,
fabric_cin,
fabric_reset,
fabric_clk,
ccff_head,
fabric_out,
fabric_reg_out,
fabric_sc_out,
fabric_cout,
ccff_tail);
//----- GLOBAL PORTS -----
input [0:0] pReset;
//----- GLOBAL PORTS -----
input [0:0] prog_clk;
//----- GLOBAL PORTS -----
input [0:0] Test_en;
//----- INPUT PORTS -----
input [0:3] fabric_in;
//----- INPUT PORTS -----
input [0:0] fabric_reg_in;
//----- INPUT PORTS -----
input [0:0] fabric_sc_in;
//----- INPUT PORTS -----
input [0:0] fabric_cin;
//----- INPUT PORTS -----
input [0:0] fabric_reset;
//----- INPUT PORTS -----
input [0:0] fabric_clk;
//----- INPUT PORTS -----
input [0:0] ccff_head;
//----- OUTPUT PORTS -----
output [0:1] fabric_out;
//----- OUTPUT PORTS -----
output [0:0] fabric_reg_out;
//----- OUTPUT PORTS -----
output [0:0] fabric_sc_out;
//----- OUTPUT PORTS -----
output [0:0] fabric_cout;
//----- OUTPUT PORTS -----
output [0:0] ccff_tail;
//----- BEGIN wire-connection ports -----
wire [0:3] fabric_in;
wire [0:0] fabric_reg_in;
wire [0:0] fabric_sc_in;
wire [0:0] fabric_cin;
wire [0:0] fabric_reset;
wire [0:0] fabric_clk;
wire [0:1] fabric_out;
wire [0:0] fabric_reg_out;
wire [0:0] fabric_sc_out;
wire [0:0] fabric_cout;
//----- END wire-connection ports -----
//----- BEGIN Registered ports -----
//----- END Registered ports -----
wire [0:0] direct_interc_10_out;
wire [0:0] direct_interc_11_out;
wire [0:0] direct_interc_12_out;
wire [0:0] direct_interc_13_out;
wire [0:0] direct_interc_3_out;
wire [0:0] direct_interc_4_out;
wire [0:0] direct_interc_5_out;
wire [0:0] direct_interc_6_out;
wire [0:0] direct_interc_7_out;
wire [0:0] direct_interc_8_out;
wire [0:0] direct_interc_9_out;
wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q;
wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_1_ff_Q;
wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail;
wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_cout;
wire [0:1] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out;
wire [0:1] mux_fabric_out_0_undriven_sram_inv;
wire [0:1] mux_fabric_out_1_undriven_sram_inv;
wire [0:1] mux_ff_0_D_0_undriven_sram_inv;
wire [0:1] mux_ff_1_D_0_undriven_sram_inv;
wire [0:1] mux_tree_size2_0_sram;
wire [0:1] mux_tree_size2_1_sram;
wire [0:0] mux_tree_size2_2_out;
wire [0:1] mux_tree_size2_2_sram;
wire [0:0] mux_tree_size2_3_out;
wire [0:1] mux_tree_size2_3_sram;
wire [0:0] mux_tree_size2_mem_0_ccff_tail;
wire [0:0] mux_tree_size2_mem_1_ccff_tail;
wire [0:0] mux_tree_size2_mem_2_ccff_tail;
// ----- BEGIN Local short connections -----
// ----- END Local short connections -----
// ----- BEGIN Local output short connections -----
// ----- END Local output short connections -----
logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0 (
.pReset(pReset),
.prog_clk(prog_clk),
.frac_logic_in({direct_interc_3_out, direct_interc_4_out, direct_interc_5_out, direct_interc_6_out}),
.frac_logic_cin(direct_interc_7_out),
.ccff_head(ccff_head),
.frac_logic_out(logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[0:1]),
.frac_logic_cout(logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_cout),
.ccff_tail(logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail));
logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0 (
.Test_en(Test_en),
.ff_D(mux_tree_size2_2_out),
.ff_DI(direct_interc_8_out),
.ff_reset(direct_interc_9_out),
.ff_Q(logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q),
.ff_clk(direct_interc_10_out));
logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_1 (
.Test_en(Test_en),
.ff_D(mux_tree_size2_3_out),
.ff_DI(direct_interc_11_out),
.ff_reset(direct_interc_12_out),
.ff_Q(logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_1_ff_Q),
.ff_clk(direct_interc_13_out));
mux_tree_size2 mux_fabric_out_0 (
.in({logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q, logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[0]}),
.sram(mux_tree_size2_0_sram[0:1]),
.sram_inv(mux_fabric_out_0_undriven_sram_inv[0:1]),
.out(fabric_out[0]));
mux_tree_size2 mux_fabric_out_1 (
.in({logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_1_ff_Q, logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[1]}),
.sram(mux_tree_size2_1_sram[0:1]),
.sram_inv(mux_fabric_out_1_undriven_sram_inv[0:1]),
.out(fabric_out[1]));
mux_tree_size2 mux_ff_0_D_0 (
.in({logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[0], fabric_reg_in}),
.sram(mux_tree_size2_2_sram[0:1]),
.sram_inv(mux_ff_0_D_0_undriven_sram_inv[0:1]),
.out(mux_tree_size2_2_out));
mux_tree_size2 mux_ff_1_D_0 (
.in({logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[1], logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q}),
.sram(mux_tree_size2_3_sram[0:1]),
.sram_inv(mux_ff_1_D_0_undriven_sram_inv[0:1]),
.out(mux_tree_size2_3_out));
mux_tree_size2_mem mem_fabric_out_0 (
.pReset(pReset),
.prog_clk(prog_clk),
.ccff_head(logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail),
.ccff_tail(mux_tree_size2_mem_0_ccff_tail),
.mem_out(mux_tree_size2_0_sram[0:1]));
mux_tree_size2_mem mem_fabric_out_1 (
.pReset(pReset),
.prog_clk(prog_clk),
.ccff_head(mux_tree_size2_mem_0_ccff_tail),
.ccff_tail(mux_tree_size2_mem_1_ccff_tail),
.mem_out(mux_tree_size2_1_sram[0:1]));
mux_tree_size2_mem mem_ff_0_D_0 (
.pReset(pReset),
.prog_clk(prog_clk),
.ccff_head(mux_tree_size2_mem_1_ccff_tail),
.ccff_tail(mux_tree_size2_mem_2_ccff_tail),
.mem_out(mux_tree_size2_2_sram[0:1]));
mux_tree_size2_mem mem_ff_1_D_0 (
.pReset(pReset),
.prog_clk(prog_clk),
.ccff_head(mux_tree_size2_mem_2_ccff_tail),
.ccff_tail(ccff_tail),
.mem_out(mux_tree_size2_3_sram[0:1]));
direct_interc direct_interc_0_ (
.in(logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_1_ff_Q),
.out(fabric_reg_out));
direct_interc direct_interc_1_ (
.in(logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_1_ff_Q),
.out(fabric_sc_out));
direct_interc direct_interc_2_ (
.in(logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_cout),
.out(fabric_cout));
direct_interc direct_interc_3_ (
.in(fabric_in[0]),
.out(direct_interc_3_out));
direct_interc direct_interc_4_ (
.in(fabric_in[1]),
.out(direct_interc_4_out));
direct_interc direct_interc_5_ (
.in(fabric_in[2]),
.out(direct_interc_5_out));
direct_interc direct_interc_6_ (
.in(fabric_in[3]),
.out(direct_interc_6_out));
direct_interc direct_interc_7_ (
.in(fabric_cin),
.out(direct_interc_7_out));
direct_interc direct_interc_8_ (
.in(fabric_sc_in),
.out(direct_interc_8_out));
direct_interc direct_interc_9_ (
.in(fabric_reset),
.out(direct_interc_9_out));
direct_interc direct_interc_10_ (
.in(fabric_clk),
.out(direct_interc_10_out));
direct_interc direct_interc_11_ (
.in(logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q),
.out(direct_interc_11_out));
direct_interc direct_interc_12_ (
.in(fabric_reset),
.out(direct_interc_12_out));
direct_interc direct_interc_13_ (
.in(fabric_clk),
.out(direct_interc_13_out));
endmodule
// ----- END Verilog module for logical_tile_clb_mode_default__fle_mode_physical__fabric -----
//----- Default net type -----
`default_nettype none
// ----- END Physical programmable logic block Verilog module: fabric -----

68
SOFA_A/SOFA_A_verilog/lb/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff.v Normal file
View File

@ -0,0 +1,68 @@
//-------------------------------------------
// FPGA Synthesizable Verilog Netlist
// Description: Verilog modules for primitive pb_type: ff
// Author: Xifan TANG
// Organization: University of Utah
// Date: Sun Feb 19 10:53:27 2023
//-------------------------------------------
//----- Time scale -----
`timescale 1ns / 1ps
//----- Default net type -----
`default_nettype none
// ----- Verilog module for logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff -----
module logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff(Test_en,
ff_D,
ff_DI,
ff_reset,
ff_Q,
ff_clk);
//----- GLOBAL PORTS -----
input [0:0] Test_en;
//----- INPUT PORTS -----
input [0:0] ff_D;
//----- INPUT PORTS -----
input [0:0] ff_DI;
//----- INPUT PORTS -----
input [0:0] ff_reset;
//----- OUTPUT PORTS -----
output [0:0] ff_Q;
//----- CLOCK PORTS -----
input [0:0] ff_clk;
//----- BEGIN wire-connection ports -----
wire [0:0] ff_D;
wire [0:0] ff_DI;
wire [0:0] ff_reset;
wire [0:0] ff_Q;
wire [0:0] ff_clk;
//----- END wire-connection ports -----
//----- BEGIN Registered ports -----
//----- END Registered ports -----
// ----- BEGIN Local short connections -----
// ----- END Local short connections -----
// ----- BEGIN Local output short connections -----
// ----- END Local output short connections -----
sky130_fd_sc_hd__sdfrtp_1 sky130_fd_sc_hd__sdfrtp_1_0_ (
.SCE(Test_en),
.D(ff_D),
.SCD(ff_DI),
.RESET_B(ff_reset),
.CLK(ff_clk),
.Q(ff_Q));
endmodule
// ----- END Verilog module for logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff -----
//----- Default net type -----
`default_nettype none

158
SOFA_A/SOFA_A_verilog/lb/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic.v Normal file
View File

@ -0,0 +1,158 @@
//-------------------------------------------
// FPGA Synthesizable Verilog Netlist
// Description: Verilog modules for pb_type: frac_logic
// Author: Xifan TANG
// Organization: University of Utah
// Date: Sun Feb 19 10:53:27 2023
//-------------------------------------------
//----- Time scale -----
`timescale 1ns / 1ps
// ----- BEGIN Physical programmable logic block Verilog module: frac_logic -----
//----- Default net type -----
`default_nettype none
// ----- Verilog module for logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic -----
module logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic(pReset,
prog_clk,
frac_logic_in,
frac_logic_cin,
ccff_head,
frac_logic_out,
frac_logic_cout,
ccff_tail);
//----- GLOBAL PORTS -----
input [0:0] pReset;
//----- GLOBAL PORTS -----
input [0:0] prog_clk;
//----- INPUT PORTS -----
input [0:3] frac_logic_in;
//----- INPUT PORTS -----
input [0:0] frac_logic_cin;
//----- INPUT PORTS -----
input [0:0] ccff_head;
//----- OUTPUT PORTS -----
output [0:1] frac_logic_out;
//----- OUTPUT PORTS -----
output [0:0] frac_logic_cout;
//----- OUTPUT PORTS -----
output [0:0] ccff_tail;
//----- BEGIN wire-connection ports -----
wire [0:3] frac_logic_in;
wire [0:0] frac_logic_cin;
wire [0:1] frac_logic_out;
wire [0:0] frac_logic_cout;
//----- END wire-connection ports -----
//----- BEGIN Registered ports -----
//----- END Registered ports -----
wire [0:0] direct_interc_2_out;
wire [0:0] direct_interc_3_out;
wire [0:0] direct_interc_4_out;
wire [0:0] direct_interc_5_out;
wire [0:0] direct_interc_6_out;
wire [0:0] direct_interc_7_out;
wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__carry_follower_0_carry_follower_cout;
wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_ccff_tail;
wire [0:1] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut2_out;
wire [0:1] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut3_out;
wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut4_out;
wire [0:1] mux_frac_logic_out_0_undriven_sram_inv;
wire [0:1] mux_frac_lut4_0_in_2_undriven_sram_inv;
wire [0:1] mux_tree_size2_0_sram;
wire [0:0] mux_tree_size2_1_out;
wire [0:1] mux_tree_size2_1_sram;
wire [0:0] mux_tree_size2_mem_0_ccff_tail;
// ----- BEGIN Local short connections -----
// ----- END Local short connections -----
// ----- BEGIN Local output short connections -----
// ----- END Local output short connections -----
logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0 (
.pReset(pReset),
.prog_clk(prog_clk),
.frac_lut4_in({direct_interc_2_out, direct_interc_3_out, mux_tree_size2_1_out, direct_interc_4_out}),
.ccff_head(ccff_head),
.frac_lut4_lut2_out(logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut2_out[0:1]),
.frac_lut4_lut3_out(logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut3_out[0:1]),
.frac_lut4_lut4_out(logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut4_out),
.ccff_tail(logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_ccff_tail));
logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__carry_follower logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__carry_follower_0 (
.carry_follower_a(direct_interc_5_out),
.carry_follower_b(direct_interc_6_out),
.carry_follower_cin(direct_interc_7_out),
.carry_follower_cout(logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__carry_follower_0_carry_follower_cout));
mux_tree_size2 mux_frac_logic_out_0 (
.in({logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut4_out, logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut3_out[0]}),
.sram(mux_tree_size2_0_sram[0:1]),
.sram_inv(mux_frac_logic_out_0_undriven_sram_inv[0:1]),
.out(frac_logic_out[0]));
mux_tree_size2 mux_frac_lut4_0_in_2 (
.in({frac_logic_cin, frac_logic_in[2]}),
.sram(mux_tree_size2_1_sram[0:1]),
.sram_inv(mux_frac_lut4_0_in_2_undriven_sram_inv[0:1]),
.out(mux_tree_size2_1_out));
mux_tree_size2_mem mem_frac_logic_out_0 (
.pReset(pReset),
.prog_clk(prog_clk),
.ccff_head(logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_ccff_tail),
.ccff_tail(mux_tree_size2_mem_0_ccff_tail),
.mem_out(mux_tree_size2_0_sram[0:1]));
mux_tree_size2_mem mem_frac_lut4_0_in_2 (
.pReset(pReset),
.prog_clk(prog_clk),
.ccff_head(mux_tree_size2_mem_0_ccff_tail),
.ccff_tail(ccff_tail),
.mem_out(mux_tree_size2_1_sram[0:1]));
direct_interc direct_interc_0_ (
.in(logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut3_out[1]),
.out(frac_logic_out[1]));
direct_interc direct_interc_1_ (
.in(logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__carry_follower_0_carry_follower_cout),
.out(frac_logic_cout));
direct_interc direct_interc_2_ (
.in(frac_logic_in[0]),
.out(direct_interc_2_out));
direct_interc direct_interc_3_ (
.in(frac_logic_in[1]),
.out(direct_interc_3_out));
direct_interc direct_interc_4_ (
.in(frac_logic_in[3]),
.out(direct_interc_4_out));
direct_interc direct_interc_5_ (
.in(logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut2_out[1]),
.out(direct_interc_5_out));
direct_interc direct_interc_6_ (
.in(frac_logic_cin),
.out(direct_interc_6_out));
direct_interc direct_interc_7_ (
.in(logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut2_out[0]),
.out(direct_interc_7_out));
endmodule
// ----- END Verilog module for logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic -----
//----- Default net type -----
`default_nettype none
// ----- END Physical programmable logic block Verilog module: frac_logic -----

59
SOFA_A/SOFA_A_verilog/lb/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__carry_follower.v Normal file
View File

@ -0,0 +1,59 @@
//-------------------------------------------
// FPGA Synthesizable Verilog Netlist
// Description: Verilog modules for primitive pb_type: carry_follower
// Author: Xifan TANG
// Organization: University of Utah
// Date: Sun Feb 19 10:53:27 2023
//-------------------------------------------
//----- Time scale -----
`timescale 1ns / 1ps
//----- Default net type -----
`default_nettype none
// ----- Verilog module for logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__carry_follower -----
module logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__carry_follower(carry_follower_a,
carry_follower_b,
carry_follower_cin,
carry_follower_cout);
//----- INPUT PORTS -----
input [0:0] carry_follower_a;
//----- INPUT PORTS -----
input [0:0] carry_follower_b;
//----- INPUT PORTS -----
input [0:0] carry_follower_cin;
//----- OUTPUT PORTS -----
output [0:0] carry_follower_cout;
//----- BEGIN wire-connection ports -----
wire [0:0] carry_follower_a;
wire [0:0] carry_follower_b;
wire [0:0] carry_follower_cin;
wire [0:0] carry_follower_cout;
//----- END wire-connection ports -----
//----- BEGIN Registered ports -----
//----- END Registered ports -----
// ----- BEGIN Local short connections -----
// ----- END Local short connections -----
// ----- BEGIN Local output short connections -----
// ----- END Local output short connections -----
sky130_fd_sc_hd__mux2_1_wrapper sky130_fd_sc_hd__mux2_1_wrapper_0_ (
.A0(carry_follower_a),
.A1(carry_follower_b),
.S(carry_follower_cin),
.X(carry_follower_cout));
endmodule
// ----- END Verilog module for logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__carry_follower -----
//----- Default net type -----
`default_nettype none

86
SOFA_A/SOFA_A_verilog/lb/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4.v Normal file
View File

@ -0,0 +1,86 @@
//-------------------------------------------
// FPGA Synthesizable Verilog Netlist
// Description: Verilog modules for primitive pb_type: frac_lut4
// Author: Xifan TANG
// Organization: University of Utah
// Date: Sun Feb 19 10:53:27 2023
//-------------------------------------------
//----- Time scale -----
`timescale 1ns / 1ps
//----- Default net type -----
`default_nettype none
// ----- Verilog module for logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4 -----
module logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4(pReset,
prog_clk,
frac_lut4_in,
ccff_head,
frac_lut4_lut2_out,
frac_lut4_lut3_out,
frac_lut4_lut4_out,
ccff_tail);
//----- GLOBAL PORTS -----
input [0:0] pReset;
//----- GLOBAL PORTS -----
input [0:0] prog_clk;
//----- INPUT PORTS -----
input [0:3] frac_lut4_in;
//----- INPUT PORTS -----
input [0:0] ccff_head;
//----- OUTPUT PORTS -----
output [0:1] frac_lut4_lut2_out;
//----- OUTPUT PORTS -----
output [0:1] frac_lut4_lut3_out;
//----- OUTPUT PORTS -----
output [0:0] frac_lut4_lut4_out;
//----- OUTPUT PORTS -----
output [0:0] ccff_tail;
//----- BEGIN wire-connection ports -----
wire [0:3] frac_lut4_in;
wire [0:1] frac_lut4_lut2_out;
wire [0:1] frac_lut4_lut3_out;
wire [0:0] frac_lut4_lut4_out;
//----- END wire-connection ports -----
//----- BEGIN Registered ports -----
//----- END Registered ports -----
wire [0:0] frac_lut4_0__undriven_mode_inv;
wire [0:15] frac_lut4_0__undriven_sram_inv;
wire [0:0] frac_lut4_0_mode;
wire [0:15] frac_lut4_0_sram;
// ----- BEGIN Local short connections -----
// ----- END Local short connections -----
// ----- BEGIN Local output short connections -----
// ----- END Local output short connections -----
frac_lut4 frac_lut4_0_ (
.in(frac_lut4_in[0:3]),
.sram(frac_lut4_0_sram[0:15]),
.sram_inv(frac_lut4_0__undriven_sram_inv[0:15]),
.mode(frac_lut4_0_mode),
.mode_inv(frac_lut4_0__undriven_mode_inv),
.lut2_out(frac_lut4_lut2_out[0:1]),
.lut3_out(frac_lut4_lut3_out[0:1]),
.lut4_out(frac_lut4_lut4_out));
frac_lut4_sky130_fd_sc_hd__dfrtp_1_mem frac_lut4_sky130_fd_sc_hd__dfrtp_1_mem (
.pReset(pReset),
.prog_clk(prog_clk),
.ccff_head(ccff_head),
.ccff_tail(ccff_tail),
.mem_out({frac_lut4_0_sram[0:15], frac_lut4_0_mode}));
endmodule
// ----- END Verilog module for logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4 -----
//----- Default net type -----
`default_nettype none

93
SOFA_A/SOFA_A_verilog/lb/logical_tile_io_mode_io_.v Normal file
View File

@ -0,0 +1,93 @@
//-------------------------------------------
// FPGA Synthesizable Verilog Netlist
// Description: Verilog modules for pb_type: io
// Author: Xifan TANG
// Organization: University of Utah
// Date: Sun Feb 19 10:53:27 2023
//-------------------------------------------
//----- Time scale -----
`timescale 1ns / 1ps
// ----- BEGIN Physical programmable logic block Verilog module: io -----
//----- Default net type -----
`default_nettype none
// ----- Verilog module for logical_tile_io_mode_io_ -----
module logical_tile_io_mode_io_(IO_ISOL_N,
pReset,
prog_clk,
gfpga_pad_EMBEDDED_IO_HD_SOC_IN,
gfpga_pad_EMBEDDED_IO_HD_SOC_OUT,
gfpga_pad_EMBEDDED_IO_HD_SOC_DIR,
io_outpad,
ccff_head,
io_inpad,
ccff_tail);
//----- GLOBAL PORTS -----
input [0:0] IO_ISOL_N;
//----- GLOBAL PORTS -----
input [0:0] pReset;
//----- GLOBAL PORTS -----
input [0:0] prog_clk;
//----- GPIN PORTS -----
input [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_IN;
//----- GPOUT PORTS -----
output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_OUT;
//----- GPOUT PORTS -----
output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_DIR;
//----- INPUT PORTS -----
input [0:0] io_outpad;
//----- INPUT PORTS -----
input [0:0] ccff_head;
//----- OUTPUT PORTS -----
output [0:0] io_inpad;
//----- OUTPUT PORTS -----
output [0:0] ccff_tail;
//----- BEGIN wire-connection ports -----
wire [0:0] io_outpad;
wire [0:0] io_inpad;
//----- END wire-connection ports -----
//----- BEGIN Registered ports -----
//----- END Registered ports -----
wire [0:0] direct_interc_1_out;
wire [0:0] logical_tile_io_mode_physical__iopad_0_iopad_inpad;
// ----- BEGIN Local short connections -----
// ----- END Local short connections -----
// ----- BEGIN Local output short connections -----
// ----- END Local output short connections -----
logical_tile_io_mode_physical__iopad logical_tile_io_mode_physical__iopad_0 (
.IO_ISOL_N(IO_ISOL_N),
.pReset(pReset),
.prog_clk(prog_clk),
.gfpga_pad_EMBEDDED_IO_HD_SOC_IN(gfpga_pad_EMBEDDED_IO_HD_SOC_IN),
.gfpga_pad_EMBEDDED_IO_HD_SOC_OUT(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT),
.gfpga_pad_EMBEDDED_IO_HD_SOC_DIR(gfpga_pad_EMBEDDED_IO_HD_SOC_DIR),
.iopad_outpad(direct_interc_1_out),
.ccff_head(ccff_head),
.iopad_inpad(logical_tile_io_mode_physical__iopad_0_iopad_inpad),
.ccff_tail(ccff_tail));
direct_interc direct_interc_0_ (
.in(logical_tile_io_mode_physical__iopad_0_iopad_inpad),
.out(io_inpad));
direct_interc direct_interc_1_ (
.in(io_outpad),
.out(direct_interc_1_out));
endmodule
// ----- END Verilog module for logical_tile_io_mode_io_ -----
//----- Default net type -----
`default_nettype none
// ----- END Physical programmable logic block Verilog module: io -----

86
SOFA_A/SOFA_A_verilog/lb/logical_tile_io_mode_physical__iopad.v Normal file
View File

@ -0,0 +1,86 @@
//-------------------------------------------
// FPGA Synthesizable Verilog Netlist
// Description: Verilog modules for primitive pb_type: iopad
// Author: Xifan TANG
// Organization: University of Utah
// Date: Sun Feb 19 10:53:27 2023
//-------------------------------------------
//----- Time scale -----
`timescale 1ns / 1ps
//----- Default net type -----
`default_nettype none
// ----- Verilog module for logical_tile_io_mode_physical__iopad -----
module logical_tile_io_mode_physical__iopad(IO_ISOL_N,
pReset,
prog_clk,
gfpga_pad_EMBEDDED_IO_HD_SOC_IN,
gfpga_pad_EMBEDDED_IO_HD_SOC_OUT,
gfpga_pad_EMBEDDED_IO_HD_SOC_DIR,
iopad_outpad,
ccff_head,
iopad_inpad,
ccff_tail);
//----- GLOBAL PORTS -----
input [0:0] IO_ISOL_N;
//----- GLOBAL PORTS -----
input [0:0] pReset;
//----- GLOBAL PORTS -----
input [0:0] prog_clk;
//----- GPIN PORTS -----
input [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_IN;
//----- GPOUT PORTS -----
output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_OUT;
//----- GPOUT PORTS -----
output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_DIR;
//----- INPUT PORTS -----
input [0:0] iopad_outpad;
//----- INPUT PORTS -----
input [0:0] ccff_head;
//----- OUTPUT PORTS -----
output [0:0] iopad_inpad;
//----- OUTPUT PORTS -----
output [0:0] ccff_tail;
//----- BEGIN wire-connection ports -----
wire [0:0] iopad_outpad;
wire [0:0] iopad_inpad;
//----- END wire-connection ports -----
//----- BEGIN Registered ports -----
//----- END Registered ports -----
wire [0:0] EMBEDDED_IO_HD_0_en;
// ----- BEGIN Local short connections -----
// ----- END Local short connections -----
// ----- BEGIN Local output short connections -----
// ----- END Local output short connections -----
EMBEDDED_IO_HD EMBEDDED_IO_HD_0_ (
.IO_ISOL_N(IO_ISOL_N),
.SOC_IN(gfpga_pad_EMBEDDED_IO_HD_SOC_IN),
.SOC_OUT(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT),
.SOC_DIR(gfpga_pad_EMBEDDED_IO_HD_SOC_DIR),
.FPGA_OUT(iopad_outpad),
.FPGA_DIR(EMBEDDED_IO_HD_0_en),
.FPGA_IN(iopad_inpad));
EMBEDDED_IO_HD_sky130_fd_sc_hd__dfrtp_1_mem EMBEDDED_IO_HD_sky130_fd_sc_hd__dfrtp_1_mem (
.pReset(pReset),
.prog_clk(prog_clk),
.ccff_head(ccff_head),
.ccff_tail(ccff_tail),
.mem_out(EMBEDDED_IO_HD_0_en));
endmodule
// ----- END Verilog module for logical_tile_io_mode_physical__iopad -----
//----- Default net type -----
`default_nettype none

320
SOFA_A/SOFA_A_verilog/routing/cbx_1__0_.v Normal file
View File

@ -0,0 +1,320 @@
//-------------------------------------------
// FPGA Synthesizable Verilog Netlist
// Description: Verilog modules for Unique Connection Blocks[1][0]
// Author: Xifan TANG
// Organization: University of Utah
// Date: Sun Feb 19 10:53:27 2023
//-------------------------------------------
//----- Time scale -----
`timescale 1ns / 1ps
//----- Default net type -----
`default_nettype none
// ----- Verilog module for cbx_1__0_ -----
module cbx_1__0_(pReset,
prog_clk,
chanx_left_in,
chanx_right_in,
ccff_head,
chanx_left_out,
chanx_right_out,
bottom_grid_top_width_0_height_0_subtile_0__pin_outpad_0_,
bottom_grid_top_width_0_height_0_subtile_1__pin_outpad_0_,
bottom_grid_top_width_0_height_0_subtile_2__pin_outpad_0_,
bottom_grid_top_width_0_height_0_subtile_3__pin_outpad_0_,
bottom_grid_top_width_0_height_0_subtile_4__pin_outpad_0_,
bottom_grid_top_width_0_height_0_subtile_5__pin_outpad_0_,
bottom_grid_top_width_0_height_0_subtile_6__pin_outpad_0_,
bottom_grid_top_width_0_height_0_subtile_7__pin_outpad_0_,
bottom_grid_top_width_0_height_0_subtile_8__pin_outpad_0_,
ccff_tail);
//----- GLOBAL PORTS -----
input [0:0] pReset;
//----- GLOBAL PORTS -----
input [0:0] prog_clk;
//----- INPUT PORTS -----
input [0:10] chanx_left_in;
//----- INPUT PORTS -----
input [0:10] chanx_right_in;
//----- INPUT PORTS -----
input [0:0] ccff_head;
//----- OUTPUT PORTS -----
output [0:10] chanx_left_out;
//----- OUTPUT PORTS -----
output [0:10] chanx_right_out;
//----- OUTPUT PORTS -----
output [0:0] bottom_grid_top_width_0_height_0_subtile_0__pin_outpad_0_;
//----- OUTPUT PORTS -----
output [0:0] bottom_grid_top_width_0_height_0_subtile_1__pin_outpad_0_;
//----- OUTPUT PORTS -----
output [0:0] bottom_grid_top_width_0_height_0_subtile_2__pin_outpad_0_;
//----- OUTPUT PORTS -----
output [0:0] bottom_grid_top_width_0_height_0_subtile_3__pin_outpad_0_;
//----- OUTPUT PORTS -----
output [0:0] bottom_grid_top_width_0_height_0_subtile_4__pin_outpad_0_;
//----- OUTPUT PORTS -----
output [0:0] bottom_grid_top_width_0_height_0_subtile_5__pin_outpad_0_;
//----- OUTPUT PORTS -----
output [0:0] bottom_grid_top_width_0_height_0_subtile_6__pin_outpad_0_;
//----- OUTPUT PORTS -----
output [0:0] bottom_grid_top_width_0_height_0_subtile_7__pin_outpad_0_;
//----- OUTPUT PORTS -----
output [0:0] bottom_grid_top_width_0_height_0_subtile_8__pin_outpad_0_;
//----- OUTPUT PORTS -----
output [0:0] ccff_tail;
//----- BEGIN wire-connection ports -----
//----- END wire-connection ports -----
//----- BEGIN Registered ports -----
//----- END Registered ports -----
wire [0:3] mux_top_ipin_0_undriven_sram_inv;
wire [0:3] mux_top_ipin_1_undriven_sram_inv;
wire [0:3] mux_top_ipin_2_undriven_sram_inv;
wire [0:3] mux_top_ipin_3_undriven_sram_inv;
wire [0:3] mux_top_ipin_4_undriven_sram_inv;
wire [0:3] mux_top_ipin_5_undriven_sram_inv;
wire [0:3] mux_top_ipin_6_undriven_sram_inv;
wire [0:3] mux_top_ipin_7_undriven_sram_inv;
wire [0:3] mux_top_ipin_8_undriven_sram_inv;
wire [0:3] mux_tree_tapbuf_size10_0_sram;
wire [0:3] mux_tree_tapbuf_size10_1_sram;
wire [0:3] mux_tree_tapbuf_size10_2_sram;
wire [0:3] mux_tree_tapbuf_size10_3_sram;
wire [0:3] mux_tree_tapbuf_size10_4_sram;
wire [0:3] mux_tree_tapbuf_size10_5_sram;
wire [0:3] mux_tree_tapbuf_size10_6_sram;
wire [0:3] mux_tree_tapbuf_size10_7_sram;
wire [0:3] mux_tree_tapbuf_size10_8_sram;
wire [0:0] mux_tree_tapbuf_size10_mem_0_ccff_tail;
wire [0:0] mux_tree_tapbuf_size10_mem_1_ccff_tail;
wire [0:0] mux_tree_tapbuf_size10_mem_2_ccff_tail;
wire [0:0] mux_tree_tapbuf_size10_mem_3_ccff_tail;
wire [0:0] mux_tree_tapbuf_size10_mem_4_ccff_tail;
wire [0:0] mux_tree_tapbuf_size10_mem_5_ccff_tail;
wire [0:0] mux_tree_tapbuf_size10_mem_6_ccff_tail;
wire [0:0] mux_tree_tapbuf_size10_mem_7_ccff_tail;
// ----- BEGIN Local short connections -----
// ----- Local connection due to Wire 0 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chanx_right_out[0] = chanx_left_in[0];
// ----- Local connection due to Wire 1 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chanx_right_out[1] = chanx_left_in[1];
// ----- Local connection due to Wire 2 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chanx_right_out[2] = chanx_left_in[2];
// ----- Local connection due to Wire 3 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chanx_right_out[3] = chanx_left_in[3];
// ----- Local connection due to Wire 4 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chanx_right_out[4] = chanx_left_in[4];
// ----- Local connection due to Wire 5 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chanx_right_out[5] = chanx_left_in[5];
// ----- Local connection due to Wire 6 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chanx_right_out[6] = chanx_left_in[6];
// ----- Local connection due to Wire 7 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chanx_right_out[7] = chanx_left_in[7];
// ----- Local connection due to Wire 8 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chanx_right_out[8] = chanx_left_in[8];
// ----- Local connection due to Wire 9 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chanx_right_out[9] = chanx_left_in[9];
// ----- Local connection due to Wire 10 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chanx_right_out[10] = chanx_left_in[10];
// ----- Local connection due to Wire 11 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chanx_left_out[0] = chanx_right_in[0];
// ----- Local connection due to Wire 12 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chanx_left_out[1] = chanx_right_in[1];
// ----- Local connection due to Wire 13 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chanx_left_out[2] = chanx_right_in[2];
// ----- Local connection due to Wire 14 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chanx_left_out[3] = chanx_right_in[3];
// ----- Local connection due to Wire 15 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chanx_left_out[4] = chanx_right_in[4];
// ----- Local connection due to Wire 16 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chanx_left_out[5] = chanx_right_in[5];
// ----- Local connection due to Wire 17 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chanx_left_out[6] = chanx_right_in[6];
// ----- Local connection due to Wire 18 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chanx_left_out[7] = chanx_right_in[7];
// ----- Local connection due to Wire 19 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chanx_left_out[8] = chanx_right_in[8];
// ----- Local connection due to Wire 20 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chanx_left_out[9] = chanx_right_in[9];
// ----- Local connection due to Wire 21 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chanx_left_out[10] = chanx_right_in[10];
// ----- END Local short connections -----
// ----- BEGIN Local output short connections -----
// ----- END Local output short connections -----
mux_tree_tapbuf_size10 mux_top_ipin_0 (
.in({chanx_left_in[0], chanx_right_in[0], chanx_left_in[1], chanx_right_in[1], chanx_left_in[2], chanx_right_in[2], chanx_left_in[6], chanx_right_in[6], chanx_left_in[10], chanx_right_in[10]}),
.sram(mux_tree_tapbuf_size10_0_sram[0:3]),
.sram_inv(mux_top_ipin_0_undriven_sram_inv[0:3]),
.out(bottom_grid_top_width_0_height_0_subtile_0__pin_outpad_0_));
mux_tree_tapbuf_size10 mux_top_ipin_1 (
.in({chanx_left_in[0], chanx_right_in[0], chanx_left_in[1], chanx_right_in[1], chanx_left_in[2], chanx_right_in[2], chanx_left_in[3], chanx_right_in[3], chanx_left_in[7], chanx_right_in[7]}),
.sram(mux_tree_tapbuf_size10_1_sram[0:3]),
.sram_inv(mux_top_ipin_1_undriven_sram_inv[0:3]),
.out(bottom_grid_top_width_0_height_0_subtile_1__pin_outpad_0_));
mux_tree_tapbuf_size10 mux_top_ipin_2 (
.in({chanx_left_in[0], chanx_right_in[0], chanx_left_in[1], chanx_right_in[1], chanx_left_in[3], chanx_right_in[3], chanx_left_in[4], chanx_right_in[4], chanx_left_in[8], chanx_right_in[8]}),
.sram(mux_tree_tapbuf_size10_2_sram[0:3]),
.sram_inv(mux_top_ipin_2_undriven_sram_inv[0:3]),
.out(bottom_grid_top_width_0_height_0_subtile_2__pin_outpad_0_));
mux_tree_tapbuf_size10 mux_top_ipin_3 (
.in({chanx_left_in[0], chanx_right_in[0], chanx_left_in[1], chanx_right_in[1], chanx_left_in[4], chanx_right_in[4], chanx_left_in[5], chanx_right_in[5], chanx_left_in[9], chanx_right_in[9]}),
.sram(mux_tree_tapbuf_size10_3_sram[0:3]),
.sram_inv(mux_top_ipin_3_undriven_sram_inv[0:3]),
.out(bottom_grid_top_width_0_height_0_subtile_3__pin_outpad_0_));
mux_tree_tapbuf_size10 mux_top_ipin_4 (
.in({chanx_left_in[0], chanx_right_in[0], chanx_left_in[1], chanx_right_in[1], chanx_left_in[5], chanx_right_in[5], chanx_left_in[6], chanx_right_in[6], chanx_left_in[10], chanx_right_in[10]}),
.sram(mux_tree_tapbuf_size10_4_sram[0:3]),
.sram_inv(mux_top_ipin_4_undriven_sram_inv[0:3]),
.out(bottom_grid_top_width_0_height_0_subtile_4__pin_outpad_0_));
mux_tree_tapbuf_size10 mux_top_ipin_5 (
.in({chanx_left_in[0], chanx_right_in[0], chanx_left_in[1], chanx_right_in[1], chanx_left_in[2], chanx_right_in[2], chanx_left_in[6], chanx_right_in[6], chanx_left_in[7], chanx_right_in[7]}),
.sram(mux_tree_tapbuf_size10_5_sram[0:3]),
.sram_inv(mux_top_ipin_5_undriven_sram_inv[0:3]),
.out(bottom_grid_top_width_0_height_0_subtile_5__pin_outpad_0_));
mux_tree_tapbuf_size10 mux_top_ipin_6 (
.in({chanx_left_in[0], chanx_right_in[0], chanx_left_in[1], chanx_right_in[1], chanx_left_in[3], chanx_right_in[3], chanx_left_in[7], chanx_right_in[7], chanx_left_in[8], chanx_right_in[8]}),
.sram(mux_tree_tapbuf_size10_6_sram[0:3]),
.sram_inv(mux_top_ipin_6_undriven_sram_inv[0:3]),
.out(bottom_grid_top_width_0_height_0_subtile_6__pin_outpad_0_));
mux_tree_tapbuf_size10 mux_top_ipin_7 (
.in({chanx_left_in[0], chanx_right_in[0], chanx_left_in[1], chanx_right_in[1], chanx_left_in[4], chanx_right_in[4], chanx_left_in[8], chanx_right_in[8], chanx_left_in[9], chanx_right_in[9]}),
.sram(mux_tree_tapbuf_size10_7_sram[0:3]),
.sram_inv(mux_top_ipin_7_undriven_sram_inv[0:3]),
.out(bottom_grid_top_width_0_height_0_subtile_7__pin_outpad_0_));
mux_tree_tapbuf_size10 mux_top_ipin_8 (
.in({chanx_left_in[0], chanx_right_in[0], chanx_left_in[1], chanx_right_in[1], chanx_left_in[5], chanx_right_in[5], chanx_left_in[9], chanx_right_in[9], chanx_left_in[10], chanx_right_in[10]}),
.sram(mux_tree_tapbuf_size10_8_sram[0:3]),
.sram_inv(mux_top_ipin_8_undriven_sram_inv[0:3]),
.out(bottom_grid_top_width_0_height_0_subtile_8__pin_outpad_0_));
mux_tree_tapbuf_size10_mem mem_top_ipin_0 (
.pReset(pReset),
.prog_clk(prog_clk),
.ccff_head(ccff_head),
.ccff_tail(mux_tree_tapbuf_size10_mem_0_ccff_tail),
.mem_out(mux_tree_tapbuf_size10_0_sram[0:3]));
mux_tree_tapbuf_size10_mem mem_top_ipin_1 (
.pReset(pReset),
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size10_mem_0_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size10_mem_1_ccff_tail),
.mem_out(mux_tree_tapbuf_size10_1_sram[0:3]));
mux_tree_tapbuf_size10_mem mem_top_ipin_2 (
.pReset(pReset),
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size10_mem_1_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size10_mem_2_ccff_tail),
.mem_out(mux_tree_tapbuf_size10_2_sram[0:3]));
mux_tree_tapbuf_size10_mem mem_top_ipin_3 (
.pReset(pReset),
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size10_mem_2_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size10_mem_3_ccff_tail),
.mem_out(mux_tree_tapbuf_size10_3_sram[0:3]));
mux_tree_tapbuf_size10_mem mem_top_ipin_4 (
.pReset(pReset),
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size10_mem_3_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size10_mem_4_ccff_tail),
.mem_out(mux_tree_tapbuf_size10_4_sram[0:3]));
mux_tree_tapbuf_size10_mem mem_top_ipin_5 (
.pReset(pReset),
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size10_mem_4_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size10_mem_5_ccff_tail),
.mem_out(mux_tree_tapbuf_size10_5_sram[0:3]));
mux_tree_tapbuf_size10_mem mem_top_ipin_6 (
.pReset(pReset),
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size10_mem_5_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size10_mem_6_ccff_tail),
.mem_out(mux_tree_tapbuf_size10_6_sram[0:3]));
mux_tree_tapbuf_size10_mem mem_top_ipin_7 (
.pReset(pReset),
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size10_mem_6_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size10_mem_7_ccff_tail),
.mem_out(mux_tree_tapbuf_size10_7_sram[0:3]));
mux_tree_tapbuf_size10_mem mem_top_ipin_8 (
.pReset(pReset),
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size10_mem_7_ccff_tail),
.ccff_tail(ccff_tail),
.mem_out(mux_tree_tapbuf_size10_8_sram[0:3]));
endmodule
// ----- END Verilog module for cbx_1__0_ -----
//----- Default net type -----
`default_nettype none

605
SOFA_A/SOFA_A_verilog/routing/cbx_1__1_.v Normal file
View File

@ -0,0 +1,605 @@
//-------------------------------------------
// FPGA Synthesizable Verilog Netlist
// Description: Verilog modules for Unique Connection Blocks[1][1]
// Author: Xifan TANG
// Organization: University of Utah
// Date: Sun Feb 19 10:53:27 2023
//-------------------------------------------
//----- Time scale -----
`timescale 1ns / 1ps
//----- Default net type -----
`default_nettype none
// ----- Verilog module for cbx_1__1_ -----
module cbx_1__1_(pReset,
prog_clk,
chanx_left_in,
chanx_right_in,
ccff_head,
chanx_left_out,
chanx_right_out,
top_grid_bottom_width_0_height_0_subtile_0__pin_outpad_0_,
top_grid_bottom_width_0_height_0_subtile_1__pin_outpad_0_,
top_grid_bottom_width_0_height_0_subtile_2__pin_outpad_0_,
top_grid_bottom_width_0_height_0_subtile_3__pin_outpad_0_,
top_grid_bottom_width_0_height_0_subtile_4__pin_outpad_0_,
top_grid_bottom_width_0_height_0_subtile_5__pin_outpad_0_,
top_grid_bottom_width_0_height_0_subtile_6__pin_outpad_0_,
top_grid_bottom_width_0_height_0_subtile_7__pin_outpad_0_,
bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_,
bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_,
bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_,
bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_,
bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_,
bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_,
bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_,
bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_,
bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_,
bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_,
bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_,
bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_,
bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_,
bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_,
bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_,
bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_,
ccff_tail);
//----- GLOBAL PORTS -----
input [0:0] pReset;
//----- GLOBAL PORTS -----
input [0:0] prog_clk;
//----- INPUT PORTS -----
input [0:10] chanx_left_in;
//----- INPUT PORTS -----
input [0:10] chanx_right_in;
//----- INPUT PORTS -----
input [0:0] ccff_head;
//----- OUTPUT PORTS -----
output [0:10] chanx_left_out;
//----- OUTPUT PORTS -----
output [0:10] chanx_right_out;
//----- OUTPUT PORTS -----
output [0:0] top_grid_bottom_width_0_height_0_subtile_0__pin_outpad_0_;
//----- OUTPUT PORTS -----
output [0:0] top_grid_bottom_width_0_height_0_subtile_1__pin_outpad_0_;
//----- OUTPUT PORTS -----
output [0:0] top_grid_bottom_width_0_height_0_subtile_2__pin_outpad_0_;
//----- OUTPUT PORTS -----
output [0:0] top_grid_bottom_width_0_height_0_subtile_3__pin_outpad_0_;
//----- OUTPUT PORTS -----
output [0:0] top_grid_bottom_width_0_height_0_subtile_4__pin_outpad_0_;
//----- OUTPUT PORTS -----
output [0:0] top_grid_bottom_width_0_height_0_subtile_5__pin_outpad_0_;
//----- OUTPUT PORTS -----
output [0:0] top_grid_bottom_width_0_height_0_subtile_6__pin_outpad_0_;
//----- OUTPUT PORTS -----
output [0:0] top_grid_bottom_width_0_height_0_subtile_7__pin_outpad_0_;
//----- OUTPUT PORTS -----
output [0:0] bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_;
//----- OUTPUT PORTS -----
output [0:0] bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_;
//----- OUTPUT PORTS -----
output [0:0] bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_;
//----- OUTPUT PORTS -----
output [0:0] bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_;
//----- OUTPUT PORTS -----
output [0:0] bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_;
//----- OUTPUT PORTS -----
output [0:0] bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_;
//----- OUTPUT PORTS -----
output [0:0] bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_;
//----- OUTPUT PORTS -----
output [0:0] bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_;
//----- OUTPUT PORTS -----
output [0:0] bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_;
//----- OUTPUT PORTS -----
output [0:0] bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_;
//----- OUTPUT PORTS -----
output [0:0] bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_;
//----- OUTPUT PORTS -----
output [0:0] bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_;
//----- OUTPUT PORTS -----
output [0:0] bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_;
//----- OUTPUT PORTS -----
output [0:0] bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_;
//----- OUTPUT PORTS -----
output [0:0] bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_;
//----- OUTPUT PORTS -----
output [0:0] bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_;
//----- OUTPUT PORTS -----
output [0:0] ccff_tail;
//----- BEGIN wire-connection ports -----
//----- END wire-connection ports -----
//----- BEGIN Registered ports -----
//----- END Registered ports -----
wire [0:3] mux_bottom_ipin_0_undriven_sram_inv;
wire [0:3] mux_bottom_ipin_1_undriven_sram_inv;
wire [0:3] mux_bottom_ipin_2_undriven_sram_inv;
wire [0:3] mux_bottom_ipin_3_undriven_sram_inv;
wire [0:3] mux_bottom_ipin_4_undriven_sram_inv;
wire [0:3] mux_bottom_ipin_5_undriven_sram_inv;
wire [0:3] mux_bottom_ipin_6_undriven_sram_inv;
wire [0:3] mux_bottom_ipin_7_undriven_sram_inv;
wire [0:3] mux_top_ipin_0_undriven_sram_inv;
wire [0:3] mux_top_ipin_10_undriven_sram_inv;
wire [0:2] mux_top_ipin_11_undriven_sram_inv;
wire [0:3] mux_top_ipin_12_undriven_sram_inv;
wire [0:2] mux_top_ipin_13_undriven_sram_inv;
wire [0:3] mux_top_ipin_14_undriven_sram_inv;
wire [0:2] mux_top_ipin_15_undriven_sram_inv;
wire [0:2] mux_top_ipin_1_undriven_sram_inv;
wire [0:3] mux_top_ipin_2_undriven_sram_inv;
wire [0:2] mux_top_ipin_3_undriven_sram_inv;
wire [0:3] mux_top_ipin_4_undriven_sram_inv;
wire [0:2] mux_top_ipin_5_undriven_sram_inv;
wire [0:3] mux_top_ipin_6_undriven_sram_inv;
wire [0:2] mux_top_ipin_7_undriven_sram_inv;
wire [0:3] mux_top_ipin_8_undriven_sram_inv;
wire [0:2] mux_top_ipin_9_undriven_sram_inv;
wire [0:3] mux_tree_tapbuf_size10_0_sram;
wire [0:3] mux_tree_tapbuf_size10_10_sram;
wire [0:3] mux_tree_tapbuf_size10_11_sram;
wire [0:3] mux_tree_tapbuf_size10_12_sram;
wire [0:3] mux_tree_tapbuf_size10_13_sram;
wire [0:3] mux_tree_tapbuf_size10_14_sram;
wire [0:3] mux_tree_tapbuf_size10_15_sram;
wire [0:3] mux_tree_tapbuf_size10_1_sram;
wire [0:3] mux_tree_tapbuf_size10_2_sram;
wire [0:3] mux_tree_tapbuf_size10_3_sram;
wire [0:3] mux_tree_tapbuf_size10_4_sram;
wire [0:3] mux_tree_tapbuf_size10_5_sram;
wire [0:3] mux_tree_tapbuf_size10_6_sram;
wire [0:3] mux_tree_tapbuf_size10_7_sram;
wire [0:3] mux_tree_tapbuf_size10_8_sram;
wire [0:3] mux_tree_tapbuf_size10_9_sram;
wire [0:0] mux_tree_tapbuf_size10_mem_0_ccff_tail;
wire [0:0] mux_tree_tapbuf_size10_mem_10_ccff_tail;
wire [0:0] mux_tree_tapbuf_size10_mem_11_ccff_tail;
wire [0:0] mux_tree_tapbuf_size10_mem_12_ccff_tail;
wire [0:0] mux_tree_tapbuf_size10_mem_13_ccff_tail;
wire [0:0] mux_tree_tapbuf_size10_mem_14_ccff_tail;
wire [0:0] mux_tree_tapbuf_size10_mem_15_ccff_tail;
wire [0:0] mux_tree_tapbuf_size10_mem_1_ccff_tail;
wire [0:0] mux_tree_tapbuf_size10_mem_2_ccff_tail;
wire [0:0] mux_tree_tapbuf_size10_mem_3_ccff_tail;
wire [0:0] mux_tree_tapbuf_size10_mem_4_ccff_tail;
wire [0:0] mux_tree_tapbuf_size10_mem_5_ccff_tail;
wire [0:0] mux_tree_tapbuf_size10_mem_6_ccff_tail;
wire [0:0] mux_tree_tapbuf_size10_mem_7_ccff_tail;
wire [0:0] mux_tree_tapbuf_size10_mem_8_ccff_tail;
wire [0:0] mux_tree_tapbuf_size10_mem_9_ccff_tail;
wire [0:2] mux_tree_tapbuf_size6_0_sram;
wire [0:2] mux_tree_tapbuf_size6_1_sram;
wire [0:2] mux_tree_tapbuf_size6_2_sram;
wire [0:2] mux_tree_tapbuf_size6_3_sram;
wire [0:2] mux_tree_tapbuf_size6_4_sram;
wire [0:2] mux_tree_tapbuf_size6_5_sram;
wire [0:2] mux_tree_tapbuf_size6_6_sram;
wire [0:2] mux_tree_tapbuf_size6_7_sram;
wire [0:0] mux_tree_tapbuf_size6_mem_0_ccff_tail;
wire [0:0] mux_tree_tapbuf_size6_mem_1_ccff_tail;
wire [0:0] mux_tree_tapbuf_size6_mem_2_ccff_tail;
wire [0:0] mux_tree_tapbuf_size6_mem_3_ccff_tail;
wire [0:0] mux_tree_tapbuf_size6_mem_4_ccff_tail;
wire [0:0] mux_tree_tapbuf_size6_mem_5_ccff_tail;
wire [0:0] mux_tree_tapbuf_size6_mem_6_ccff_tail;
// ----- BEGIN Local short connections -----
// ----- Local connection due to Wire 0 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chanx_right_out[0] = chanx_left_in[0];
// ----- Local connection due to Wire 1 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chanx_right_out[1] = chanx_left_in[1];
// ----- Local connection due to Wire 2 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chanx_right_out[2] = chanx_left_in[2];
// ----- Local connection due to Wire 3 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chanx_right_out[3] = chanx_left_in[3];
// ----- Local connection due to Wire 4 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chanx_right_out[4] = chanx_left_in[4];
// ----- Local connection due to Wire 5 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chanx_right_out[5] = chanx_left_in[5];
// ----- Local connection due to Wire 6 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chanx_right_out[6] = chanx_left_in[6];
// ----- Local connection due to Wire 7 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chanx_right_out[7] = chanx_left_in[7];
// ----- Local connection due to Wire 8 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chanx_right_out[8] = chanx_left_in[8];
// ----- Local connection due to Wire 9 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chanx_right_out[9] = chanx_left_in[9];
// ----- Local connection due to Wire 10 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chanx_right_out[10] = chanx_left_in[10];
// ----- Local connection due to Wire 11 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chanx_left_out[0] = chanx_right_in[0];
// ----- Local connection due to Wire 12 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chanx_left_out[1] = chanx_right_in[1];
// ----- Local connection due to Wire 13 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chanx_left_out[2] = chanx_right_in[2];
// ----- Local connection due to Wire 14 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chanx_left_out[3] = chanx_right_in[3];
// ----- Local connection due to Wire 15 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chanx_left_out[4] = chanx_right_in[4];
// ----- Local connection due to Wire 16 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chanx_left_out[5] = chanx_right_in[5];
// ----- Local connection due to Wire 17 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chanx_left_out[6] = chanx_right_in[6];
// ----- Local connection due to Wire 18 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chanx_left_out[7] = chanx_right_in[7];
// ----- Local connection due to Wire 19 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chanx_left_out[8] = chanx_right_in[8];
// ----- Local connection due to Wire 20 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chanx_left_out[9] = chanx_right_in[9];
// ----- Local connection due to Wire 21 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chanx_left_out[10] = chanx_right_in[10];
// ----- END Local short connections -----
// ----- BEGIN Local output short connections -----
// ----- END Local output short connections -----
mux_tree_tapbuf_size10 mux_bottom_ipin_0 (
.in({chanx_left_in[0], chanx_right_in[0], chanx_left_in[1], chanx_right_in[1], chanx_left_in[2], chanx_right_in[2], chanx_left_in[6], chanx_right_in[6], chanx_left_in[10], chanx_right_in[10]}),
.sram(mux_tree_tapbuf_size10_0_sram[0:3]),
.sram_inv(mux_bottom_ipin_0_undriven_sram_inv[0:3]),
.out(top_grid_bottom_width_0_height_0_subtile_0__pin_outpad_0_));
mux_tree_tapbuf_size10 mux_bottom_ipin_1 (
.in({chanx_left_in[0], chanx_right_in[0], chanx_left_in[1], chanx_right_in[1], chanx_left_in[2], chanx_right_in[2], chanx_left_in[3], chanx_right_in[3], chanx_left_in[7], chanx_right_in[7]}),
.sram(mux_tree_tapbuf_size10_1_sram[0:3]),
.sram_inv(mux_bottom_ipin_1_undriven_sram_inv[0:3]),
.out(top_grid_bottom_width_0_height_0_subtile_1__pin_outpad_0_));
mux_tree_tapbuf_size10 mux_bottom_ipin_2 (
.in({chanx_left_in[0], chanx_right_in[0], chanx_left_in[1], chanx_right_in[1], chanx_left_in[3], chanx_right_in[3], chanx_left_in[4], chanx_right_in[4], chanx_left_in[8], chanx_right_in[8]}),
.sram(mux_tree_tapbuf_size10_2_sram[0:3]),
.sram_inv(mux_bottom_ipin_2_undriven_sram_inv[0:3]),
.out(top_grid_bottom_width_0_height_0_subtile_2__pin_outpad_0_));
mux_tree_tapbuf_size10 mux_bottom_ipin_3 (
.in({chanx_left_in[0], chanx_right_in[0], chanx_left_in[1], chanx_right_in[1], chanx_left_in[4], chanx_right_in[4], chanx_left_in[5], chanx_right_in[5], chanx_left_in[9], chanx_right_in[9]}),
.sram(mux_tree_tapbuf_size10_3_sram[0:3]),
.sram_inv(mux_bottom_ipin_3_undriven_sram_inv[0:3]),
.out(top_grid_bottom_width_0_height_0_subtile_3__pin_outpad_0_));
mux_tree_tapbuf_size10 mux_bottom_ipin_4 (
.in({chanx_left_in[0], chanx_right_in[0], chanx_left_in[1], chanx_right_in[1], chanx_left_in[5], chanx_right_in[5], chanx_left_in[6], chanx_right_in[6], chanx_left_in[10], chanx_right_in[10]}),
.sram(mux_tree_tapbuf_size10_4_sram[0:3]),
.sram_inv(mux_bottom_ipin_4_undriven_sram_inv[0:3]),
.out(top_grid_bottom_width_0_height_0_subtile_4__pin_outpad_0_));
mux_tree_tapbuf_size10 mux_bottom_ipin_5 (
.in({chanx_left_in[0], chanx_right_in[0], chanx_left_in[1], chanx_right_in[1], chanx_left_in[2], chanx_right_in[2], chanx_left_in[6], chanx_right_in[6], chanx_left_in[7], chanx_right_in[7]}),
.sram(mux_tree_tapbuf_size10_5_sram[0:3]),
.sram_inv(mux_bottom_ipin_5_undriven_sram_inv[0:3]),
.out(top_grid_bottom_width_0_height_0_subtile_5__pin_outpad_0_));
mux_tree_tapbuf_size10 mux_bottom_ipin_6 (
.in({chanx_left_in[0], chanx_right_in[0], chanx_left_in[1], chanx_right_in[1], chanx_left_in[3], chanx_right_in[3], chanx_left_in[7], chanx_right_in[7], chanx_left_in[8], chanx_right_in[8]}),
.sram(mux_tree_tapbuf_size10_6_sram[0:3]),
.sram_inv(mux_bottom_ipin_6_undriven_sram_inv[0:3]),
.out(top_grid_bottom_width_0_height_0_subtile_6__pin_outpad_0_));
mux_tree_tapbuf_size10 mux_bottom_ipin_7 (
.in({chanx_left_in[0], chanx_right_in[0], chanx_left_in[1], chanx_right_in[1], chanx_left_in[4], chanx_right_in[4], chanx_left_in[8], chanx_right_in[8], chanx_left_in[9], chanx_right_in[9]}),
.sram(mux_tree_tapbuf_size10_7_sram[0:3]),
.sram_inv(mux_bottom_ipin_7_undriven_sram_inv[0:3]),
.out(top_grid_bottom_width_0_height_0_subtile_7__pin_outpad_0_));
mux_tree_tapbuf_size10 mux_top_ipin_0 (
.in({chanx_left_in[0], chanx_right_in[0], chanx_left_in[1], chanx_right_in[1], chanx_left_in[5], chanx_right_in[5], chanx_left_in[9], chanx_right_in[9], chanx_left_in[10], chanx_right_in[10]}),
.sram(mux_tree_tapbuf_size10_8_sram[0:3]),
.sram_inv(mux_top_ipin_0_undriven_sram_inv[0:3]),
.out(bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_));
mux_tree_tapbuf_size10 mux_top_ipin_2 (
.in({chanx_left_in[0], chanx_right_in[0], chanx_left_in[1], chanx_right_in[1], chanx_left_in[2], chanx_right_in[2], chanx_left_in[3], chanx_right_in[3], chanx_left_in[7], chanx_right_in[7]}),
.sram(mux_tree_tapbuf_size10_9_sram[0:3]),
.sram_inv(mux_top_ipin_2_undriven_sram_inv[0:3]),
.out(bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_));
mux_tree_tapbuf_size10 mux_top_ipin_4 (
.in({chanx_left_in[0], chanx_right_in[0], chanx_left_in[1], chanx_right_in[1], chanx_left_in[4], chanx_right_in[4], chanx_left_in[5], chanx_right_in[5], chanx_left_in[9], chanx_right_in[9]}),
.sram(mux_tree_tapbuf_size10_10_sram[0:3]),
.sram_inv(mux_top_ipin_4_undriven_sram_inv[0:3]),
.out(bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_));
mux_tree_tapbuf_size10 mux_top_ipin_6 (
.in({chanx_left_in[0], chanx_right_in[0], chanx_left_in[1], chanx_right_in[1], chanx_left_in[2], chanx_right_in[2], chanx_left_in[6], chanx_right_in[6], chanx_left_in[7], chanx_right_in[7]}),
.sram(mux_tree_tapbuf_size10_11_sram[0:3]),
.sram_inv(mux_top_ipin_6_undriven_sram_inv[0:3]),
.out(bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_));
mux_tree_tapbuf_size10 mux_top_ipin_8 (
.in({chanx_left_in[0], chanx_right_in[0], chanx_left_in[1], chanx_right_in[1], chanx_left_in[4], chanx_right_in[4], chanx_left_in[8], chanx_right_in[8], chanx_left_in[9], chanx_right_in[9]}),
.sram(mux_tree_tapbuf_size10_12_sram[0:3]),
.sram_inv(mux_top_ipin_8_undriven_sram_inv[0:3]),
.out(bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_));
mux_tree_tapbuf_size10 mux_top_ipin_10 (
.in({chanx_left_in[0], chanx_right_in[0], chanx_left_in[1], chanx_right_in[1], chanx_left_in[2], chanx_right_in[2], chanx_left_in[6], chanx_right_in[6], chanx_left_in[10], chanx_right_in[10]}),
.sram(mux_tree_tapbuf_size10_13_sram[0:3]),
.sram_inv(mux_top_ipin_10_undriven_sram_inv[0:3]),
.out(bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_));
mux_tree_tapbuf_size10 mux_top_ipin_12 (
.in({chanx_left_in[0], chanx_right_in[0], chanx_left_in[1], chanx_right_in[1], chanx_left_in[3], chanx_right_in[3], chanx_left_in[4], chanx_right_in[4], chanx_left_in[8], chanx_right_in[8]}),
.sram(mux_tree_tapbuf_size10_14_sram[0:3]),
.sram_inv(mux_top_ipin_12_undriven_sram_inv[0:3]),
.out(bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_));
mux_tree_tapbuf_size10 mux_top_ipin_14 (
.in({chanx_left_in[0], chanx_right_in[0], chanx_left_in[1], chanx_right_in[1], chanx_left_in[5], chanx_right_in[5], chanx_left_in[6], chanx_right_in[6], chanx_left_in[10], chanx_right_in[10]}),
.sram(mux_tree_tapbuf_size10_15_sram[0:3]),
.sram_inv(mux_top_ipin_14_undriven_sram_inv[0:3]),
.out(bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_));
mux_tree_tapbuf_size10_mem mem_bottom_ipin_0 (
.pReset(pReset),
.prog_clk(prog_clk),
.ccff_head(ccff_head),
.ccff_tail(mux_tree_tapbuf_size10_mem_0_ccff_tail),
.mem_out(mux_tree_tapbuf_size10_0_sram[0:3]));
mux_tree_tapbuf_size10_mem mem_bottom_ipin_1 (
.pReset(pReset),
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size10_mem_0_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size10_mem_1_ccff_tail),
.mem_out(mux_tree_tapbuf_size10_1_sram[0:3]));
mux_tree_tapbuf_size10_mem mem_bottom_ipin_2 (
.pReset(pReset),
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size10_mem_1_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size10_mem_2_ccff_tail),
.mem_out(mux_tree_tapbuf_size10_2_sram[0:3]));
mux_tree_tapbuf_size10_mem mem_bottom_ipin_3 (
.pReset(pReset),
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size10_mem_2_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size10_mem_3_ccff_tail),
.mem_out(mux_tree_tapbuf_size10_3_sram[0:3]));
mux_tree_tapbuf_size10_mem mem_bottom_ipin_4 (
.pReset(pReset),
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size10_mem_3_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size10_mem_4_ccff_tail),
.mem_out(mux_tree_tapbuf_size10_4_sram[0:3]));
mux_tree_tapbuf_size10_mem mem_bottom_ipin_5 (
.pReset(pReset),
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size10_mem_4_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size10_mem_5_ccff_tail),
.mem_out(mux_tree_tapbuf_size10_5_sram[0:3]));
mux_tree_tapbuf_size10_mem mem_bottom_ipin_6 (
.pReset(pReset),
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size10_mem_5_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size10_mem_6_ccff_tail),
.mem_out(mux_tree_tapbuf_size10_6_sram[0:3]));
mux_tree_tapbuf_size10_mem mem_bottom_ipin_7 (
.pReset(pReset),
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size10_mem_6_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size10_mem_7_ccff_tail),
.mem_out(mux_tree_tapbuf_size10_7_sram[0:3]));
mux_tree_tapbuf_size10_mem mem_top_ipin_0 (
.pReset(pReset),
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size10_mem_7_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size10_mem_8_ccff_tail),
.mem_out(mux_tree_tapbuf_size10_8_sram[0:3]));
mux_tree_tapbuf_size10_mem mem_top_ipin_2 (
.pReset(pReset),
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size6_mem_0_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size10_mem_9_ccff_tail),
.mem_out(mux_tree_tapbuf_size10_9_sram[0:3]));
mux_tree_tapbuf_size10_mem mem_top_ipin_4 (
.pReset(pReset),
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size6_mem_1_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size10_mem_10_ccff_tail),
.mem_out(mux_tree_tapbuf_size10_10_sram[0:3]));
mux_tree_tapbuf_size10_mem mem_top_ipin_6 (
.pReset(pReset),
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size6_mem_2_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size10_mem_11_ccff_tail),
.mem_out(mux_tree_tapbuf_size10_11_sram[0:3]));
mux_tree_tapbuf_size10_mem mem_top_ipin_8 (
.pReset(pReset),
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size6_mem_3_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size10_mem_12_ccff_tail),
.mem_out(mux_tree_tapbuf_size10_12_sram[0:3]));
mux_tree_tapbuf_size10_mem mem_top_ipin_10 (
.pReset(pReset),
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size6_mem_4_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size10_mem_13_ccff_tail),
.mem_out(mux_tree_tapbuf_size10_13_sram[0:3]));
mux_tree_tapbuf_size10_mem mem_top_ipin_12 (
.pReset(pReset),
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size6_mem_5_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size10_mem_14_ccff_tail),
.mem_out(mux_tree_tapbuf_size10_14_sram[0:3]));
mux_tree_tapbuf_size10_mem mem_top_ipin_14 (
.pReset(pReset),
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size6_mem_6_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size10_mem_15_ccff_tail),
.mem_out(mux_tree_tapbuf_size10_15_sram[0:3]));
mux_tree_tapbuf_size6 mux_top_ipin_1 (
.in({chanx_left_in[0], chanx_right_in[0], chanx_left_in[1], chanx_right_in[1], chanx_left_in[2], chanx_right_in[2]}),
.sram(mux_tree_tapbuf_size6_0_sram[0:2]),
.sram_inv(mux_top_ipin_1_undriven_sram_inv[0:2]),
.out(bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_));
mux_tree_tapbuf_size6 mux_top_ipin_3 (
.in({chanx_left_in[0], chanx_right_in[0], chanx_left_in[1], chanx_right_in[1], chanx_left_in[4], chanx_right_in[4]}),
.sram(mux_tree_tapbuf_size6_1_sram[0:2]),
.sram_inv(mux_top_ipin_3_undriven_sram_inv[0:2]),
.out(bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_));
mux_tree_tapbuf_size6 mux_top_ipin_5 (
.in({chanx_left_in[0], chanx_right_in[0], chanx_left_in[1], chanx_right_in[1], chanx_left_in[6], chanx_right_in[6]}),
.sram(mux_tree_tapbuf_size6_2_sram[0:2]),
.sram_inv(mux_top_ipin_5_undriven_sram_inv[0:2]),
.out(bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_));
mux_tree_tapbuf_size6 mux_top_ipin_7 (
.in({chanx_left_in[0], chanx_right_in[0], chanx_left_in[1], chanx_right_in[1], chanx_left_in[8], chanx_right_in[8]}),
.sram(mux_tree_tapbuf_size6_3_sram[0:2]),
.sram_inv(mux_top_ipin_7_undriven_sram_inv[0:2]),
.out(bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_));
mux_tree_tapbuf_size6 mux_top_ipin_9 (
.in({chanx_left_in[0], chanx_right_in[0], chanx_left_in[1], chanx_right_in[1], chanx_left_in[10], chanx_right_in[10]}),
.sram(mux_tree_tapbuf_size6_4_sram[0:2]),
.sram_inv(mux_top_ipin_9_undriven_sram_inv[0:2]),
.out(bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_));
mux_tree_tapbuf_size6 mux_top_ipin_11 (
.in({chanx_left_in[0], chanx_right_in[0], chanx_left_in[1], chanx_right_in[1], chanx_left_in[3], chanx_right_in[3]}),
.sram(mux_tree_tapbuf_size6_5_sram[0:2]),
.sram_inv(mux_top_ipin_11_undriven_sram_inv[0:2]),
.out(bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_));
mux_tree_tapbuf_size6 mux_top_ipin_13 (
.in({chanx_left_in[0], chanx_right_in[0], chanx_left_in[1], chanx_right_in[1], chanx_left_in[5], chanx_right_in[5]}),
.sram(mux_tree_tapbuf_size6_6_sram[0:2]),
.sram_inv(mux_top_ipin_13_undriven_sram_inv[0:2]),
.out(bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_));
mux_tree_tapbuf_size6 mux_top_ipin_15 (
.in({chanx_left_in[0], chanx_right_in[0], chanx_left_in[1], chanx_right_in[1], chanx_left_in[7], chanx_right_in[7]}),
.sram(mux_tree_tapbuf_size6_7_sram[0:2]),
.sram_inv(mux_top_ipin_15_undriven_sram_inv[0:2]),
.out(bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_));
mux_tree_tapbuf_size6_mem mem_top_ipin_1 (
.pReset(pReset),
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size10_mem_8_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size6_mem_0_ccff_tail),
.mem_out(mux_tree_tapbuf_size6_0_sram[0:2]));
mux_tree_tapbuf_size6_mem mem_top_ipin_3 (
.pReset(pReset),
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size10_mem_9_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size6_mem_1_ccff_tail),
.mem_out(mux_tree_tapbuf_size6_1_sram[0:2]));
mux_tree_tapbuf_size6_mem mem_top_ipin_5 (
.pReset(pReset),
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size10_mem_10_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size6_mem_2_ccff_tail),
.mem_out(mux_tree_tapbuf_size6_2_sram[0:2]));
mux_tree_tapbuf_size6_mem mem_top_ipin_7 (
.pReset(pReset),
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size10_mem_11_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size6_mem_3_ccff_tail),
.mem_out(mux_tree_tapbuf_size6_3_sram[0:2]));
mux_tree_tapbuf_size6_mem mem_top_ipin_9 (
.pReset(pReset),
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size10_mem_12_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size6_mem_4_ccff_tail),
.mem_out(mux_tree_tapbuf_size6_4_sram[0:2]));
mux_tree_tapbuf_size6_mem mem_top_ipin_11 (
.pReset(pReset),
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size10_mem_13_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size6_mem_5_ccff_tail),
.mem_out(mux_tree_tapbuf_size6_5_sram[0:2]));
mux_tree_tapbuf_size6_mem mem_top_ipin_13 (
.pReset(pReset),
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size10_mem_14_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size6_mem_6_ccff_tail),
.mem_out(mux_tree_tapbuf_size6_6_sram[0:2]));
mux_tree_tapbuf_size6_mem mem_top_ipin_15 (
.pReset(pReset),
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size10_mem_15_ccff_tail),
.ccff_tail(ccff_tail),
.mem_out(mux_tree_tapbuf_size6_7_sram[0:2]));
endmodule
// ----- END Verilog module for cbx_1__1_ -----
//----- Default net type -----
`default_nettype none

168
SOFA_A/SOFA_A_verilog/routing/cby_0__1_.v Normal file
View File

@ -0,0 +1,168 @@
//-------------------------------------------
// FPGA Synthesizable Verilog Netlist
// Description: Verilog modules for Unique Connection Blocks[0][1]
// Author: Xifan TANG
// Organization: University of Utah
// Date: Sun Feb 19 10:53:27 2023
//-------------------------------------------
//----- Time scale -----
`timescale 1ns / 1ps
//----- Default net type -----
`default_nettype none
// ----- Verilog module for cby_0__1_ -----
module cby_0__1_(pReset,
prog_clk,
chany_bottom_in,
chany_top_in,
ccff_head,
chany_bottom_out,
chany_top_out,
left_grid_right_width_0_height_0_subtile_0__pin_outpad_0_,
ccff_tail);
//----- GLOBAL PORTS -----
input [0:0] pReset;
//----- GLOBAL PORTS -----
input [0:0] prog_clk;
//----- INPUT PORTS -----
input [0:10] chany_bottom_in;
//----- INPUT PORTS -----
input [0:10] chany_top_in;
//----- INPUT PORTS -----
input [0:0] ccff_head;
//----- OUTPUT PORTS -----
output [0:10] chany_bottom_out;
//----- OUTPUT PORTS -----
output [0:10] chany_top_out;
//----- OUTPUT PORTS -----
output [0:0] left_grid_right_width_0_height_0_subtile_0__pin_outpad_0_;
//----- OUTPUT PORTS -----
output [0:0] ccff_tail;
//----- BEGIN wire-connection ports -----
//----- END wire-connection ports -----
//----- BEGIN Registered ports -----
//----- END Registered ports -----
wire [0:3] mux_right_ipin_0_undriven_sram_inv;
wire [0:3] mux_tree_tapbuf_size10_0_sram;
// ----- BEGIN Local short connections -----
// ----- Local connection due to Wire 0 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chany_top_out[0] = chany_bottom_in[0];
// ----- Local connection due to Wire 1 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chany_top_out[1] = chany_bottom_in[1];
// ----- Local connection due to Wire 2 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chany_top_out[2] = chany_bottom_in[2];
// ----- Local connection due to Wire 3 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chany_top_out[3] = chany_bottom_in[3];
// ----- Local connection due to Wire 4 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chany_top_out[4] = chany_bottom_in[4];
// ----- Local connection due to Wire 5 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chany_top_out[5] = chany_bottom_in[5];
// ----- Local connection due to Wire 6 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chany_top_out[6] = chany_bottom_in[6];
// ----- Local connection due to Wire 7 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chany_top_out[7] = chany_bottom_in[7];
// ----- Local connection due to Wire 8 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chany_top_out[8] = chany_bottom_in[8];
// ----- Local connection due to Wire 9 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chany_top_out[9] = chany_bottom_in[9];
// ----- Local connection due to Wire 10 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chany_top_out[10] = chany_bottom_in[10];
// ----- Local connection due to Wire 11 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chany_bottom_out[0] = chany_top_in[0];
// ----- Local connection due to Wire 12 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chany_bottom_out[1] = chany_top_in[1];
// ----- Local connection due to Wire 13 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chany_bottom_out[2] = chany_top_in[2];
// ----- Local connection due to Wire 14 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chany_bottom_out[3] = chany_top_in[3];
// ----- Local connection due to Wire 15 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chany_bottom_out[4] = chany_top_in[4];
// ----- Local connection due to Wire 16 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chany_bottom_out[5] = chany_top_in[5];
// ----- Local connection due to Wire 17 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chany_bottom_out[6] = chany_top_in[6];
// ----- Local connection due to Wire 18 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chany_bottom_out[7] = chany_top_in[7];
// ----- Local connection due to Wire 19 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chany_bottom_out[8] = chany_top_in[8];
// ----- Local connection due to Wire 20 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chany_bottom_out[9] = chany_top_in[9];
// ----- Local connection due to Wire 21 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chany_bottom_out[10] = chany_top_in[10];
// ----- END Local short connections -----
// ----- BEGIN Local output short connections -----
// ----- END Local output short connections -----
mux_tree_tapbuf_size10 mux_right_ipin_0 (
.in({chany_bottom_in[0], chany_top_in[0], chany_bottom_in[1], chany_top_in[1], chany_bottom_in[2], chany_top_in[2], chany_bottom_in[6], chany_top_in[6], chany_bottom_in[10], chany_top_in[10]}),
.sram(mux_tree_tapbuf_size10_0_sram[0:3]),
.sram_inv(mux_right_ipin_0_undriven_sram_inv[0:3]),
.out(left_grid_right_width_0_height_0_subtile_0__pin_outpad_0_));
mux_tree_tapbuf_size10_mem mem_right_ipin_0 (
.pReset(pReset),
.prog_clk(prog_clk),
.ccff_head(ccff_head),
.ccff_tail(ccff_tail),
.mem_out(mux_tree_tapbuf_size10_0_sram[0:3]));
endmodule
// ----- END Verilog module for cby_0__1_ -----
//----- Default net type -----
`default_nettype none

605
SOFA_A/SOFA_A_verilog/routing/cby_1__1_.v Normal file
View File

@ -0,0 +1,605 @@
//-------------------------------------------
// FPGA Synthesizable Verilog Netlist
// Description: Verilog modules for Unique Connection Blocks[1][1]
// Author: Xifan TANG
// Organization: University of Utah
// Date: Sun Feb 19 10:53:27 2023
//-------------------------------------------
//----- Time scale -----
`timescale 1ns / 1ps
//----- Default net type -----
`default_nettype none
// ----- Verilog module for cby_1__1_ -----
module cby_1__1_(pReset,
prog_clk,
chany_bottom_in,
chany_top_in,
ccff_head,
chany_bottom_out,
chany_top_out,
right_grid_left_width_0_height_0_subtile_0__pin_outpad_0_,
right_grid_left_width_0_height_0_subtile_1__pin_outpad_0_,
right_grid_left_width_0_height_0_subtile_2__pin_outpad_0_,
right_grid_left_width_0_height_0_subtile_3__pin_outpad_0_,
right_grid_left_width_0_height_0_subtile_4__pin_outpad_0_,
right_grid_left_width_0_height_0_subtile_5__pin_outpad_0_,
right_grid_left_width_0_height_0_subtile_6__pin_outpad_0_,
right_grid_left_width_0_height_0_subtile_7__pin_outpad_0_,
left_grid_right_width_0_height_0_subtile_0__pin_I4_0_,
left_grid_right_width_0_height_0_subtile_0__pin_I4_1_,
left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_,
left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_,
left_grid_right_width_0_height_0_subtile_0__pin_I5_0_,
left_grid_right_width_0_height_0_subtile_0__pin_I5_1_,
left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_,
left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_,
left_grid_right_width_0_height_0_subtile_0__pin_I6_0_,
left_grid_right_width_0_height_0_subtile_0__pin_I6_1_,
left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_,
left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_,
left_grid_right_width_0_height_0_subtile_0__pin_I7_0_,
left_grid_right_width_0_height_0_subtile_0__pin_I7_1_,
left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_,
left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_,
ccff_tail);
//----- GLOBAL PORTS -----
input [0:0] pReset;
//----- GLOBAL PORTS -----
input [0:0] prog_clk;
//----- INPUT PORTS -----
input [0:10] chany_bottom_in;
//----- INPUT PORTS -----
input [0:10] chany_top_in;
//----- INPUT PORTS -----
input [0:0] ccff_head;
//----- OUTPUT PORTS -----
output [0:10] chany_bottom_out;
//----- OUTPUT PORTS -----
output [0:10] chany_top_out;
//----- OUTPUT PORTS -----
output [0:0] right_grid_left_width_0_height_0_subtile_0__pin_outpad_0_;
//----- OUTPUT PORTS -----
output [0:0] right_grid_left_width_0_height_0_subtile_1__pin_outpad_0_;
//----- OUTPUT PORTS -----
output [0:0] right_grid_left_width_0_height_0_subtile_2__pin_outpad_0_;
//----- OUTPUT PORTS -----
output [0:0] right_grid_left_width_0_height_0_subtile_3__pin_outpad_0_;
//----- OUTPUT PORTS -----
output [0:0] right_grid_left_width_0_height_0_subtile_4__pin_outpad_0_;
//----- OUTPUT PORTS -----
output [0:0] right_grid_left_width_0_height_0_subtile_5__pin_outpad_0_;
//----- OUTPUT PORTS -----
output [0:0] right_grid_left_width_0_height_0_subtile_6__pin_outpad_0_;
//----- OUTPUT PORTS -----
output [0:0] right_grid_left_width_0_height_0_subtile_7__pin_outpad_0_;
//----- OUTPUT PORTS -----
output [0:0] left_grid_right_width_0_height_0_subtile_0__pin_I4_0_;
//----- OUTPUT PORTS -----
output [0:0] left_grid_right_width_0_height_0_subtile_0__pin_I4_1_;
//----- OUTPUT PORTS -----
output [0:0] left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_;
//----- OUTPUT PORTS -----
output [0:0] left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_;
//----- OUTPUT PORTS -----
output [0:0] left_grid_right_width_0_height_0_subtile_0__pin_I5_0_;
//----- OUTPUT PORTS -----
output [0:0] left_grid_right_width_0_height_0_subtile_0__pin_I5_1_;
//----- OUTPUT PORTS -----
output [0:0] left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_;
//----- OUTPUT PORTS -----
output [0:0] left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_;
//----- OUTPUT PORTS -----
output [0:0] left_grid_right_width_0_height_0_subtile_0__pin_I6_0_;
//----- OUTPUT PORTS -----
output [0:0] left_grid_right_width_0_height_0_subtile_0__pin_I6_1_;
//----- OUTPUT PORTS -----
output [0:0] left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_;
//----- OUTPUT PORTS -----
output [0:0] left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_;
//----- OUTPUT PORTS -----
output [0:0] left_grid_right_width_0_height_0_subtile_0__pin_I7_0_;
//----- OUTPUT PORTS -----
output [0:0] left_grid_right_width_0_height_0_subtile_0__pin_I7_1_;
//----- OUTPUT PORTS -----
output [0:0] left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_;
//----- OUTPUT PORTS -----
output [0:0] left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_;
//----- OUTPUT PORTS -----
output [0:0] ccff_tail;
//----- BEGIN wire-connection ports -----
//----- END wire-connection ports -----
//----- BEGIN Registered ports -----
//----- END Registered ports -----
wire [0:3] mux_left_ipin_0_undriven_sram_inv;
wire [0:3] mux_left_ipin_1_undriven_sram_inv;
wire [0:3] mux_left_ipin_2_undriven_sram_inv;
wire [0:3] mux_left_ipin_3_undriven_sram_inv;
wire [0:3] mux_left_ipin_4_undriven_sram_inv;
wire [0:3] mux_left_ipin_5_undriven_sram_inv;
wire [0:3] mux_left_ipin_6_undriven_sram_inv;
wire [0:3] mux_left_ipin_7_undriven_sram_inv;
wire [0:3] mux_right_ipin_0_undriven_sram_inv;
wire [0:3] mux_right_ipin_10_undriven_sram_inv;
wire [0:2] mux_right_ipin_11_undriven_sram_inv;
wire [0:3] mux_right_ipin_12_undriven_sram_inv;
wire [0:2] mux_right_ipin_13_undriven_sram_inv;
wire [0:3] mux_right_ipin_14_undriven_sram_inv;
wire [0:2] mux_right_ipin_15_undriven_sram_inv;
wire [0:2] mux_right_ipin_1_undriven_sram_inv;
wire [0:3] mux_right_ipin_2_undriven_sram_inv;
wire [0:2] mux_right_ipin_3_undriven_sram_inv;
wire [0:3] mux_right_ipin_4_undriven_sram_inv;
wire [0:2] mux_right_ipin_5_undriven_sram_inv;
wire [0:3] mux_right_ipin_6_undriven_sram_inv;
wire [0:2] mux_right_ipin_7_undriven_sram_inv;
wire [0:3] mux_right_ipin_8_undriven_sram_inv;
wire [0:2] mux_right_ipin_9_undriven_sram_inv;
wire [0:3] mux_tree_tapbuf_size10_0_sram;
wire [0:3] mux_tree_tapbuf_size10_10_sram;
wire [0:3] mux_tree_tapbuf_size10_11_sram;
wire [0:3] mux_tree_tapbuf_size10_12_sram;
wire [0:3] mux_tree_tapbuf_size10_13_sram;
wire [0:3] mux_tree_tapbuf_size10_14_sram;
wire [0:3] mux_tree_tapbuf_size10_15_sram;
wire [0:3] mux_tree_tapbuf_size10_1_sram;
wire [0:3] mux_tree_tapbuf_size10_2_sram;
wire [0:3] mux_tree_tapbuf_size10_3_sram;
wire [0:3] mux_tree_tapbuf_size10_4_sram;
wire [0:3] mux_tree_tapbuf_size10_5_sram;
wire [0:3] mux_tree_tapbuf_size10_6_sram;
wire [0:3] mux_tree_tapbuf_size10_7_sram;
wire [0:3] mux_tree_tapbuf_size10_8_sram;
wire [0:3] mux_tree_tapbuf_size10_9_sram;
wire [0:0] mux_tree_tapbuf_size10_mem_0_ccff_tail;
wire [0:0] mux_tree_tapbuf_size10_mem_10_ccff_tail;
wire [0:0] mux_tree_tapbuf_size10_mem_11_ccff_tail;
wire [0:0] mux_tree_tapbuf_size10_mem_12_ccff_tail;
wire [0:0] mux_tree_tapbuf_size10_mem_13_ccff_tail;
wire [0:0] mux_tree_tapbuf_size10_mem_14_ccff_tail;
wire [0:0] mux_tree_tapbuf_size10_mem_15_ccff_tail;
wire [0:0] mux_tree_tapbuf_size10_mem_1_ccff_tail;
wire [0:0] mux_tree_tapbuf_size10_mem_2_ccff_tail;
wire [0:0] mux_tree_tapbuf_size10_mem_3_ccff_tail;
wire [0:0] mux_tree_tapbuf_size10_mem_4_ccff_tail;
wire [0:0] mux_tree_tapbuf_size10_mem_5_ccff_tail;
wire [0:0] mux_tree_tapbuf_size10_mem_6_ccff_tail;
wire [0:0] mux_tree_tapbuf_size10_mem_7_ccff_tail;
wire [0:0] mux_tree_tapbuf_size10_mem_8_ccff_tail;
wire [0:0] mux_tree_tapbuf_size10_mem_9_ccff_tail;
wire [0:2] mux_tree_tapbuf_size6_0_sram;
wire [0:2] mux_tree_tapbuf_size6_1_sram;
wire [0:2] mux_tree_tapbuf_size6_2_sram;
wire [0:2] mux_tree_tapbuf_size6_3_sram;
wire [0:2] mux_tree_tapbuf_size6_4_sram;
wire [0:2] mux_tree_tapbuf_size6_5_sram;
wire [0:2] mux_tree_tapbuf_size6_6_sram;
wire [0:2] mux_tree_tapbuf_size6_7_sram;
wire [0:0] mux_tree_tapbuf_size6_mem_0_ccff_tail;
wire [0:0] mux_tree_tapbuf_size6_mem_1_ccff_tail;
wire [0:0] mux_tree_tapbuf_size6_mem_2_ccff_tail;
wire [0:0] mux_tree_tapbuf_size6_mem_3_ccff_tail;
wire [0:0] mux_tree_tapbuf_size6_mem_4_ccff_tail;
wire [0:0] mux_tree_tapbuf_size6_mem_5_ccff_tail;
wire [0:0] mux_tree_tapbuf_size6_mem_6_ccff_tail;
// ----- BEGIN Local short connections -----
// ----- Local connection due to Wire 0 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chany_top_out[0] = chany_bottom_in[0];
// ----- Local connection due to Wire 1 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chany_top_out[1] = chany_bottom_in[1];
// ----- Local connection due to Wire 2 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chany_top_out[2] = chany_bottom_in[2];
// ----- Local connection due to Wire 3 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chany_top_out[3] = chany_bottom_in[3];
// ----- Local connection due to Wire 4 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chany_top_out[4] = chany_bottom_in[4];
// ----- Local connection due to Wire 5 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chany_top_out[5] = chany_bottom_in[5];
// ----- Local connection due to Wire 6 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chany_top_out[6] = chany_bottom_in[6];
// ----- Local connection due to Wire 7 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chany_top_out[7] = chany_bottom_in[7];
// ----- Local connection due to Wire 8 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chany_top_out[8] = chany_bottom_in[8];
// ----- Local connection due to Wire 9 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chany_top_out[9] = chany_bottom_in[9];
// ----- Local connection due to Wire 10 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chany_top_out[10] = chany_bottom_in[10];
// ----- Local connection due to Wire 11 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chany_bottom_out[0] = chany_top_in[0];
// ----- Local connection due to Wire 12 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chany_bottom_out[1] = chany_top_in[1];
// ----- Local connection due to Wire 13 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chany_bottom_out[2] = chany_top_in[2];
// ----- Local connection due to Wire 14 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chany_bottom_out[3] = chany_top_in[3];
// ----- Local connection due to Wire 15 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chany_bottom_out[4] = chany_top_in[4];
// ----- Local connection due to Wire 16 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chany_bottom_out[5] = chany_top_in[5];
// ----- Local connection due to Wire 17 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chany_bottom_out[6] = chany_top_in[6];
// ----- Local connection due to Wire 18 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chany_bottom_out[7] = chany_top_in[7];
// ----- Local connection due to Wire 19 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chany_bottom_out[8] = chany_top_in[8];
// ----- Local connection due to Wire 20 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chany_bottom_out[9] = chany_top_in[9];
// ----- Local connection due to Wire 21 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chany_bottom_out[10] = chany_top_in[10];
// ----- END Local short connections -----
// ----- BEGIN Local output short connections -----
// ----- END Local output short connections -----
mux_tree_tapbuf_size10 mux_left_ipin_0 (
.in({chany_bottom_in[0], chany_top_in[0], chany_bottom_in[1], chany_top_in[1], chany_bottom_in[2], chany_top_in[2], chany_bottom_in[6], chany_top_in[6], chany_bottom_in[10], chany_top_in[10]}),
.sram(mux_tree_tapbuf_size10_0_sram[0:3]),
.sram_inv(mux_left_ipin_0_undriven_sram_inv[0:3]),
.out(right_grid_left_width_0_height_0_subtile_0__pin_outpad_0_));
mux_tree_tapbuf_size10 mux_left_ipin_1 (
.in({chany_bottom_in[0], chany_top_in[0], chany_bottom_in[1], chany_top_in[1], chany_bottom_in[2], chany_top_in[2], chany_bottom_in[3], chany_top_in[3], chany_bottom_in[7], chany_top_in[7]}),
.sram(mux_tree_tapbuf_size10_1_sram[0:3]),
.sram_inv(mux_left_ipin_1_undriven_sram_inv[0:3]),
.out(right_grid_left_width_0_height_0_subtile_1__pin_outpad_0_));
mux_tree_tapbuf_size10 mux_left_ipin_2 (
.in({chany_bottom_in[0], chany_top_in[0], chany_bottom_in[1], chany_top_in[1], chany_bottom_in[3], chany_top_in[3], chany_bottom_in[4], chany_top_in[4], chany_bottom_in[8], chany_top_in[8]}),
.sram(mux_tree_tapbuf_size10_2_sram[0:3]),
.sram_inv(mux_left_ipin_2_undriven_sram_inv[0:3]),
.out(right_grid_left_width_0_height_0_subtile_2__pin_outpad_0_));
mux_tree_tapbuf_size10 mux_left_ipin_3 (
.in({chany_bottom_in[0], chany_top_in[0], chany_bottom_in[1], chany_top_in[1], chany_bottom_in[4], chany_top_in[4], chany_bottom_in[5], chany_top_in[5], chany_bottom_in[9], chany_top_in[9]}),
.sram(mux_tree_tapbuf_size10_3_sram[0:3]),
.sram_inv(mux_left_ipin_3_undriven_sram_inv[0:3]),
.out(right_grid_left_width_0_height_0_subtile_3__pin_outpad_0_));
mux_tree_tapbuf_size10 mux_left_ipin_4 (
.in({chany_bottom_in[0], chany_top_in[0], chany_bottom_in[1], chany_top_in[1], chany_bottom_in[5], chany_top_in[5], chany_bottom_in[6], chany_top_in[6], chany_bottom_in[10], chany_top_in[10]}),
.sram(mux_tree_tapbuf_size10_4_sram[0:3]),
.sram_inv(mux_left_ipin_4_undriven_sram_inv[0:3]),
.out(right_grid_left_width_0_height_0_subtile_4__pin_outpad_0_));
mux_tree_tapbuf_size10 mux_left_ipin_5 (
.in({chany_bottom_in[0], chany_top_in[0], chany_bottom_in[1], chany_top_in[1], chany_bottom_in[2], chany_top_in[2], chany_bottom_in[6], chany_top_in[6], chany_bottom_in[7], chany_top_in[7]}),
.sram(mux_tree_tapbuf_size10_5_sram[0:3]),
.sram_inv(mux_left_ipin_5_undriven_sram_inv[0:3]),
.out(right_grid_left_width_0_height_0_subtile_5__pin_outpad_0_));
mux_tree_tapbuf_size10 mux_left_ipin_6 (
.in({chany_bottom_in[0], chany_top_in[0], chany_bottom_in[1], chany_top_in[1], chany_bottom_in[3], chany_top_in[3], chany_bottom_in[7], chany_top_in[7], chany_bottom_in[8], chany_top_in[8]}),
.sram(mux_tree_tapbuf_size10_6_sram[0:3]),
.sram_inv(mux_left_ipin_6_undriven_sram_inv[0:3]),
.out(right_grid_left_width_0_height_0_subtile_6__pin_outpad_0_));
mux_tree_tapbuf_size10 mux_left_ipin_7 (
.in({chany_bottom_in[0], chany_top_in[0], chany_bottom_in[1], chany_top_in[1], chany_bottom_in[4], chany_top_in[4], chany_bottom_in[8], chany_top_in[8], chany_bottom_in[9], chany_top_in[9]}),
.sram(mux_tree_tapbuf_size10_7_sram[0:3]),
.sram_inv(mux_left_ipin_7_undriven_sram_inv[0:3]),
.out(right_grid_left_width_0_height_0_subtile_7__pin_outpad_0_));
mux_tree_tapbuf_size10 mux_right_ipin_0 (
.in({chany_bottom_in[0], chany_top_in[0], chany_bottom_in[1], chany_top_in[1], chany_bottom_in[5], chany_top_in[5], chany_bottom_in[9], chany_top_in[9], chany_bottom_in[10], chany_top_in[10]}),
.sram(mux_tree_tapbuf_size10_8_sram[0:3]),
.sram_inv(mux_right_ipin_0_undriven_sram_inv[0:3]),
.out(left_grid_right_width_0_height_0_subtile_0__pin_I4_0_));
mux_tree_tapbuf_size10 mux_right_ipin_2 (
.in({chany_bottom_in[0], chany_top_in[0], chany_bottom_in[1], chany_top_in[1], chany_bottom_in[2], chany_top_in[2], chany_bottom_in[3], chany_top_in[3], chany_bottom_in[7], chany_top_in[7]}),
.sram(mux_tree_tapbuf_size10_9_sram[0:3]),
.sram_inv(mux_right_ipin_2_undriven_sram_inv[0:3]),
.out(left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_));
mux_tree_tapbuf_size10 mux_right_ipin_4 (
.in({chany_bottom_in[0], chany_top_in[0], chany_bottom_in[1], chany_top_in[1], chany_bottom_in[4], chany_top_in[4], chany_bottom_in[5], chany_top_in[5], chany_bottom_in[9], chany_top_in[9]}),
.sram(mux_tree_tapbuf_size10_10_sram[0:3]),
.sram_inv(mux_right_ipin_4_undriven_sram_inv[0:3]),
.out(left_grid_right_width_0_height_0_subtile_0__pin_I5_0_));
mux_tree_tapbuf_size10 mux_right_ipin_6 (
.in({chany_bottom_in[0], chany_top_in[0], chany_bottom_in[1], chany_top_in[1], chany_bottom_in[2], chany_top_in[2], chany_bottom_in[6], chany_top_in[6], chany_bottom_in[7], chany_top_in[7]}),
.sram(mux_tree_tapbuf_size10_11_sram[0:3]),
.sram_inv(mux_right_ipin_6_undriven_sram_inv[0:3]),
.out(left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_));
mux_tree_tapbuf_size10 mux_right_ipin_8 (
.in({chany_bottom_in[0], chany_top_in[0], chany_bottom_in[1], chany_top_in[1], chany_bottom_in[4], chany_top_in[4], chany_bottom_in[8], chany_top_in[8], chany_bottom_in[9], chany_top_in[9]}),
.sram(mux_tree_tapbuf_size10_12_sram[0:3]),
.sram_inv(mux_right_ipin_8_undriven_sram_inv[0:3]),
.out(left_grid_right_width_0_height_0_subtile_0__pin_I6_0_));
mux_tree_tapbuf_size10 mux_right_ipin_10 (
.in({chany_bottom_in[0], chany_top_in[0], chany_bottom_in[1], chany_top_in[1], chany_bottom_in[2], chany_top_in[2], chany_bottom_in[6], chany_top_in[6], chany_bottom_in[10], chany_top_in[10]}),
.sram(mux_tree_tapbuf_size10_13_sram[0:3]),
.sram_inv(mux_right_ipin_10_undriven_sram_inv[0:3]),
.out(left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_));
mux_tree_tapbuf_size10 mux_right_ipin_12 (
.in({chany_bottom_in[0], chany_top_in[0], chany_bottom_in[1], chany_top_in[1], chany_bottom_in[3], chany_top_in[3], chany_bottom_in[4], chany_top_in[4], chany_bottom_in[8], chany_top_in[8]}),
.sram(mux_tree_tapbuf_size10_14_sram[0:3]),
.sram_inv(mux_right_ipin_12_undriven_sram_inv[0:3]),
.out(left_grid_right_width_0_height_0_subtile_0__pin_I7_0_));
mux_tree_tapbuf_size10 mux_right_ipin_14 (
.in({chany_bottom_in[0], chany_top_in[0], chany_bottom_in[1], chany_top_in[1], chany_bottom_in[5], chany_top_in[5], chany_bottom_in[6], chany_top_in[6], chany_bottom_in[10], chany_top_in[10]}),
.sram(mux_tree_tapbuf_size10_15_sram[0:3]),
.sram_inv(mux_right_ipin_14_undriven_sram_inv[0:3]),
.out(left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_));
mux_tree_tapbuf_size10_mem mem_left_ipin_0 (
.pReset(pReset),
.prog_clk(prog_clk),
.ccff_head(ccff_head),
.ccff_tail(mux_tree_tapbuf_size10_mem_0_ccff_tail),
.mem_out(mux_tree_tapbuf_size10_0_sram[0:3]));
mux_tree_tapbuf_size10_mem mem_left_ipin_1 (
.pReset(pReset),
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size10_mem_0_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size10_mem_1_ccff_tail),
.mem_out(mux_tree_tapbuf_size10_1_sram[0:3]));
mux_tree_tapbuf_size10_mem mem_left_ipin_2 (
.pReset(pReset),
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size10_mem_1_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size10_mem_2_ccff_tail),
.mem_out(mux_tree_tapbuf_size10_2_sram[0:3]));
mux_tree_tapbuf_size10_mem mem_left_ipin_3 (
.pReset(pReset),
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size10_mem_2_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size10_mem_3_ccff_tail),
.mem_out(mux_tree_tapbuf_size10_3_sram[0:3]));
mux_tree_tapbuf_size10_mem mem_left_ipin_4 (
.pReset(pReset),
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size10_mem_3_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size10_mem_4_ccff_tail),
.mem_out(mux_tree_tapbuf_size10_4_sram[0:3]));
mux_tree_tapbuf_size10_mem mem_left_ipin_5 (
.pReset(pReset),
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size10_mem_4_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size10_mem_5_ccff_tail),
.mem_out(mux_tree_tapbuf_size10_5_sram[0:3]));
mux_tree_tapbuf_size10_mem mem_left_ipin_6 (
.pReset(pReset),
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size10_mem_5_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size10_mem_6_ccff_tail),
.mem_out(mux_tree_tapbuf_size10_6_sram[0:3]));
mux_tree_tapbuf_size10_mem mem_left_ipin_7 (
.pReset(pReset),
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size10_mem_6_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size10_mem_7_ccff_tail),
.mem_out(mux_tree_tapbuf_size10_7_sram[0:3]));
mux_tree_tapbuf_size10_mem mem_right_ipin_0 (
.pReset(pReset),
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size10_mem_7_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size10_mem_8_ccff_tail),
.mem_out(mux_tree_tapbuf_size10_8_sram[0:3]));
mux_tree_tapbuf_size10_mem mem_right_ipin_2 (
.pReset(pReset),
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size6_mem_0_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size10_mem_9_ccff_tail),
.mem_out(mux_tree_tapbuf_size10_9_sram[0:3]));
mux_tree_tapbuf_size10_mem mem_right_ipin_4 (
.pReset(pReset),
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size6_mem_1_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size10_mem_10_ccff_tail),
.mem_out(mux_tree_tapbuf_size10_10_sram[0:3]));
mux_tree_tapbuf_size10_mem mem_right_ipin_6 (
.pReset(pReset),
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size6_mem_2_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size10_mem_11_ccff_tail),
.mem_out(mux_tree_tapbuf_size10_11_sram[0:3]));
mux_tree_tapbuf_size10_mem mem_right_ipin_8 (
.pReset(pReset),
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size6_mem_3_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size10_mem_12_ccff_tail),
.mem_out(mux_tree_tapbuf_size10_12_sram[0:3]));
mux_tree_tapbuf_size10_mem mem_right_ipin_10 (
.pReset(pReset),
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size6_mem_4_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size10_mem_13_ccff_tail),
.mem_out(mux_tree_tapbuf_size10_13_sram[0:3]));
mux_tree_tapbuf_size10_mem mem_right_ipin_12 (
.pReset(pReset),
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size6_mem_5_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size10_mem_14_ccff_tail),
.mem_out(mux_tree_tapbuf_size10_14_sram[0:3]));
mux_tree_tapbuf_size10_mem mem_right_ipin_14 (
.pReset(pReset),
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size6_mem_6_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size10_mem_15_ccff_tail),
.mem_out(mux_tree_tapbuf_size10_15_sram[0:3]));
mux_tree_tapbuf_size6 mux_right_ipin_1 (
.in({chany_bottom_in[0], chany_top_in[0], chany_bottom_in[1], chany_top_in[1], chany_bottom_in[2], chany_top_in[2]}),
.sram(mux_tree_tapbuf_size6_0_sram[0:2]),
.sram_inv(mux_right_ipin_1_undriven_sram_inv[0:2]),
.out(left_grid_right_width_0_height_0_subtile_0__pin_I4_1_));
mux_tree_tapbuf_size6 mux_right_ipin_3 (
.in({chany_bottom_in[0], chany_top_in[0], chany_bottom_in[1], chany_top_in[1], chany_bottom_in[4], chany_top_in[4]}),
.sram(mux_tree_tapbuf_size6_1_sram[0:2]),
.sram_inv(mux_right_ipin_3_undriven_sram_inv[0:2]),
.out(left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_));
mux_tree_tapbuf_size6 mux_right_ipin_5 (
.in({chany_bottom_in[0], chany_top_in[0], chany_bottom_in[1], chany_top_in[1], chany_bottom_in[6], chany_top_in[6]}),
.sram(mux_tree_tapbuf_size6_2_sram[0:2]),
.sram_inv(mux_right_ipin_5_undriven_sram_inv[0:2]),
.out(left_grid_right_width_0_height_0_subtile_0__pin_I5_1_));
mux_tree_tapbuf_size6 mux_right_ipin_7 (
.in({chany_bottom_in[0], chany_top_in[0], chany_bottom_in[1], chany_top_in[1], chany_bottom_in[8], chany_top_in[8]}),
.sram(mux_tree_tapbuf_size6_3_sram[0:2]),
.sram_inv(mux_right_ipin_7_undriven_sram_inv[0:2]),
.out(left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_));
mux_tree_tapbuf_size6 mux_right_ipin_9 (
.in({chany_bottom_in[0], chany_top_in[0], chany_bottom_in[1], chany_top_in[1], chany_bottom_in[10], chany_top_in[10]}),
.sram(mux_tree_tapbuf_size6_4_sram[0:2]),
.sram_inv(mux_right_ipin_9_undriven_sram_inv[0:2]),
.out(left_grid_right_width_0_height_0_subtile_0__pin_I6_1_));
mux_tree_tapbuf_size6 mux_right_ipin_11 (
.in({chany_bottom_in[0], chany_top_in[0], chany_bottom_in[1], chany_top_in[1], chany_bottom_in[3], chany_top_in[3]}),
.sram(mux_tree_tapbuf_size6_5_sram[0:2]),
.sram_inv(mux_right_ipin_11_undriven_sram_inv[0:2]),
.out(left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_));
mux_tree_tapbuf_size6 mux_right_ipin_13 (
.in({chany_bottom_in[0], chany_top_in[0], chany_bottom_in[1], chany_top_in[1], chany_bottom_in[5], chany_top_in[5]}),
.sram(mux_tree_tapbuf_size6_6_sram[0:2]),
.sram_inv(mux_right_ipin_13_undriven_sram_inv[0:2]),
.out(left_grid_right_width_0_height_0_subtile_0__pin_I7_1_));
mux_tree_tapbuf_size6 mux_right_ipin_15 (
.in({chany_bottom_in[0], chany_top_in[0], chany_bottom_in[1], chany_top_in[1], chany_bottom_in[7], chany_top_in[7]}),
.sram(mux_tree_tapbuf_size6_7_sram[0:2]),
.sram_inv(mux_right_ipin_15_undriven_sram_inv[0:2]),
.out(left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_));
mux_tree_tapbuf_size6_mem mem_right_ipin_1 (
.pReset(pReset),
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size10_mem_8_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size6_mem_0_ccff_tail),
.mem_out(mux_tree_tapbuf_size6_0_sram[0:2]));
mux_tree_tapbuf_size6_mem mem_right_ipin_3 (
.pReset(pReset),
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size10_mem_9_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size6_mem_1_ccff_tail),
.mem_out(mux_tree_tapbuf_size6_1_sram[0:2]));
mux_tree_tapbuf_size6_mem mem_right_ipin_5 (
.pReset(pReset),
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size10_mem_10_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size6_mem_2_ccff_tail),
.mem_out(mux_tree_tapbuf_size6_2_sram[0:2]));
mux_tree_tapbuf_size6_mem mem_right_ipin_7 (
.pReset(pReset),
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size10_mem_11_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size6_mem_3_ccff_tail),
.mem_out(mux_tree_tapbuf_size6_3_sram[0:2]));
mux_tree_tapbuf_size6_mem mem_right_ipin_9 (
.pReset(pReset),
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size10_mem_12_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size6_mem_4_ccff_tail),
.mem_out(mux_tree_tapbuf_size6_4_sram[0:2]));
mux_tree_tapbuf_size6_mem mem_right_ipin_11 (
.pReset(pReset),
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size10_mem_13_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size6_mem_5_ccff_tail),
.mem_out(mux_tree_tapbuf_size6_5_sram[0:2]));
mux_tree_tapbuf_size6_mem mem_right_ipin_13 (
.pReset(pReset),
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size10_mem_14_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size6_mem_6_ccff_tail),
.mem_out(mux_tree_tapbuf_size6_6_sram[0:2]));
mux_tree_tapbuf_size6_mem mem_right_ipin_15 (
.pReset(pReset),
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size10_mem_15_ccff_tail),
.ccff_tail(ccff_tail),
.mem_out(mux_tree_tapbuf_size6_7_sram[0:2]));
endmodule
// ----- END Verilog module for cby_1__1_ -----
//----- Default net type -----
`default_nettype none

346
SOFA_A/SOFA_A_verilog/routing/sb_0__0_.v Normal file
View File

@ -0,0 +1,346 @@
//-------------------------------------------
// FPGA Synthesizable Verilog Netlist
// Description: Verilog modules for Unique Switch Blocks[0][0]
// Author: Xifan TANG
// Organization: University of Utah
// Date: Sun Feb 19 10:53:27 2023
//-------------------------------------------
//----- Time scale -----
`timescale 1ns / 1ps
//----- Default net type -----
`default_nettype none
// ----- Verilog module for sb_0__0_ -----
module sb_0__0_(pReset,
prog_clk,
chany_top_in,
top_left_grid_right_width_0_height_0_subtile_0__pin_inpad_0_,
chanx_right_in,
right_bottom_grid_top_width_0_height_0_subtile_0__pin_inpad_0_,
right_bottom_grid_top_width_0_height_0_subtile_1__pin_inpad_0_,
right_bottom_grid_top_width_0_height_0_subtile_2__pin_inpad_0_,
right_bottom_grid_top_width_0_height_0_subtile_3__pin_inpad_0_,
right_bottom_grid_top_width_0_height_0_subtile_4__pin_inpad_0_,
right_bottom_grid_top_width_0_height_0_subtile_5__pin_inpad_0_,
right_bottom_grid_top_width_0_height_0_subtile_6__pin_inpad_0_,
right_bottom_grid_top_width_0_height_0_subtile_7__pin_inpad_0_,
right_bottom_grid_top_width_0_height_0_subtile_8__pin_inpad_0_,
ccff_head,
chany_top_out,
chanx_right_out,
ccff_tail);
//----- GLOBAL PORTS -----
input [0:0] pReset;
//----- GLOBAL PORTS -----
input [0:0] prog_clk;
//----- INPUT PORTS -----
input [0:10] chany_top_in;
//----- INPUT PORTS -----
input [0:0] top_left_grid_right_width_0_height_0_subtile_0__pin_inpad_0_;
//----- INPUT PORTS -----
input [0:10] chanx_right_in;
//----- INPUT PORTS -----
input [0:0] right_bottom_grid_top_width_0_height_0_subtile_0__pin_inpad_0_;
//----- INPUT PORTS -----
input [0:0] right_bottom_grid_top_width_0_height_0_subtile_1__pin_inpad_0_;
//----- INPUT PORTS -----
input [0:0] right_bottom_grid_top_width_0_height_0_subtile_2__pin_inpad_0_;
//----- INPUT PORTS -----
input [0:0] right_bottom_grid_top_width_0_height_0_subtile_3__pin_inpad_0_;
//----- INPUT PORTS -----
input [0:0] right_bottom_grid_top_width_0_height_0_subtile_4__pin_inpad_0_;
//----- INPUT PORTS -----
input [0:0] right_bottom_grid_top_width_0_height_0_subtile_5__pin_inpad_0_;
//----- INPUT PORTS -----
input [0:0] right_bottom_grid_top_width_0_height_0_subtile_6__pin_inpad_0_;
//----- INPUT PORTS -----
input [0:0] right_bottom_grid_top_width_0_height_0_subtile_7__pin_inpad_0_;
//----- INPUT PORTS -----
input [0:0] right_bottom_grid_top_width_0_height_0_subtile_8__pin_inpad_0_;
//----- INPUT PORTS -----
input [0:0] ccff_head;
//----- OUTPUT PORTS -----
output [0:10] chany_top_out;
//----- OUTPUT PORTS -----
output [0:10] chanx_right_out;
//----- OUTPUT PORTS -----
output [0:0] ccff_tail;
//----- BEGIN wire-connection ports -----
//----- END wire-connection ports -----
//----- BEGIN Registered ports -----
//----- END Registered ports -----
wire [0:3] mux_right_track_0_undriven_sram_inv;
wire [0:1] mux_right_track_10_undriven_sram_inv;
wire [0:1] mux_right_track_12_undriven_sram_inv;
wire [0:1] mux_right_track_14_undriven_sram_inv;
wire [0:1] mux_right_track_16_undriven_sram_inv;
wire [0:1] mux_right_track_18_undriven_sram_inv;
wire [0:1] mux_right_track_20_undriven_sram_inv;
wire [0:3] mux_right_track_2_undriven_sram_inv;
wire [0:1] mux_right_track_4_undriven_sram_inv;
wire [0:1] mux_right_track_6_undriven_sram_inv;
wire [0:1] mux_right_track_8_undriven_sram_inv;
wire [0:1] mux_top_track_0_undriven_sram_inv;
wire [0:1] mux_top_track_2_undriven_sram_inv;
wire [0:1] mux_top_track_4_undriven_sram_inv;
wire [0:3] mux_tree_tapbuf_size10_0_sram;
wire [0:3] mux_tree_tapbuf_size10_1_sram;
wire [0:0] mux_tree_tapbuf_size10_mem_0_ccff_tail;
wire [0:0] mux_tree_tapbuf_size10_mem_1_ccff_tail;
wire [0:1] mux_tree_tapbuf_size2_0_sram;
wire [0:1] mux_tree_tapbuf_size2_10_sram;
wire [0:1] mux_tree_tapbuf_size2_11_sram;
wire [0:1] mux_tree_tapbuf_size2_1_sram;
wire [0:1] mux_tree_tapbuf_size2_2_sram;
wire [0:1] mux_tree_tapbuf_size2_3_sram;
wire [0:1] mux_tree_tapbuf_size2_4_sram;
wire [0:1] mux_tree_tapbuf_size2_5_sram;
wire [0:1] mux_tree_tapbuf_size2_6_sram;
wire [0:1] mux_tree_tapbuf_size2_7_sram;
wire [0:1] mux_tree_tapbuf_size2_8_sram;
wire [0:1] mux_tree_tapbuf_size2_9_sram;
wire [0:0] mux_tree_tapbuf_size2_mem_0_ccff_tail;
wire [0:0] mux_tree_tapbuf_size2_mem_10_ccff_tail;
wire [0:0] mux_tree_tapbuf_size2_mem_1_ccff_tail;
wire [0:0] mux_tree_tapbuf_size2_mem_2_ccff_tail;
wire [0:0] mux_tree_tapbuf_size2_mem_3_ccff_tail;
wire [0:0] mux_tree_tapbuf_size2_mem_4_ccff_tail;
wire [0:0] mux_tree_tapbuf_size2_mem_5_ccff_tail;
wire [0:0] mux_tree_tapbuf_size2_mem_6_ccff_tail;
wire [0:0] mux_tree_tapbuf_size2_mem_7_ccff_tail;
wire [0:0] mux_tree_tapbuf_size2_mem_8_ccff_tail;
wire [0:0] mux_tree_tapbuf_size2_mem_9_ccff_tail;
// ----- BEGIN Local short connections -----
// ----- Local connection due to Wire 12 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chany_top_out[10] = chanx_right_in[0];
// ----- Local connection due to Wire 16 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chany_top_out[3] = chanx_right_in[4];
// ----- Local connection due to Wire 17 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chany_top_out[4] = chanx_right_in[5];
// ----- Local connection due to Wire 18 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chany_top_out[5] = chanx_right_in[6];
// ----- Local connection due to Wire 19 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chany_top_out[6] = chanx_right_in[7];
// ----- Local connection due to Wire 20 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chany_top_out[7] = chanx_right_in[8];
// ----- Local connection due to Wire 21 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chany_top_out[8] = chanx_right_in[9];
// ----- Local connection due to Wire 22 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chany_top_out[9] = chanx_right_in[10];
// ----- END Local short connections -----
// ----- BEGIN Local output short connections -----
// ----- END Local output short connections -----
mux_tree_tapbuf_size2 mux_top_track_0 (
.in({top_left_grid_right_width_0_height_0_subtile_0__pin_inpad_0_, chanx_right_in[1]}),
.sram(mux_tree_tapbuf_size2_0_sram[0:1]),
.sram_inv(mux_top_track_0_undriven_sram_inv[0:1]),
.out(chany_top_out[0]));
mux_tree_tapbuf_size2 mux_top_track_2 (
.in({top_left_grid_right_width_0_height_0_subtile_0__pin_inpad_0_, chanx_right_in[2]}),
.sram(mux_tree_tapbuf_size2_1_sram[0:1]),
.sram_inv(mux_top_track_2_undriven_sram_inv[0:1]),
.out(chany_top_out[1]));
mux_tree_tapbuf_size2 mux_top_track_4 (
.in({top_left_grid_right_width_0_height_0_subtile_0__pin_inpad_0_, chanx_right_in[3]}),
.sram(mux_tree_tapbuf_size2_2_sram[0:1]),
.sram_inv(mux_top_track_4_undriven_sram_inv[0:1]),
.out(chany_top_out[2]));
mux_tree_tapbuf_size2 mux_right_track_4 (
.in({chany_top_in[1], right_bottom_grid_top_width_0_height_0_subtile_0__pin_inpad_0_}),
.sram(mux_tree_tapbuf_size2_3_sram[0:1]),
.sram_inv(mux_right_track_4_undriven_sram_inv[0:1]),
.out(chanx_right_out[2]));
mux_tree_tapbuf_size2 mux_right_track_6 (
.in({chany_top_in[2], right_bottom_grid_top_width_0_height_0_subtile_1__pin_inpad_0_}),
.sram(mux_tree_tapbuf_size2_4_sram[0:1]),
.sram_inv(mux_right_track_6_undriven_sram_inv[0:1]),
.out(chanx_right_out[3]));
mux_tree_tapbuf_size2 mux_right_track_8 (
.in({chany_top_in[3], right_bottom_grid_top_width_0_height_0_subtile_2__pin_inpad_0_}),
.sram(mux_tree_tapbuf_size2_5_sram[0:1]),
.sram_inv(mux_right_track_8_undriven_sram_inv[0:1]),
.out(chanx_right_out[4]));
mux_tree_tapbuf_size2 mux_right_track_10 (
.in({chany_top_in[4], right_bottom_grid_top_width_0_height_0_subtile_3__pin_inpad_0_}),
.sram(mux_tree_tapbuf_size2_6_sram[0:1]),
.sram_inv(mux_right_track_10_undriven_sram_inv[0:1]),
.out(chanx_right_out[5]));
mux_tree_tapbuf_size2 mux_right_track_12 (
.in({chany_top_in[5], right_bottom_grid_top_width_0_height_0_subtile_4__pin_inpad_0_}),
.sram(mux_tree_tapbuf_size2_7_sram[0:1]),
.sram_inv(mux_right_track_12_undriven_sram_inv[0:1]),
.out(chanx_right_out[6]));
mux_tree_tapbuf_size2 mux_right_track_14 (
.in({chany_top_in[6], right_bottom_grid_top_width_0_height_0_subtile_5__pin_inpad_0_}),
.sram(mux_tree_tapbuf_size2_8_sram[0:1]),
.sram_inv(mux_right_track_14_undriven_sram_inv[0:1]),
.out(chanx_right_out[7]));
mux_tree_tapbuf_size2 mux_right_track_16 (
.in({chany_top_in[7], right_bottom_grid_top_width_0_height_0_subtile_6__pin_inpad_0_}),
.sram(mux_tree_tapbuf_size2_9_sram[0:1]),
.sram_inv(mux_right_track_16_undriven_sram_inv[0:1]),
.out(chanx_right_out[8]));
mux_tree_tapbuf_size2 mux_right_track_18 (
.in({chany_top_in[8], right_bottom_grid_top_width_0_height_0_subtile_7__pin_inpad_0_}),
.sram(mux_tree_tapbuf_size2_10_sram[0:1]),
.sram_inv(mux_right_track_18_undriven_sram_inv[0:1]),
.out(chanx_right_out[9]));
mux_tree_tapbuf_size2 mux_right_track_20 (
.in({chany_top_in[9], right_bottom_grid_top_width_0_height_0_subtile_8__pin_inpad_0_}),
.sram(mux_tree_tapbuf_size2_11_sram[0:1]),
.sram_inv(mux_right_track_20_undriven_sram_inv[0:1]),
.out(chanx_right_out[10]));
mux_tree_tapbuf_size2_mem mem_top_track_0 (
.pReset(pReset),
.prog_clk(prog_clk),
.ccff_head(ccff_head),
.ccff_tail(mux_tree_tapbuf_size2_mem_0_ccff_tail),
.mem_out(mux_tree_tapbuf_size2_0_sram[0:1]));
mux_tree_tapbuf_size2_mem mem_top_track_2 (
.pReset(pReset),
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size2_mem_0_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size2_mem_1_ccff_tail),
.mem_out(mux_tree_tapbuf_size2_1_sram[0:1]));
mux_tree_tapbuf_size2_mem mem_top_track_4 (
.pReset(pReset),
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size2_mem_1_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size2_mem_2_ccff_tail),
.mem_out(mux_tree_tapbuf_size2_2_sram[0:1]));
mux_tree_tapbuf_size2_mem mem_right_track_4 (
.pReset(pReset),
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size10_mem_1_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size2_mem_3_ccff_tail),
.mem_out(mux_tree_tapbuf_size2_3_sram[0:1]));
mux_tree_tapbuf_size2_mem mem_right_track_6 (
.pReset(pReset),
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size2_mem_3_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size2_mem_4_ccff_tail),
.mem_out(mux_tree_tapbuf_size2_4_sram[0:1]));
mux_tree_tapbuf_size2_mem mem_right_track_8 (
.pReset(pReset),
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size2_mem_4_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size2_mem_5_ccff_tail),
.mem_out(mux_tree_tapbuf_size2_5_sram[0:1]));
mux_tree_tapbuf_size2_mem mem_right_track_10 (
.pReset(pReset),
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size2_mem_5_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size2_mem_6_ccff_tail),
.mem_out(mux_tree_tapbuf_size2_6_sram[0:1]));
mux_tree_tapbuf_size2_mem mem_right_track_12 (
.pReset(pReset),
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size2_mem_6_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size2_mem_7_ccff_tail),
.mem_out(mux_tree_tapbuf_size2_7_sram[0:1]));
mux_tree_tapbuf_size2_mem mem_right_track_14 (
.pReset(pReset),
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size2_mem_7_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size2_mem_8_ccff_tail),
.mem_out(mux_tree_tapbuf_size2_8_sram[0:1]));
mux_tree_tapbuf_size2_mem mem_right_track_16 (
.pReset(pReset),
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size2_mem_8_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size2_mem_9_ccff_tail),
.mem_out(mux_tree_tapbuf_size2_9_sram[0:1]));
mux_tree_tapbuf_size2_mem mem_right_track_18 (
.pReset(pReset),
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size2_mem_9_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size2_mem_10_ccff_tail),
.mem_out(mux_tree_tapbuf_size2_10_sram[0:1]));
mux_tree_tapbuf_size2_mem mem_right_track_20 (
.pReset(pReset),
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size2_mem_10_ccff_tail),
.ccff_tail(ccff_tail),
.mem_out(mux_tree_tapbuf_size2_11_sram[0:1]));
mux_tree_tapbuf_size10 mux_right_track_0 (
.in({chany_top_in[10], right_bottom_grid_top_width_0_height_0_subtile_0__pin_inpad_0_, right_bottom_grid_top_width_0_height_0_subtile_1__pin_inpad_0_, right_bottom_grid_top_width_0_height_0_subtile_2__pin_inpad_0_, right_bottom_grid_top_width_0_height_0_subtile_3__pin_inpad_0_, right_bottom_grid_top_width_0_height_0_subtile_4__pin_inpad_0_, right_bottom_grid_top_width_0_height_0_subtile_5__pin_inpad_0_, right_bottom_grid_top_width_0_height_0_subtile_6__pin_inpad_0_, right_bottom_grid_top_width_0_height_0_subtile_7__pin_inpad_0_, right_bottom_grid_top_width_0_height_0_subtile_8__pin_inpad_0_}),
.sram(mux_tree_tapbuf_size10_0_sram[0:3]),
.sram_inv(mux_right_track_0_undriven_sram_inv[0:3]),
.out(chanx_right_out[0]));
mux_tree_tapbuf_size10 mux_right_track_2 (
.in({chany_top_in[0], right_bottom_grid_top_width_0_height_0_subtile_0__pin_inpad_0_, right_bottom_grid_top_width_0_height_0_subtile_1__pin_inpad_0_, right_bottom_grid_top_width_0_height_0_subtile_2__pin_inpad_0_, right_bottom_grid_top_width_0_height_0_subtile_3__pin_inpad_0_, right_bottom_grid_top_width_0_height_0_subtile_4__pin_inpad_0_, right_bottom_grid_top_width_0_height_0_subtile_5__pin_inpad_0_, right_bottom_grid_top_width_0_height_0_subtile_6__pin_inpad_0_, right_bottom_grid_top_width_0_height_0_subtile_7__pin_inpad_0_, right_bottom_grid_top_width_0_height_0_subtile_8__pin_inpad_0_}),
.sram(mux_tree_tapbuf_size10_1_sram[0:3]),
.sram_inv(mux_right_track_2_undriven_sram_inv[0:3]),
.out(chanx_right_out[1]));
mux_tree_tapbuf_size10_mem mem_right_track_0 (
.pReset(pReset),
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size2_mem_2_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size10_mem_0_ccff_tail),
.mem_out(mux_tree_tapbuf_size10_0_sram[0:3]));
mux_tree_tapbuf_size10_mem mem_right_track_2 (
.pReset(pReset),
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size10_mem_0_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size10_mem_1_ccff_tail),
.mem_out(mux_tree_tapbuf_size10_1_sram[0:3]));
endmodule
// ----- END Verilog module for sb_0__0_ -----
//----- Default net type -----
`default_nettype none

367
SOFA_A/SOFA_A_verilog/routing/sb_0__1_.v Normal file
View File

@ -0,0 +1,367 @@
//-------------------------------------------
// FPGA Synthesizable Verilog Netlist
// Description: Verilog modules for Unique Switch Blocks[0][1]
// Author: Xifan TANG
// Organization: University of Utah
// Date: Sun Feb 19 10:53:27 2023
//-------------------------------------------
//----- Time scale -----
`timescale 1ns / 1ps
//----- Default net type -----
`default_nettype none
// ----- Verilog module for sb_0__1_ -----
module sb_0__1_(pReset,
prog_clk,
chanx_right_in,
right_top_grid_bottom_width_0_height_0_subtile_0__pin_inpad_0_,
right_top_grid_bottom_width_0_height_0_subtile_1__pin_inpad_0_,
right_top_grid_bottom_width_0_height_0_subtile_2__pin_inpad_0_,
right_top_grid_bottom_width_0_height_0_subtile_3__pin_inpad_0_,
right_top_grid_bottom_width_0_height_0_subtile_4__pin_inpad_0_,
right_top_grid_bottom_width_0_height_0_subtile_5__pin_inpad_0_,
right_top_grid_bottom_width_0_height_0_subtile_6__pin_inpad_0_,
right_top_grid_bottom_width_0_height_0_subtile_7__pin_inpad_0_,
right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_,
right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_,
right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_,
right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_,
right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_,
right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_,
right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_,
right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_,
chany_bottom_in,
bottom_left_grid_right_width_0_height_0_subtile_0__pin_inpad_0_,
ccff_head,
chanx_right_out,
chany_bottom_out,
ccff_tail);
//----- GLOBAL PORTS -----
input [0:0] pReset;
//----- GLOBAL PORTS -----
input [0:0] prog_clk;
//----- INPUT PORTS -----
input [0:10] chanx_right_in;
//----- INPUT PORTS -----
input [0:0] right_top_grid_bottom_width_0_height_0_subtile_0__pin_inpad_0_;
//----- INPUT PORTS -----
input [0:0] right_top_grid_bottom_width_0_height_0_subtile_1__pin_inpad_0_;
//----- INPUT PORTS -----
input [0:0] right_top_grid_bottom_width_0_height_0_subtile_2__pin_inpad_0_;
//----- INPUT PORTS -----
input [0:0] right_top_grid_bottom_width_0_height_0_subtile_3__pin_inpad_0_;
//----- INPUT PORTS -----
input [0:0] right_top_grid_bottom_width_0_height_0_subtile_4__pin_inpad_0_;
//----- INPUT PORTS -----
input [0:0] right_top_grid_bottom_width_0_height_0_subtile_5__pin_inpad_0_;
//----- INPUT PORTS -----
input [0:0] right_top_grid_bottom_width_0_height_0_subtile_6__pin_inpad_0_;
//----- INPUT PORTS -----
input [0:0] right_top_grid_bottom_width_0_height_0_subtile_7__pin_inpad_0_;
//----- INPUT PORTS -----
input [0:0] right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_;
//----- INPUT PORTS -----
input [0:0] right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_;
//----- INPUT PORTS -----
input [0:0] right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_;
//----- INPUT PORTS -----
input [0:0] right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_;
//----- INPUT PORTS -----
input [0:0] right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_;
//----- INPUT PORTS -----
input [0:0] right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_;
//----- INPUT PORTS -----
input [0:0] right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_;
//----- INPUT PORTS -----
input [0:0] right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_;
//----- INPUT PORTS -----
input [0:10] chany_bottom_in;
//----- INPUT PORTS -----
input [0:0] bottom_left_grid_right_width_0_height_0_subtile_0__pin_inpad_0_;
//----- INPUT PORTS -----
input [0:0] ccff_head;
//----- OUTPUT PORTS -----
output [0:10] chanx_right_out;
//----- OUTPUT PORTS -----
output [0:10] chany_bottom_out;
//----- OUTPUT PORTS -----
output [0:0] ccff_tail;
//----- BEGIN wire-connection ports -----
//----- END wire-connection ports -----
//----- BEGIN Registered ports -----
//----- END Registered ports -----
wire [0:1] mux_bottom_track_1_undriven_sram_inv;
wire [0:1] mux_bottom_track_3_undriven_sram_inv;
wire [0:1] mux_bottom_track_5_undriven_sram_inv;
wire [0:4] mux_right_track_0_undriven_sram_inv;
wire [0:1] mux_right_track_10_undriven_sram_inv;
wire [0:1] mux_right_track_12_undriven_sram_inv;
wire [0:1] mux_right_track_14_undriven_sram_inv;
wire [0:1] mux_right_track_16_undriven_sram_inv;
wire [0:1] mux_right_track_18_undriven_sram_inv;
wire [0:1] mux_right_track_20_undriven_sram_inv;
wire [0:4] mux_right_track_2_undriven_sram_inv;
wire [0:1] mux_right_track_4_undriven_sram_inv;
wire [0:1] mux_right_track_6_undriven_sram_inv;
wire [0:1] mux_right_track_8_undriven_sram_inv;
wire [0:4] mux_tree_tapbuf_size17_0_sram;
wire [0:4] mux_tree_tapbuf_size17_1_sram;
wire [0:0] mux_tree_tapbuf_size17_mem_0_ccff_tail;
wire [0:0] mux_tree_tapbuf_size17_mem_1_ccff_tail;
wire [0:1] mux_tree_tapbuf_size2_0_sram;
wire [0:1] mux_tree_tapbuf_size2_1_sram;
wire [0:1] mux_tree_tapbuf_size2_2_sram;
wire [0:1] mux_tree_tapbuf_size2_3_sram;
wire [0:1] mux_tree_tapbuf_size2_4_sram;
wire [0:0] mux_tree_tapbuf_size2_mem_0_ccff_tail;
wire [0:0] mux_tree_tapbuf_size2_mem_1_ccff_tail;
wire [0:0] mux_tree_tapbuf_size2_mem_2_ccff_tail;
wire [0:0] mux_tree_tapbuf_size2_mem_3_ccff_tail;
wire [0:1] mux_tree_tapbuf_size3_0_sram;
wire [0:1] mux_tree_tapbuf_size3_1_sram;
wire [0:1] mux_tree_tapbuf_size3_2_sram;
wire [0:1] mux_tree_tapbuf_size3_3_sram;
wire [0:1] mux_tree_tapbuf_size3_4_sram;
wire [0:1] mux_tree_tapbuf_size3_5_sram;
wire [0:1] mux_tree_tapbuf_size3_6_sram;
wire [0:0] mux_tree_tapbuf_size3_mem_0_ccff_tail;
wire [0:0] mux_tree_tapbuf_size3_mem_1_ccff_tail;
wire [0:0] mux_tree_tapbuf_size3_mem_2_ccff_tail;
wire [0:0] mux_tree_tapbuf_size3_mem_3_ccff_tail;
wire [0:0] mux_tree_tapbuf_size3_mem_4_ccff_tail;
wire [0:0] mux_tree_tapbuf_size3_mem_5_ccff_tail;
wire [0:0] mux_tree_tapbuf_size3_mem_6_ccff_tail;
// ----- BEGIN Local short connections -----
// ----- Local connection due to Wire 0 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chany_bottom_out[9] = chanx_right_in[0];
// ----- Local connection due to Wire 1 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chany_bottom_out[8] = chanx_right_in[1];
// ----- Local connection due to Wire 2 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chany_bottom_out[7] = chanx_right_in[2];
// ----- Local connection due to Wire 3 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chany_bottom_out[6] = chanx_right_in[3];
// ----- Local connection due to Wire 4 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chany_bottom_out[5] = chanx_right_in[4];
// ----- Local connection due to Wire 5 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chany_bottom_out[4] = chanx_right_in[5];
// ----- Local connection due to Wire 6 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chany_bottom_out[3] = chanx_right_in[6];
// ----- Local connection due to Wire 10 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chany_bottom_out[10] = chanx_right_in[10];
// ----- END Local short connections -----
// ----- BEGIN Local output short connections -----
// ----- END Local output short connections -----
mux_tree_tapbuf_size17 mux_right_track_0 (
.in({right_top_grid_bottom_width_0_height_0_subtile_0__pin_inpad_0_, right_top_grid_bottom_width_0_height_0_subtile_1__pin_inpad_0_, right_top_grid_bottom_width_0_height_0_subtile_2__pin_inpad_0_, right_top_grid_bottom_width_0_height_0_subtile_3__pin_inpad_0_, right_top_grid_bottom_width_0_height_0_subtile_4__pin_inpad_0_, right_top_grid_bottom_width_0_height_0_subtile_5__pin_inpad_0_, right_top_grid_bottom_width_0_height_0_subtile_6__pin_inpad_0_, right_top_grid_bottom_width_0_height_0_subtile_7__pin_inpad_0_, right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_, right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_, right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_, right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_, right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_, right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_, right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_, right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_, chany_bottom_in[9]}),
.sram(mux_tree_tapbuf_size17_0_sram[0:4]),
.sram_inv(mux_right_track_0_undriven_sram_inv[0:4]),
.out(chanx_right_out[0]));
mux_tree_tapbuf_size17 mux_right_track_2 (
.in({right_top_grid_bottom_width_0_height_0_subtile_0__pin_inpad_0_, right_top_grid_bottom_width_0_height_0_subtile_1__pin_inpad_0_, right_top_grid_bottom_width_0_height_0_subtile_2__pin_inpad_0_, right_top_grid_bottom_width_0_height_0_subtile_3__pin_inpad_0_, right_top_grid_bottom_width_0_height_0_subtile_4__pin_inpad_0_, right_top_grid_bottom_width_0_height_0_subtile_5__pin_inpad_0_, right_top_grid_bottom_width_0_height_0_subtile_6__pin_inpad_0_, right_top_grid_bottom_width_0_height_0_subtile_7__pin_inpad_0_, right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_, right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_, right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_, right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_, right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_, right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_, right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_, right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_, chany_bottom_in[8]}),
.sram(mux_tree_tapbuf_size17_1_sram[0:4]),
.sram_inv(mux_right_track_2_undriven_sram_inv[0:4]),
.out(chanx_right_out[1]));
mux_tree_tapbuf_size17_mem mem_right_track_0 (
.pReset(pReset),
.prog_clk(prog_clk),
.ccff_head(ccff_head),
.ccff_tail(mux_tree_tapbuf_size17_mem_0_ccff_tail),
.mem_out(mux_tree_tapbuf_size17_0_sram[0:4]));
mux_tree_tapbuf_size17_mem mem_right_track_2 (
.pReset(pReset),
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size17_mem_0_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size17_mem_1_ccff_tail),
.mem_out(mux_tree_tapbuf_size17_1_sram[0:4]));
mux_tree_tapbuf_size3 mux_right_track_4 (
.in({right_top_grid_bottom_width_0_height_0_subtile_0__pin_inpad_0_, right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_, chany_bottom_in[7]}),
.sram(mux_tree_tapbuf_size3_0_sram[0:1]),
.sram_inv(mux_right_track_4_undriven_sram_inv[0:1]),
.out(chanx_right_out[2]));
mux_tree_tapbuf_size3 mux_right_track_6 (
.in({right_top_grid_bottom_width_0_height_0_subtile_1__pin_inpad_0_, right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_, chany_bottom_in[6]}),
.sram(mux_tree_tapbuf_size3_1_sram[0:1]),
.sram_inv(mux_right_track_6_undriven_sram_inv[0:1]),
.out(chanx_right_out[3]));
mux_tree_tapbuf_size3 mux_right_track_8 (
.in({right_top_grid_bottom_width_0_height_0_subtile_2__pin_inpad_0_, right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_, chany_bottom_in[5]}),
.sram(mux_tree_tapbuf_size3_2_sram[0:1]),
.sram_inv(mux_right_track_8_undriven_sram_inv[0:1]),
.out(chanx_right_out[4]));
mux_tree_tapbuf_size3 mux_right_track_10 (
.in({right_top_grid_bottom_width_0_height_0_subtile_3__pin_inpad_0_, right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_, chany_bottom_in[4]}),
.sram(mux_tree_tapbuf_size3_3_sram[0:1]),
.sram_inv(mux_right_track_10_undriven_sram_inv[0:1]),
.out(chanx_right_out[5]));
mux_tree_tapbuf_size3 mux_right_track_12 (
.in({right_top_grid_bottom_width_0_height_0_subtile_4__pin_inpad_0_, right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_, chany_bottom_in[3]}),
.sram(mux_tree_tapbuf_size3_4_sram[0:1]),
.sram_inv(mux_right_track_12_undriven_sram_inv[0:1]),
.out(chanx_right_out[6]));
mux_tree_tapbuf_size3 mux_right_track_14 (
.in({right_top_grid_bottom_width_0_height_0_subtile_5__pin_inpad_0_, right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_, chany_bottom_in[2]}),
.sram(mux_tree_tapbuf_size3_5_sram[0:1]),
.sram_inv(mux_right_track_14_undriven_sram_inv[0:1]),
.out(chanx_right_out[7]));
mux_tree_tapbuf_size3 mux_right_track_16 (
.in({right_top_grid_bottom_width_0_height_0_subtile_6__pin_inpad_0_, right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_, chany_bottom_in[1]}),
.sram(mux_tree_tapbuf_size3_6_sram[0:1]),
.sram_inv(mux_right_track_16_undriven_sram_inv[0:1]),
.out(chanx_right_out[8]));
mux_tree_tapbuf_size3_mem mem_right_track_4 (
.pReset(pReset),
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size17_mem_1_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size3_mem_0_ccff_tail),
.mem_out(mux_tree_tapbuf_size3_0_sram[0:1]));
mux_tree_tapbuf_size3_mem mem_right_track_6 (
.pReset(pReset),
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size3_mem_0_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size3_mem_1_ccff_tail),
.mem_out(mux_tree_tapbuf_size3_1_sram[0:1]));
mux_tree_tapbuf_size3_mem mem_right_track_8 (
.pReset(pReset),
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size3_mem_1_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size3_mem_2_ccff_tail),
.mem_out(mux_tree_tapbuf_size3_2_sram[0:1]));
mux_tree_tapbuf_size3_mem mem_right_track_10 (
.pReset(pReset),
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size3_mem_2_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size3_mem_3_ccff_tail),
.mem_out(mux_tree_tapbuf_size3_3_sram[0:1]));
mux_tree_tapbuf_size3_mem mem_right_track_12 (
.pReset(pReset),
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size3_mem_3_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size3_mem_4_ccff_tail),
.mem_out(mux_tree_tapbuf_size3_4_sram[0:1]));
mux_tree_tapbuf_size3_mem mem_right_track_14 (
.pReset(pReset),
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size3_mem_4_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size3_mem_5_ccff_tail),
.mem_out(mux_tree_tapbuf_size3_5_sram[0:1]));
mux_tree_tapbuf_size3_mem mem_right_track_16 (
.pReset(pReset),
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size3_mem_5_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size3_mem_6_ccff_tail),
.mem_out(mux_tree_tapbuf_size3_6_sram[0:1]));
mux_tree_tapbuf_size2 mux_right_track_18 (
.in({right_top_grid_bottom_width_0_height_0_subtile_7__pin_inpad_0_, chany_bottom_in[0]}),
.sram(mux_tree_tapbuf_size2_0_sram[0:1]),
.sram_inv(mux_right_track_18_undriven_sram_inv[0:1]),
.out(chanx_right_out[9]));
mux_tree_tapbuf_size2 mux_right_track_20 (
.in({right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_, chany_bottom_in[10]}),
.sram(mux_tree_tapbuf_size2_1_sram[0:1]),
.sram_inv(mux_right_track_20_undriven_sram_inv[0:1]),
.out(chanx_right_out[10]));
mux_tree_tapbuf_size2 mux_bottom_track_1 (
.in({chanx_right_in[9], bottom_left_grid_right_width_0_height_0_subtile_0__pin_inpad_0_}),
.sram(mux_tree_tapbuf_size2_2_sram[0:1]),
.sram_inv(mux_bottom_track_1_undriven_sram_inv[0:1]),
.out(chany_bottom_out[0]));
mux_tree_tapbuf_size2 mux_bottom_track_3 (
.in({chanx_right_in[8], bottom_left_grid_right_width_0_height_0_subtile_0__pin_inpad_0_}),
.sram(mux_tree_tapbuf_size2_3_sram[0:1]),
.sram_inv(mux_bottom_track_3_undriven_sram_inv[0:1]),
.out(chany_bottom_out[1]));
mux_tree_tapbuf_size2 mux_bottom_track_5 (
.in({chanx_right_in[7], bottom_left_grid_right_width_0_height_0_subtile_0__pin_inpad_0_}),
.sram(mux_tree_tapbuf_size2_4_sram[0:1]),
.sram_inv(mux_bottom_track_5_undriven_sram_inv[0:1]),
.out(chany_bottom_out[2]));
mux_tree_tapbuf_size2_mem mem_right_track_18 (
.pReset(pReset),
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size3_mem_6_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size2_mem_0_ccff_tail),
.mem_out(mux_tree_tapbuf_size2_0_sram[0:1]));
mux_tree_tapbuf_size2_mem mem_right_track_20 (
.pReset(pReset),
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size2_mem_0_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size2_mem_1_ccff_tail),
.mem_out(mux_tree_tapbuf_size2_1_sram[0:1]));
mux_tree_tapbuf_size2_mem mem_bottom_track_1 (
.pReset(pReset),
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size2_mem_1_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size2_mem_2_ccff_tail),
.mem_out(mux_tree_tapbuf_size2_2_sram[0:1]));
mux_tree_tapbuf_size2_mem mem_bottom_track_3 (
.pReset(pReset),
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size2_mem_2_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size2_mem_3_ccff_tail),
.mem_out(mux_tree_tapbuf_size2_3_sram[0:1]));
mux_tree_tapbuf_size2_mem mem_bottom_track_5 (
.pReset(pReset),
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size2_mem_3_ccff_tail),
.ccff_tail(ccff_tail),
.mem_out(mux_tree_tapbuf_size2_4_sram[0:1]));
endmodule
// ----- END Verilog module for sb_0__1_ -----
//----- Default net type -----
`default_nettype none

484
SOFA_A/SOFA_A_verilog/routing/sb_1__0_.v Normal file
View File

@ -0,0 +1,484 @@
//-------------------------------------------
// FPGA Synthesizable Verilog Netlist
// Description: Verilog modules for Unique Switch Blocks[1][0]
// Author: Xifan TANG
// Organization: University of Utah
// Date: Sun Feb 19 10:53:27 2023
//-------------------------------------------
//----- Time scale -----
`timescale 1ns / 1ps
//----- Default net type -----
`default_nettype none
// ----- Verilog module for sb_1__0_ -----
module sb_1__0_(pReset,
prog_clk,
chany_top_in,
top_left_grid_right_width_0_height_0_subtile_0__pin_O_8_,
top_left_grid_right_width_0_height_0_subtile_0__pin_O_9_,
top_left_grid_right_width_0_height_0_subtile_0__pin_O_10_,
top_left_grid_right_width_0_height_0_subtile_0__pin_O_11_,
top_left_grid_right_width_0_height_0_subtile_0__pin_O_12_,
top_left_grid_right_width_0_height_0_subtile_0__pin_O_13_,
top_left_grid_right_width_0_height_0_subtile_0__pin_O_14_,
top_right_grid_left_width_0_height_0_subtile_0__pin_inpad_0_,
top_right_grid_left_width_0_height_0_subtile_1__pin_inpad_0_,
top_right_grid_left_width_0_height_0_subtile_2__pin_inpad_0_,
top_right_grid_left_width_0_height_0_subtile_3__pin_inpad_0_,
top_right_grid_left_width_0_height_0_subtile_4__pin_inpad_0_,
top_right_grid_left_width_0_height_0_subtile_5__pin_inpad_0_,
top_right_grid_left_width_0_height_0_subtile_6__pin_inpad_0_,
top_right_grid_left_width_0_height_0_subtile_7__pin_inpad_0_,
chanx_left_in,
left_bottom_grid_top_width_0_height_0_subtile_0__pin_inpad_0_,
left_bottom_grid_top_width_0_height_0_subtile_1__pin_inpad_0_,
left_bottom_grid_top_width_0_height_0_subtile_2__pin_inpad_0_,
left_bottom_grid_top_width_0_height_0_subtile_3__pin_inpad_0_,
left_bottom_grid_top_width_0_height_0_subtile_4__pin_inpad_0_,
left_bottom_grid_top_width_0_height_0_subtile_5__pin_inpad_0_,
left_bottom_grid_top_width_0_height_0_subtile_6__pin_inpad_0_,
left_bottom_grid_top_width_0_height_0_subtile_7__pin_inpad_0_,
left_bottom_grid_top_width_0_height_0_subtile_8__pin_inpad_0_,
ccff_head,
chany_top_out,
chanx_left_out,
ccff_tail);
//----- GLOBAL PORTS -----
input [0:0] pReset;
//----- GLOBAL PORTS -----
input [0:0] prog_clk;
//----- INPUT PORTS -----
input [0:10] chany_top_in;
//----- INPUT PORTS -----
input [0:0] top_left_grid_right_width_0_height_0_subtile_0__pin_O_8_;
//----- INPUT PORTS -----
input [0:0] top_left_grid_right_width_0_height_0_subtile_0__pin_O_9_;
//----- INPUT PORTS -----
input [0:0] top_left_grid_right_width_0_height_0_subtile_0__pin_O_10_;
//----- INPUT PORTS -----
input [0:0] top_left_grid_right_width_0_height_0_subtile_0__pin_O_11_;
//----- INPUT PORTS -----
input [0:0] top_left_grid_right_width_0_height_0_subtile_0__pin_O_12_;
//----- INPUT PORTS -----
input [0:0] top_left_grid_right_width_0_height_0_subtile_0__pin_O_13_;
//----- INPUT PORTS -----
input [0:0] top_left_grid_right_width_0_height_0_subtile_0__pin_O_14_;
//----- INPUT PORTS -----
input [0:0] top_right_grid_left_width_0_height_0_subtile_0__pin_inpad_0_;
//----- INPUT PORTS -----
input [0:0] top_right_grid_left_width_0_height_0_subtile_1__pin_inpad_0_;
//----- INPUT PORTS -----
input [0:0] top_right_grid_left_width_0_height_0_subtile_2__pin_inpad_0_;
//----- INPUT PORTS -----
input [0:0] top_right_grid_left_width_0_height_0_subtile_3__pin_inpad_0_;
//----- INPUT PORTS -----
input [0:0] top_right_grid_left_width_0_height_0_subtile_4__pin_inpad_0_;
//----- INPUT PORTS -----
input [0:0] top_right_grid_left_width_0_height_0_subtile_5__pin_inpad_0_;
//----- INPUT PORTS -----
input [0:0] top_right_grid_left_width_0_height_0_subtile_6__pin_inpad_0_;
//----- INPUT PORTS -----
input [0:0] top_right_grid_left_width_0_height_0_subtile_7__pin_inpad_0_;
//----- INPUT PORTS -----
input [0:10] chanx_left_in;
//----- INPUT PORTS -----
input [0:0] left_bottom_grid_top_width_0_height_0_subtile_0__pin_inpad_0_;
//----- INPUT PORTS -----
input [0:0] left_bottom_grid_top_width_0_height_0_subtile_1__pin_inpad_0_;
//----- INPUT PORTS -----
input [0:0] left_bottom_grid_top_width_0_height_0_subtile_2__pin_inpad_0_;
//----- INPUT PORTS -----
input [0:0] left_bottom_grid_top_width_0_height_0_subtile_3__pin_inpad_0_;
//----- INPUT PORTS -----
input [0:0] left_bottom_grid_top_width_0_height_0_subtile_4__pin_inpad_0_;
//----- INPUT PORTS -----
input [0:0] left_bottom_grid_top_width_0_height_0_subtile_5__pin_inpad_0_;
//----- INPUT PORTS -----
input [0:0] left_bottom_grid_top_width_0_height_0_subtile_6__pin_inpad_0_;
//----- INPUT PORTS -----
input [0:0] left_bottom_grid_top_width_0_height_0_subtile_7__pin_inpad_0_;
//----- INPUT PORTS -----
input [0:0] left_bottom_grid_top_width_0_height_0_subtile_8__pin_inpad_0_;
//----- INPUT PORTS -----
input [0:0] ccff_head;
//----- OUTPUT PORTS -----
output [0:10] chany_top_out;
//----- OUTPUT PORTS -----
output [0:10] chanx_left_out;
//----- OUTPUT PORTS -----
output [0:0] ccff_tail;
//----- BEGIN wire-connection ports -----
//----- END wire-connection ports -----
//----- BEGIN Registered ports -----
//----- END Registered ports -----
wire [0:1] mux_left_track_11_undriven_sram_inv;
wire [0:1] mux_left_track_13_undriven_sram_inv;
wire [0:1] mux_left_track_15_undriven_sram_inv;
wire [0:1] mux_left_track_17_undriven_sram_inv;
wire [0:1] mux_left_track_19_undriven_sram_inv;
wire [0:3] mux_left_track_1_undriven_sram_inv;
wire [0:1] mux_left_track_21_undriven_sram_inv;
wire [0:3] mux_left_track_3_undriven_sram_inv;
wire [0:1] mux_left_track_5_undriven_sram_inv;
wire [0:1] mux_left_track_7_undriven_sram_inv;
wire [0:1] mux_left_track_9_undriven_sram_inv;
wire [0:4] mux_top_track_0_undriven_sram_inv;
wire [0:1] mux_top_track_10_undriven_sram_inv;
wire [0:1] mux_top_track_12_undriven_sram_inv;
wire [0:1] mux_top_track_14_undriven_sram_inv;
wire [0:1] mux_top_track_16_undriven_sram_inv;
wire [0:1] mux_top_track_18_undriven_sram_inv;
wire [0:1] mux_top_track_20_undriven_sram_inv;
wire [0:4] mux_top_track_2_undriven_sram_inv;
wire [0:1] mux_top_track_4_undriven_sram_inv;
wire [0:1] mux_top_track_6_undriven_sram_inv;
wire [0:1] mux_top_track_8_undriven_sram_inv;
wire [0:3] mux_tree_tapbuf_size10_0_sram;
wire [0:3] mux_tree_tapbuf_size10_1_sram;
wire [0:0] mux_tree_tapbuf_size10_mem_0_ccff_tail;
wire [0:0] mux_tree_tapbuf_size10_mem_1_ccff_tail;
wire [0:4] mux_tree_tapbuf_size16_0_sram;
wire [0:4] mux_tree_tapbuf_size16_1_sram;
wire [0:0] mux_tree_tapbuf_size16_mem_0_ccff_tail;
wire [0:0] mux_tree_tapbuf_size16_mem_1_ccff_tail;
wire [0:1] mux_tree_tapbuf_size2_0_sram;
wire [0:1] mux_tree_tapbuf_size2_10_sram;
wire [0:1] mux_tree_tapbuf_size2_11_sram;
wire [0:1] mux_tree_tapbuf_size2_1_sram;
wire [0:1] mux_tree_tapbuf_size2_2_sram;
wire [0:1] mux_tree_tapbuf_size2_3_sram;
wire [0:1] mux_tree_tapbuf_size2_4_sram;
wire [0:1] mux_tree_tapbuf_size2_5_sram;
wire [0:1] mux_tree_tapbuf_size2_6_sram;
wire [0:1] mux_tree_tapbuf_size2_7_sram;
wire [0:1] mux_tree_tapbuf_size2_8_sram;
wire [0:1] mux_tree_tapbuf_size2_9_sram;
wire [0:0] mux_tree_tapbuf_size2_mem_0_ccff_tail;
wire [0:0] mux_tree_tapbuf_size2_mem_10_ccff_tail;
wire [0:0] mux_tree_tapbuf_size2_mem_1_ccff_tail;
wire [0:0] mux_tree_tapbuf_size2_mem_2_ccff_tail;
wire [0:0] mux_tree_tapbuf_size2_mem_3_ccff_tail;
wire [0:0] mux_tree_tapbuf_size2_mem_4_ccff_tail;
wire [0:0] mux_tree_tapbuf_size2_mem_5_ccff_tail;
wire [0:0] mux_tree_tapbuf_size2_mem_6_ccff_tail;
wire [0:0] mux_tree_tapbuf_size2_mem_7_ccff_tail;
wire [0:0] mux_tree_tapbuf_size2_mem_8_ccff_tail;
wire [0:0] mux_tree_tapbuf_size2_mem_9_ccff_tail;
wire [0:1] mux_tree_tapbuf_size3_0_sram;
wire [0:1] mux_tree_tapbuf_size3_1_sram;
wire [0:1] mux_tree_tapbuf_size3_2_sram;
wire [0:1] mux_tree_tapbuf_size3_3_sram;
wire [0:1] mux_tree_tapbuf_size3_4_sram;
wire [0:1] mux_tree_tapbuf_size3_5_sram;
wire [0:0] mux_tree_tapbuf_size3_mem_0_ccff_tail;
wire [0:0] mux_tree_tapbuf_size3_mem_1_ccff_tail;
wire [0:0] mux_tree_tapbuf_size3_mem_2_ccff_tail;
wire [0:0] mux_tree_tapbuf_size3_mem_3_ccff_tail;
wire [0:0] mux_tree_tapbuf_size3_mem_4_ccff_tail;
wire [0:0] mux_tree_tapbuf_size3_mem_5_ccff_tail;
// ----- BEGIN Local short connections -----
// ----- END Local short connections -----
// ----- BEGIN Local output short connections -----
// ----- END Local output short connections -----
mux_tree_tapbuf_size16 mux_top_track_0 (
.in({top_left_grid_right_width_0_height_0_subtile_0__pin_O_8_, top_left_grid_right_width_0_height_0_subtile_0__pin_O_9_, top_left_grid_right_width_0_height_0_subtile_0__pin_O_10_, top_left_grid_right_width_0_height_0_subtile_0__pin_O_11_, top_left_grid_right_width_0_height_0_subtile_0__pin_O_12_, top_left_grid_right_width_0_height_0_subtile_0__pin_O_13_, top_left_grid_right_width_0_height_0_subtile_0__pin_O_14_, top_right_grid_left_width_0_height_0_subtile_0__pin_inpad_0_, top_right_grid_left_width_0_height_0_subtile_1__pin_inpad_0_, top_right_grid_left_width_0_height_0_subtile_2__pin_inpad_0_, top_right_grid_left_width_0_height_0_subtile_3__pin_inpad_0_, top_right_grid_left_width_0_height_0_subtile_4__pin_inpad_0_, top_right_grid_left_width_0_height_0_subtile_5__pin_inpad_0_, top_right_grid_left_width_0_height_0_subtile_6__pin_inpad_0_, top_right_grid_left_width_0_height_0_subtile_7__pin_inpad_0_, chanx_left_in[0]}),
.sram(mux_tree_tapbuf_size16_0_sram[0:4]),
.sram_inv(mux_top_track_0_undriven_sram_inv[0:4]),
.out(chany_top_out[0]));
mux_tree_tapbuf_size16 mux_top_track_2 (
.in({top_left_grid_right_width_0_height_0_subtile_0__pin_O_8_, top_left_grid_right_width_0_height_0_subtile_0__pin_O_9_, top_left_grid_right_width_0_height_0_subtile_0__pin_O_10_, top_left_grid_right_width_0_height_0_subtile_0__pin_O_11_, top_left_grid_right_width_0_height_0_subtile_0__pin_O_12_, top_left_grid_right_width_0_height_0_subtile_0__pin_O_13_, top_left_grid_right_width_0_height_0_subtile_0__pin_O_14_, top_right_grid_left_width_0_height_0_subtile_0__pin_inpad_0_, top_right_grid_left_width_0_height_0_subtile_1__pin_inpad_0_, top_right_grid_left_width_0_height_0_subtile_2__pin_inpad_0_, top_right_grid_left_width_0_height_0_subtile_3__pin_inpad_0_, top_right_grid_left_width_0_height_0_subtile_4__pin_inpad_0_, top_right_grid_left_width_0_height_0_subtile_5__pin_inpad_0_, top_right_grid_left_width_0_height_0_subtile_6__pin_inpad_0_, top_right_grid_left_width_0_height_0_subtile_7__pin_inpad_0_, chanx_left_in[10]}),
.sram(mux_tree_tapbuf_size16_1_sram[0:4]),
.sram_inv(mux_top_track_2_undriven_sram_inv[0:4]),
.out(chany_top_out[1]));
mux_tree_tapbuf_size16_mem mem_top_track_0 (
.pReset(pReset),
.prog_clk(prog_clk),
.ccff_head(ccff_head),
.ccff_tail(mux_tree_tapbuf_size16_mem_0_ccff_tail),
.mem_out(mux_tree_tapbuf_size16_0_sram[0:4]));
mux_tree_tapbuf_size16_mem mem_top_track_2 (
.pReset(pReset),
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size16_mem_0_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size16_mem_1_ccff_tail),
.mem_out(mux_tree_tapbuf_size16_1_sram[0:4]));
mux_tree_tapbuf_size3 mux_top_track_4 (
.in({top_left_grid_right_width_0_height_0_subtile_0__pin_O_8_, top_right_grid_left_width_0_height_0_subtile_2__pin_inpad_0_, chanx_left_in[9]}),
.sram(mux_tree_tapbuf_size3_0_sram[0:1]),
.sram_inv(mux_top_track_4_undriven_sram_inv[0:1]),
.out(chany_top_out[2]));
mux_tree_tapbuf_size3 mux_top_track_6 (
.in({top_left_grid_right_width_0_height_0_subtile_0__pin_O_9_, top_right_grid_left_width_0_height_0_subtile_3__pin_inpad_0_, chanx_left_in[8]}),
.sram(mux_tree_tapbuf_size3_1_sram[0:1]),
.sram_inv(mux_top_track_6_undriven_sram_inv[0:1]),
.out(chany_top_out[3]));
mux_tree_tapbuf_size3 mux_top_track_8 (
.in({top_left_grid_right_width_0_height_0_subtile_0__pin_O_10_, top_right_grid_left_width_0_height_0_subtile_4__pin_inpad_0_, chanx_left_in[7]}),
.sram(mux_tree_tapbuf_size3_2_sram[0:1]),
.sram_inv(mux_top_track_8_undriven_sram_inv[0:1]),
.out(chany_top_out[4]));
mux_tree_tapbuf_size3 mux_top_track_10 (
.in({top_left_grid_right_width_0_height_0_subtile_0__pin_O_11_, top_right_grid_left_width_0_height_0_subtile_5__pin_inpad_0_, chanx_left_in[6]}),
.sram(mux_tree_tapbuf_size3_3_sram[0:1]),
.sram_inv(mux_top_track_10_undriven_sram_inv[0:1]),
.out(chany_top_out[5]));
mux_tree_tapbuf_size3 mux_top_track_12 (
.in({top_left_grid_right_width_0_height_0_subtile_0__pin_O_12_, top_right_grid_left_width_0_height_0_subtile_6__pin_inpad_0_, chanx_left_in[5]}),
.sram(mux_tree_tapbuf_size3_4_sram[0:1]),
.sram_inv(mux_top_track_12_undriven_sram_inv[0:1]),
.out(chany_top_out[6]));
mux_tree_tapbuf_size3 mux_top_track_14 (
.in({top_left_grid_right_width_0_height_0_subtile_0__pin_O_13_, top_right_grid_left_width_0_height_0_subtile_7__pin_inpad_0_, chanx_left_in[4]}),
.sram(mux_tree_tapbuf_size3_5_sram[0:1]),
.sram_inv(mux_top_track_14_undriven_sram_inv[0:1]),
.out(chany_top_out[7]));
mux_tree_tapbuf_size3_mem mem_top_track_4 (
.pReset(pReset),
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size16_mem_1_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size3_mem_0_ccff_tail),
.mem_out(mux_tree_tapbuf_size3_0_sram[0:1]));
mux_tree_tapbuf_size3_mem mem_top_track_6 (
.pReset(pReset),
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size3_mem_0_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size3_mem_1_ccff_tail),
.mem_out(mux_tree_tapbuf_size3_1_sram[0:1]));
mux_tree_tapbuf_size3_mem mem_top_track_8 (
.pReset(pReset),
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size3_mem_1_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size3_mem_2_ccff_tail),
.mem_out(mux_tree_tapbuf_size3_2_sram[0:1]));
mux_tree_tapbuf_size3_mem mem_top_track_10 (
.pReset(pReset),
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size3_mem_2_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size3_mem_3_ccff_tail),
.mem_out(mux_tree_tapbuf_size3_3_sram[0:1]));
mux_tree_tapbuf_size3_mem mem_top_track_12 (
.pReset(pReset),
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size3_mem_3_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size3_mem_4_ccff_tail),
.mem_out(mux_tree_tapbuf_size3_4_sram[0:1]));
mux_tree_tapbuf_size3_mem mem_top_track_14 (
.pReset(pReset),
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size3_mem_4_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size3_mem_5_ccff_tail),
.mem_out(mux_tree_tapbuf_size3_5_sram[0:1]));
mux_tree_tapbuf_size2 mux_top_track_16 (
.in({top_left_grid_right_width_0_height_0_subtile_0__pin_O_14_, chanx_left_in[3]}),
.sram(mux_tree_tapbuf_size2_0_sram[0:1]),
.sram_inv(mux_top_track_16_undriven_sram_inv[0:1]),
.out(chany_top_out[8]));
mux_tree_tapbuf_size2 mux_top_track_18 (
.in({top_right_grid_left_width_0_height_0_subtile_0__pin_inpad_0_, chanx_left_in[2]}),
.sram(mux_tree_tapbuf_size2_1_sram[0:1]),
.sram_inv(mux_top_track_18_undriven_sram_inv[0:1]),
.out(chany_top_out[9]));
mux_tree_tapbuf_size2 mux_top_track_20 (
.in({top_right_grid_left_width_0_height_0_subtile_1__pin_inpad_0_, chanx_left_in[1]}),
.sram(mux_tree_tapbuf_size2_2_sram[0:1]),
.sram_inv(mux_top_track_20_undriven_sram_inv[0:1]),
.out(chany_top_out[10]));
mux_tree_tapbuf_size2 mux_left_track_5 (
.in({chany_top_in[9], left_bottom_grid_top_width_0_height_0_subtile_0__pin_inpad_0_}),
.sram(mux_tree_tapbuf_size2_3_sram[0:1]),
.sram_inv(mux_left_track_5_undriven_sram_inv[0:1]),
.out(chanx_left_out[2]));
mux_tree_tapbuf_size2 mux_left_track_7 (
.in({chany_top_in[8], left_bottom_grid_top_width_0_height_0_subtile_1__pin_inpad_0_}),
.sram(mux_tree_tapbuf_size2_4_sram[0:1]),
.sram_inv(mux_left_track_7_undriven_sram_inv[0:1]),
.out(chanx_left_out[3]));
mux_tree_tapbuf_size2 mux_left_track_9 (
.in({chany_top_in[7], left_bottom_grid_top_width_0_height_0_subtile_2__pin_inpad_0_}),
.sram(mux_tree_tapbuf_size2_5_sram[0:1]),
.sram_inv(mux_left_track_9_undriven_sram_inv[0:1]),
.out(chanx_left_out[4]));
mux_tree_tapbuf_size2 mux_left_track_11 (
.in({chany_top_in[6], left_bottom_grid_top_width_0_height_0_subtile_3__pin_inpad_0_}),
.sram(mux_tree_tapbuf_size2_6_sram[0:1]),
.sram_inv(mux_left_track_11_undriven_sram_inv[0:1]),
.out(chanx_left_out[5]));
mux_tree_tapbuf_size2 mux_left_track_13 (
.in({chany_top_in[5], left_bottom_grid_top_width_0_height_0_subtile_4__pin_inpad_0_}),
.sram(mux_tree_tapbuf_size2_7_sram[0:1]),
.sram_inv(mux_left_track_13_undriven_sram_inv[0:1]),
.out(chanx_left_out[6]));
mux_tree_tapbuf_size2 mux_left_track_15 (
.in({chany_top_in[4], left_bottom_grid_top_width_0_height_0_subtile_5__pin_inpad_0_}),
.sram(mux_tree_tapbuf_size2_8_sram[0:1]),
.sram_inv(mux_left_track_15_undriven_sram_inv[0:1]),
.out(chanx_left_out[7]));
mux_tree_tapbuf_size2 mux_left_track_17 (
.in({chany_top_in[3], left_bottom_grid_top_width_0_height_0_subtile_6__pin_inpad_0_}),
.sram(mux_tree_tapbuf_size2_9_sram[0:1]),
.sram_inv(mux_left_track_17_undriven_sram_inv[0:1]),
.out(chanx_left_out[8]));
mux_tree_tapbuf_size2 mux_left_track_19 (
.in({chany_top_in[2], left_bottom_grid_top_width_0_height_0_subtile_7__pin_inpad_0_}),
.sram(mux_tree_tapbuf_size2_10_sram[0:1]),
.sram_inv(mux_left_track_19_undriven_sram_inv[0:1]),
.out(chanx_left_out[9]));
mux_tree_tapbuf_size2 mux_left_track_21 (
.in({chany_top_in[1], left_bottom_grid_top_width_0_height_0_subtile_8__pin_inpad_0_}),
.sram(mux_tree_tapbuf_size2_11_sram[0:1]),
.sram_inv(mux_left_track_21_undriven_sram_inv[0:1]),
.out(chanx_left_out[10]));
mux_tree_tapbuf_size2_mem mem_top_track_16 (
.pReset(pReset),
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size3_mem_5_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size2_mem_0_ccff_tail),
.mem_out(mux_tree_tapbuf_size2_0_sram[0:1]));
mux_tree_tapbuf_size2_mem mem_top_track_18 (
.pReset(pReset),
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size2_mem_0_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size2_mem_1_ccff_tail),
.mem_out(mux_tree_tapbuf_size2_1_sram[0:1]));
mux_tree_tapbuf_size2_mem mem_top_track_20 (
.pReset(pReset),
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size2_mem_1_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size2_mem_2_ccff_tail),
.mem_out(mux_tree_tapbuf_size2_2_sram[0:1]));
mux_tree_tapbuf_size2_mem mem_left_track_5 (
.pReset(pReset),
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size10_mem_1_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size2_mem_3_ccff_tail),
.mem_out(mux_tree_tapbuf_size2_3_sram[0:1]));
mux_tree_tapbuf_size2_mem mem_left_track_7 (
.pReset(pReset),
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size2_mem_3_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size2_mem_4_ccff_tail),
.mem_out(mux_tree_tapbuf_size2_4_sram[0:1]));
mux_tree_tapbuf_size2_mem mem_left_track_9 (
.pReset(pReset),
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size2_mem_4_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size2_mem_5_ccff_tail),
.mem_out(mux_tree_tapbuf_size2_5_sram[0:1]));
mux_tree_tapbuf_size2_mem mem_left_track_11 (
.pReset(pReset),
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size2_mem_5_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size2_mem_6_ccff_tail),
.mem_out(mux_tree_tapbuf_size2_6_sram[0:1]));
mux_tree_tapbuf_size2_mem mem_left_track_13 (
.pReset(pReset),
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size2_mem_6_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size2_mem_7_ccff_tail),
.mem_out(mux_tree_tapbuf_size2_7_sram[0:1]));
mux_tree_tapbuf_size2_mem mem_left_track_15 (
.pReset(pReset),
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size2_mem_7_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size2_mem_8_ccff_tail),
.mem_out(mux_tree_tapbuf_size2_8_sram[0:1]));
mux_tree_tapbuf_size2_mem mem_left_track_17 (
.pReset(pReset),
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size2_mem_8_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size2_mem_9_ccff_tail),
.mem_out(mux_tree_tapbuf_size2_9_sram[0:1]));
mux_tree_tapbuf_size2_mem mem_left_track_19 (
.pReset(pReset),
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size2_mem_9_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size2_mem_10_ccff_tail),
.mem_out(mux_tree_tapbuf_size2_10_sram[0:1]));
mux_tree_tapbuf_size2_mem mem_left_track_21 (
.pReset(pReset),
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size2_mem_10_ccff_tail),
.ccff_tail(ccff_tail),
.mem_out(mux_tree_tapbuf_size2_11_sram[0:1]));
mux_tree_tapbuf_size10 mux_left_track_1 (
.in({chany_top_in[0], left_bottom_grid_top_width_0_height_0_subtile_0__pin_inpad_0_, left_bottom_grid_top_width_0_height_0_subtile_1__pin_inpad_0_, left_bottom_grid_top_width_0_height_0_subtile_2__pin_inpad_0_, left_bottom_grid_top_width_0_height_0_subtile_3__pin_inpad_0_, left_bottom_grid_top_width_0_height_0_subtile_4__pin_inpad_0_, left_bottom_grid_top_width_0_height_0_subtile_5__pin_inpad_0_, left_bottom_grid_top_width_0_height_0_subtile_6__pin_inpad_0_, left_bottom_grid_top_width_0_height_0_subtile_7__pin_inpad_0_, left_bottom_grid_top_width_0_height_0_subtile_8__pin_inpad_0_}),
.sram(mux_tree_tapbuf_size10_0_sram[0:3]),
.sram_inv(mux_left_track_1_undriven_sram_inv[0:3]),
.out(chanx_left_out[0]));
mux_tree_tapbuf_size10 mux_left_track_3 (
.in({chany_top_in[10], left_bottom_grid_top_width_0_height_0_subtile_0__pin_inpad_0_, left_bottom_grid_top_width_0_height_0_subtile_1__pin_inpad_0_, left_bottom_grid_top_width_0_height_0_subtile_2__pin_inpad_0_, left_bottom_grid_top_width_0_height_0_subtile_3__pin_inpad_0_, left_bottom_grid_top_width_0_height_0_subtile_4__pin_inpad_0_, left_bottom_grid_top_width_0_height_0_subtile_5__pin_inpad_0_, left_bottom_grid_top_width_0_height_0_subtile_6__pin_inpad_0_, left_bottom_grid_top_width_0_height_0_subtile_7__pin_inpad_0_, left_bottom_grid_top_width_0_height_0_subtile_8__pin_inpad_0_}),
.sram(mux_tree_tapbuf_size10_1_sram[0:3]),
.sram_inv(mux_left_track_3_undriven_sram_inv[0:3]),
.out(chanx_left_out[1]));
mux_tree_tapbuf_size10_mem mem_left_track_1 (
.pReset(pReset),
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size2_mem_2_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size10_mem_0_ccff_tail),
.mem_out(mux_tree_tapbuf_size10_0_sram[0:3]));
mux_tree_tapbuf_size10_mem mem_left_track_3 (
.pReset(pReset),
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size10_mem_0_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size10_mem_1_ccff_tail),
.mem_out(mux_tree_tapbuf_size10_1_sram[0:3]));
endmodule
// ----- END Verilog module for sb_1__0_ -----
//----- Default net type -----
`default_nettype none

505
SOFA_A/SOFA_A_verilog/routing/sb_1__1_.v Normal file
View File

@ -0,0 +1,505 @@
//-------------------------------------------
// FPGA Synthesizable Verilog Netlist
// Description: Verilog modules for Unique Switch Blocks[1][1]
// Author: Xifan TANG
// Organization: University of Utah
// Date: Sun Feb 19 10:53:27 2023
//-------------------------------------------
//----- Time scale -----
`timescale 1ns / 1ps
//----- Default net type -----
`default_nettype none
// ----- Verilog module for sb_1__1_ -----
module sb_1__1_(pReset,
prog_clk,
chany_bottom_in,
bottom_right_grid_left_width_0_height_0_subtile_0__pin_inpad_0_,
bottom_right_grid_left_width_0_height_0_subtile_1__pin_inpad_0_,
bottom_right_grid_left_width_0_height_0_subtile_2__pin_inpad_0_,
bottom_right_grid_left_width_0_height_0_subtile_3__pin_inpad_0_,
bottom_right_grid_left_width_0_height_0_subtile_4__pin_inpad_0_,
bottom_right_grid_left_width_0_height_0_subtile_5__pin_inpad_0_,
bottom_right_grid_left_width_0_height_0_subtile_6__pin_inpad_0_,
bottom_right_grid_left_width_0_height_0_subtile_7__pin_inpad_0_,
bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_8_,
bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_9_,
bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_10_,
bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_11_,
bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_12_,
bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_13_,
bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_14_,
chanx_left_in,
left_top_grid_bottom_width_0_height_0_subtile_0__pin_inpad_0_,
left_top_grid_bottom_width_0_height_0_subtile_1__pin_inpad_0_,
left_top_grid_bottom_width_0_height_0_subtile_2__pin_inpad_0_,
left_top_grid_bottom_width_0_height_0_subtile_3__pin_inpad_0_,
left_top_grid_bottom_width_0_height_0_subtile_4__pin_inpad_0_,
left_top_grid_bottom_width_0_height_0_subtile_5__pin_inpad_0_,
left_top_grid_bottom_width_0_height_0_subtile_6__pin_inpad_0_,
left_top_grid_bottom_width_0_height_0_subtile_7__pin_inpad_0_,
left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_,
left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_,
left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_,
left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_,
left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_,
left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_,
left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_,
left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_,
ccff_head,
chany_bottom_out,
chanx_left_out,
ccff_tail);
//----- GLOBAL PORTS -----
input [0:0] pReset;
//----- GLOBAL PORTS -----
input [0:0] prog_clk;
//----- INPUT PORTS -----
input [0:10] chany_bottom_in;
//----- INPUT PORTS -----
input [0:0] bottom_right_grid_left_width_0_height_0_subtile_0__pin_inpad_0_;
//----- INPUT PORTS -----
input [0:0] bottom_right_grid_left_width_0_height_0_subtile_1__pin_inpad_0_;
//----- INPUT PORTS -----
input [0:0] bottom_right_grid_left_width_0_height_0_subtile_2__pin_inpad_0_;
//----- INPUT PORTS -----
input [0:0] bottom_right_grid_left_width_0_height_0_subtile_3__pin_inpad_0_;
//----- INPUT PORTS -----
input [0:0] bottom_right_grid_left_width_0_height_0_subtile_4__pin_inpad_0_;
//----- INPUT PORTS -----
input [0:0] bottom_right_grid_left_width_0_height_0_subtile_5__pin_inpad_0_;
//----- INPUT PORTS -----
input [0:0] bottom_right_grid_left_width_0_height_0_subtile_6__pin_inpad_0_;
//----- INPUT PORTS -----
input [0:0] bottom_right_grid_left_width_0_height_0_subtile_7__pin_inpad_0_;
//----- INPUT PORTS -----
input [0:0] bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_8_;
//----- INPUT PORTS -----
input [0:0] bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_9_;
//----- INPUT PORTS -----
input [0:0] bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_10_;
//----- INPUT PORTS -----
input [0:0] bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_11_;
//----- INPUT PORTS -----
input [0:0] bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_12_;
//----- INPUT PORTS -----
input [0:0] bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_13_;
//----- INPUT PORTS -----
input [0:0] bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_14_;
//----- INPUT PORTS -----
input [0:10] chanx_left_in;
//----- INPUT PORTS -----
input [0:0] left_top_grid_bottom_width_0_height_0_subtile_0__pin_inpad_0_;
//----- INPUT PORTS -----
input [0:0] left_top_grid_bottom_width_0_height_0_subtile_1__pin_inpad_0_;
//----- INPUT PORTS -----
input [0:0] left_top_grid_bottom_width_0_height_0_subtile_2__pin_inpad_0_;
//----- INPUT PORTS -----
input [0:0] left_top_grid_bottom_width_0_height_0_subtile_3__pin_inpad_0_;
//----- INPUT PORTS -----
input [0:0] left_top_grid_bottom_width_0_height_0_subtile_4__pin_inpad_0_;
//----- INPUT PORTS -----
input [0:0] left_top_grid_bottom_width_0_height_0_subtile_5__pin_inpad_0_;
//----- INPUT PORTS -----
input [0:0] left_top_grid_bottom_width_0_height_0_subtile_6__pin_inpad_0_;
//----- INPUT PORTS -----
input [0:0] left_top_grid_bottom_width_0_height_0_subtile_7__pin_inpad_0_;
//----- INPUT PORTS -----
input [0:0] left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_;
//----- INPUT PORTS -----
input [0:0] left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_;
//----- INPUT PORTS -----
input [0:0] left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_;
//----- INPUT PORTS -----
input [0:0] left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_;
//----- INPUT PORTS -----
input [0:0] left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_;
//----- INPUT PORTS -----
input [0:0] left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_;
//----- INPUT PORTS -----
input [0:0] left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_;
//----- INPUT PORTS -----
input [0:0] left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_;
//----- INPUT PORTS -----
input [0:0] ccff_head;
//----- OUTPUT PORTS -----
output [0:10] chany_bottom_out;
//----- OUTPUT PORTS -----
output [0:10] chanx_left_out;
//----- OUTPUT PORTS -----
output [0:0] ccff_tail;
//----- BEGIN wire-connection ports -----
//----- END wire-connection ports -----
//----- BEGIN Registered ports -----
//----- END Registered ports -----
wire [0:1] mux_bottom_track_11_undriven_sram_inv;
wire [0:1] mux_bottom_track_13_undriven_sram_inv;
wire [0:1] mux_bottom_track_15_undriven_sram_inv;
wire [0:1] mux_bottom_track_17_undriven_sram_inv;
wire [0:1] mux_bottom_track_19_undriven_sram_inv;
wire [0:4] mux_bottom_track_1_undriven_sram_inv;
wire [0:1] mux_bottom_track_21_undriven_sram_inv;
wire [0:4] mux_bottom_track_3_undriven_sram_inv;
wire [0:1] mux_bottom_track_5_undriven_sram_inv;
wire [0:1] mux_bottom_track_7_undriven_sram_inv;
wire [0:1] mux_bottom_track_9_undriven_sram_inv;
wire [0:1] mux_left_track_11_undriven_sram_inv;
wire [0:1] mux_left_track_13_undriven_sram_inv;
wire [0:1] mux_left_track_15_undriven_sram_inv;
wire [0:1] mux_left_track_17_undriven_sram_inv;
wire [0:1] mux_left_track_19_undriven_sram_inv;
wire [0:4] mux_left_track_1_undriven_sram_inv;
wire [0:1] mux_left_track_21_undriven_sram_inv;
wire [0:4] mux_left_track_3_undriven_sram_inv;
wire [0:1] mux_left_track_5_undriven_sram_inv;
wire [0:1] mux_left_track_7_undriven_sram_inv;
wire [0:1] mux_left_track_9_undriven_sram_inv;
wire [0:4] mux_tree_tapbuf_size16_0_sram;
wire [0:4] mux_tree_tapbuf_size16_1_sram;
wire [0:0] mux_tree_tapbuf_size16_mem_0_ccff_tail;
wire [0:0] mux_tree_tapbuf_size16_mem_1_ccff_tail;
wire [0:4] mux_tree_tapbuf_size17_0_sram;
wire [0:4] mux_tree_tapbuf_size17_1_sram;
wire [0:0] mux_tree_tapbuf_size17_mem_0_ccff_tail;
wire [0:0] mux_tree_tapbuf_size17_mem_1_ccff_tail;
wire [0:1] mux_tree_tapbuf_size2_0_sram;
wire [0:1] mux_tree_tapbuf_size2_1_sram;
wire [0:1] mux_tree_tapbuf_size2_2_sram;
wire [0:1] mux_tree_tapbuf_size2_3_sram;
wire [0:1] mux_tree_tapbuf_size2_4_sram;
wire [0:0] mux_tree_tapbuf_size2_mem_0_ccff_tail;
wire [0:0] mux_tree_tapbuf_size2_mem_1_ccff_tail;
wire [0:0] mux_tree_tapbuf_size2_mem_2_ccff_tail;
wire [0:0] mux_tree_tapbuf_size2_mem_3_ccff_tail;
wire [0:1] mux_tree_tapbuf_size3_0_sram;
wire [0:1] mux_tree_tapbuf_size3_10_sram;
wire [0:1] mux_tree_tapbuf_size3_11_sram;
wire [0:1] mux_tree_tapbuf_size3_12_sram;
wire [0:1] mux_tree_tapbuf_size3_1_sram;
wire [0:1] mux_tree_tapbuf_size3_2_sram;
wire [0:1] mux_tree_tapbuf_size3_3_sram;
wire [0:1] mux_tree_tapbuf_size3_4_sram;
wire [0:1] mux_tree_tapbuf_size3_5_sram;
wire [0:1] mux_tree_tapbuf_size3_6_sram;
wire [0:1] mux_tree_tapbuf_size3_7_sram;
wire [0:1] mux_tree_tapbuf_size3_8_sram;
wire [0:1] mux_tree_tapbuf_size3_9_sram;
wire [0:0] mux_tree_tapbuf_size3_mem_0_ccff_tail;
wire [0:0] mux_tree_tapbuf_size3_mem_10_ccff_tail;
wire [0:0] mux_tree_tapbuf_size3_mem_11_ccff_tail;
wire [0:0] mux_tree_tapbuf_size3_mem_12_ccff_tail;
wire [0:0] mux_tree_tapbuf_size3_mem_1_ccff_tail;
wire [0:0] mux_tree_tapbuf_size3_mem_2_ccff_tail;
wire [0:0] mux_tree_tapbuf_size3_mem_3_ccff_tail;
wire [0:0] mux_tree_tapbuf_size3_mem_4_ccff_tail;
wire [0:0] mux_tree_tapbuf_size3_mem_5_ccff_tail;
wire [0:0] mux_tree_tapbuf_size3_mem_6_ccff_tail;
wire [0:0] mux_tree_tapbuf_size3_mem_7_ccff_tail;
wire [0:0] mux_tree_tapbuf_size3_mem_8_ccff_tail;
wire [0:0] mux_tree_tapbuf_size3_mem_9_ccff_tail;
// ----- BEGIN Local short connections -----
// ----- END Local short connections -----
// ----- BEGIN Local output short connections -----
// ----- END Local output short connections -----
mux_tree_tapbuf_size16 mux_bottom_track_1 (
.in({bottom_right_grid_left_width_0_height_0_subtile_0__pin_inpad_0_, bottom_right_grid_left_width_0_height_0_subtile_1__pin_inpad_0_, bottom_right_grid_left_width_0_height_0_subtile_2__pin_inpad_0_, bottom_right_grid_left_width_0_height_0_subtile_3__pin_inpad_0_, bottom_right_grid_left_width_0_height_0_subtile_4__pin_inpad_0_, bottom_right_grid_left_width_0_height_0_subtile_5__pin_inpad_0_, bottom_right_grid_left_width_0_height_0_subtile_6__pin_inpad_0_, bottom_right_grid_left_width_0_height_0_subtile_7__pin_inpad_0_, bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_8_, bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_9_, bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_10_, bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_11_, bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_12_, bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_13_, bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_14_, chanx_left_in[1]}),
.sram(mux_tree_tapbuf_size16_0_sram[0:4]),
.sram_inv(mux_bottom_track_1_undriven_sram_inv[0:4]),
.out(chany_bottom_out[0]));
mux_tree_tapbuf_size16 mux_bottom_track_3 (
.in({bottom_right_grid_left_width_0_height_0_subtile_0__pin_inpad_0_, bottom_right_grid_left_width_0_height_0_subtile_1__pin_inpad_0_, bottom_right_grid_left_width_0_height_0_subtile_2__pin_inpad_0_, bottom_right_grid_left_width_0_height_0_subtile_3__pin_inpad_0_, bottom_right_grid_left_width_0_height_0_subtile_4__pin_inpad_0_, bottom_right_grid_left_width_0_height_0_subtile_5__pin_inpad_0_, bottom_right_grid_left_width_0_height_0_subtile_6__pin_inpad_0_, bottom_right_grid_left_width_0_height_0_subtile_7__pin_inpad_0_, bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_8_, bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_9_, bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_10_, bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_11_, bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_12_, bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_13_, bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_14_, chanx_left_in[2]}),
.sram(mux_tree_tapbuf_size16_1_sram[0:4]),
.sram_inv(mux_bottom_track_3_undriven_sram_inv[0:4]),
.out(chany_bottom_out[1]));
mux_tree_tapbuf_size16_mem mem_bottom_track_1 (
.pReset(pReset),
.prog_clk(prog_clk),
.ccff_head(ccff_head),
.ccff_tail(mux_tree_tapbuf_size16_mem_0_ccff_tail),
.mem_out(mux_tree_tapbuf_size16_0_sram[0:4]));
mux_tree_tapbuf_size16_mem mem_bottom_track_3 (
.pReset(pReset),
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size16_mem_0_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size16_mem_1_ccff_tail),
.mem_out(mux_tree_tapbuf_size16_1_sram[0:4]));
mux_tree_tapbuf_size3 mux_bottom_track_5 (
.in({bottom_right_grid_left_width_0_height_0_subtile_0__pin_inpad_0_, bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_9_, chanx_left_in[3]}),
.sram(mux_tree_tapbuf_size3_0_sram[0:1]),
.sram_inv(mux_bottom_track_5_undriven_sram_inv[0:1]),
.out(chany_bottom_out[2]));
mux_tree_tapbuf_size3 mux_bottom_track_7 (
.in({bottom_right_grid_left_width_0_height_0_subtile_1__pin_inpad_0_, bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_10_, chanx_left_in[4]}),
.sram(mux_tree_tapbuf_size3_1_sram[0:1]),
.sram_inv(mux_bottom_track_7_undriven_sram_inv[0:1]),
.out(chany_bottom_out[3]));
mux_tree_tapbuf_size3 mux_bottom_track_9 (
.in({bottom_right_grid_left_width_0_height_0_subtile_2__pin_inpad_0_, bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_11_, chanx_left_in[5]}),
.sram(mux_tree_tapbuf_size3_2_sram[0:1]),
.sram_inv(mux_bottom_track_9_undriven_sram_inv[0:1]),
.out(chany_bottom_out[4]));
mux_tree_tapbuf_size3 mux_bottom_track_11 (
.in({bottom_right_grid_left_width_0_height_0_subtile_3__pin_inpad_0_, bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_12_, chanx_left_in[6]}),
.sram(mux_tree_tapbuf_size3_3_sram[0:1]),
.sram_inv(mux_bottom_track_11_undriven_sram_inv[0:1]),
.out(chany_bottom_out[5]));
mux_tree_tapbuf_size3 mux_bottom_track_13 (
.in({bottom_right_grid_left_width_0_height_0_subtile_4__pin_inpad_0_, bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_13_, chanx_left_in[7]}),
.sram(mux_tree_tapbuf_size3_4_sram[0:1]),
.sram_inv(mux_bottom_track_13_undriven_sram_inv[0:1]),
.out(chany_bottom_out[6]));
mux_tree_tapbuf_size3 mux_bottom_track_15 (
.in({bottom_right_grid_left_width_0_height_0_subtile_5__pin_inpad_0_, bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_14_, chanx_left_in[8]}),
.sram(mux_tree_tapbuf_size3_5_sram[0:1]),
.sram_inv(mux_bottom_track_15_undriven_sram_inv[0:1]),
.out(chany_bottom_out[7]));
mux_tree_tapbuf_size3 mux_left_track_5 (
.in({chany_bottom_in[1], left_top_grid_bottom_width_0_height_0_subtile_0__pin_inpad_0_, left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_}),
.sram(mux_tree_tapbuf_size3_6_sram[0:1]),
.sram_inv(mux_left_track_5_undriven_sram_inv[0:1]),
.out(chanx_left_out[2]));
mux_tree_tapbuf_size3 mux_left_track_7 (
.in({chany_bottom_in[2], left_top_grid_bottom_width_0_height_0_subtile_1__pin_inpad_0_, left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_}),
.sram(mux_tree_tapbuf_size3_7_sram[0:1]),
.sram_inv(mux_left_track_7_undriven_sram_inv[0:1]),
.out(chanx_left_out[3]));
mux_tree_tapbuf_size3 mux_left_track_9 (
.in({chany_bottom_in[3], left_top_grid_bottom_width_0_height_0_subtile_2__pin_inpad_0_, left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_}),
.sram(mux_tree_tapbuf_size3_8_sram[0:1]),
.sram_inv(mux_left_track_9_undriven_sram_inv[0:1]),
.out(chanx_left_out[4]));
mux_tree_tapbuf_size3 mux_left_track_11 (
.in({chany_bottom_in[4], left_top_grid_bottom_width_0_height_0_subtile_3__pin_inpad_0_, left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_}),
.sram(mux_tree_tapbuf_size3_9_sram[0:1]),
.sram_inv(mux_left_track_11_undriven_sram_inv[0:1]),
.out(chanx_left_out[5]));
mux_tree_tapbuf_size3 mux_left_track_13 (
.in({chany_bottom_in[5], left_top_grid_bottom_width_0_height_0_subtile_4__pin_inpad_0_, left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_}),
.sram(mux_tree_tapbuf_size3_10_sram[0:1]),
.sram_inv(mux_left_track_13_undriven_sram_inv[0:1]),
.out(chanx_left_out[6]));
mux_tree_tapbuf_size3 mux_left_track_15 (
.in({chany_bottom_in[6], left_top_grid_bottom_width_0_height_0_subtile_5__pin_inpad_0_, left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_}),
.sram(mux_tree_tapbuf_size3_11_sram[0:1]),
.sram_inv(mux_left_track_15_undriven_sram_inv[0:1]),
.out(chanx_left_out[7]));
mux_tree_tapbuf_size3 mux_left_track_17 (
.in({chany_bottom_in[7], left_top_grid_bottom_width_0_height_0_subtile_6__pin_inpad_0_, left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_}),
.sram(mux_tree_tapbuf_size3_12_sram[0:1]),
.sram_inv(mux_left_track_17_undriven_sram_inv[0:1]),
.out(chanx_left_out[8]));
mux_tree_tapbuf_size3_mem mem_bottom_track_5 (
.pReset(pReset),
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size16_mem_1_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size3_mem_0_ccff_tail),
.mem_out(mux_tree_tapbuf_size3_0_sram[0:1]));
mux_tree_tapbuf_size3_mem mem_bottom_track_7 (
.pReset(pReset),
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size3_mem_0_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size3_mem_1_ccff_tail),
.mem_out(mux_tree_tapbuf_size3_1_sram[0:1]));
mux_tree_tapbuf_size3_mem mem_bottom_track_9 (
.pReset(pReset),
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size3_mem_1_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size3_mem_2_ccff_tail),
.mem_out(mux_tree_tapbuf_size3_2_sram[0:1]));
mux_tree_tapbuf_size3_mem mem_bottom_track_11 (
.pReset(pReset),
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size3_mem_2_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size3_mem_3_ccff_tail),
.mem_out(mux_tree_tapbuf_size3_3_sram[0:1]));
mux_tree_tapbuf_size3_mem mem_bottom_track_13 (
.pReset(pReset),
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size3_mem_3_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size3_mem_4_ccff_tail),
.mem_out(mux_tree_tapbuf_size3_4_sram[0:1]));
mux_tree_tapbuf_size3_mem mem_bottom_track_15 (
.pReset(pReset),
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size3_mem_4_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size3_mem_5_ccff_tail),
.mem_out(mux_tree_tapbuf_size3_5_sram[0:1]));
mux_tree_tapbuf_size3_mem mem_left_track_5 (
.pReset(pReset),
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size17_mem_1_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size3_mem_6_ccff_tail),
.mem_out(mux_tree_tapbuf_size3_6_sram[0:1]));
mux_tree_tapbuf_size3_mem mem_left_track_7 (
.pReset(pReset),
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size3_mem_6_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size3_mem_7_ccff_tail),
.mem_out(mux_tree_tapbuf_size3_7_sram[0:1]));
mux_tree_tapbuf_size3_mem mem_left_track_9 (
.pReset(pReset),
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size3_mem_7_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size3_mem_8_ccff_tail),
.mem_out(mux_tree_tapbuf_size3_8_sram[0:1]));
mux_tree_tapbuf_size3_mem mem_left_track_11 (
.pReset(pReset),
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size3_mem_8_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size3_mem_9_ccff_tail),
.mem_out(mux_tree_tapbuf_size3_9_sram[0:1]));
mux_tree_tapbuf_size3_mem mem_left_track_13 (
.pReset(pReset),
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size3_mem_9_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size3_mem_10_ccff_tail),
.mem_out(mux_tree_tapbuf_size3_10_sram[0:1]));
mux_tree_tapbuf_size3_mem mem_left_track_15 (
.pReset(pReset),
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size3_mem_10_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size3_mem_11_ccff_tail),
.mem_out(mux_tree_tapbuf_size3_11_sram[0:1]));
mux_tree_tapbuf_size3_mem mem_left_track_17 (
.pReset(pReset),
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size3_mem_11_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size3_mem_12_ccff_tail),
.mem_out(mux_tree_tapbuf_size3_12_sram[0:1]));
mux_tree_tapbuf_size2 mux_bottom_track_17 (
.in({bottom_right_grid_left_width_0_height_0_subtile_6__pin_inpad_0_, chanx_left_in[9]}),
.sram(mux_tree_tapbuf_size2_0_sram[0:1]),
.sram_inv(mux_bottom_track_17_undriven_sram_inv[0:1]),
.out(chany_bottom_out[8]));
mux_tree_tapbuf_size2 mux_bottom_track_19 (
.in({bottom_right_grid_left_width_0_height_0_subtile_7__pin_inpad_0_, chanx_left_in[10]}),
.sram(mux_tree_tapbuf_size2_1_sram[0:1]),
.sram_inv(mux_bottom_track_19_undriven_sram_inv[0:1]),
.out(chany_bottom_out[9]));
mux_tree_tapbuf_size2 mux_bottom_track_21 (
.in({bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_8_, chanx_left_in[0]}),
.sram(mux_tree_tapbuf_size2_2_sram[0:1]),
.sram_inv(mux_bottom_track_21_undriven_sram_inv[0:1]),
.out(chany_bottom_out[10]));
mux_tree_tapbuf_size2 mux_left_track_19 (
.in({chany_bottom_in[8], left_top_grid_bottom_width_0_height_0_subtile_7__pin_inpad_0_}),
.sram(mux_tree_tapbuf_size2_3_sram[0:1]),
.sram_inv(mux_left_track_19_undriven_sram_inv[0:1]),
.out(chanx_left_out[9]));
mux_tree_tapbuf_size2 mux_left_track_21 (
.in({chany_bottom_in[9], left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_}),
.sram(mux_tree_tapbuf_size2_4_sram[0:1]),
.sram_inv(mux_left_track_21_undriven_sram_inv[0:1]),
.out(chanx_left_out[10]));
mux_tree_tapbuf_size2_mem mem_bottom_track_17 (
.pReset(pReset),
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size3_mem_5_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size2_mem_0_ccff_tail),
.mem_out(mux_tree_tapbuf_size2_0_sram[0:1]));
mux_tree_tapbuf_size2_mem mem_bottom_track_19 (
.pReset(pReset),
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size2_mem_0_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size2_mem_1_ccff_tail),
.mem_out(mux_tree_tapbuf_size2_1_sram[0:1]));
mux_tree_tapbuf_size2_mem mem_bottom_track_21 (
.pReset(pReset),
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size2_mem_1_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size2_mem_2_ccff_tail),
.mem_out(mux_tree_tapbuf_size2_2_sram[0:1]));
mux_tree_tapbuf_size2_mem mem_left_track_19 (
.pReset(pReset),
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size3_mem_12_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size2_mem_3_ccff_tail),
.mem_out(mux_tree_tapbuf_size2_3_sram[0:1]));
mux_tree_tapbuf_size2_mem mem_left_track_21 (
.pReset(pReset),
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size2_mem_3_ccff_tail),
.ccff_tail(ccff_tail),
.mem_out(mux_tree_tapbuf_size2_4_sram[0:1]));
mux_tree_tapbuf_size17 mux_left_track_1 (
.in({chany_bottom_in[10], left_top_grid_bottom_width_0_height_0_subtile_0__pin_inpad_0_, left_top_grid_bottom_width_0_height_0_subtile_1__pin_inpad_0_, left_top_grid_bottom_width_0_height_0_subtile_2__pin_inpad_0_, left_top_grid_bottom_width_0_height_0_subtile_3__pin_inpad_0_, left_top_grid_bottom_width_0_height_0_subtile_4__pin_inpad_0_, left_top_grid_bottom_width_0_height_0_subtile_5__pin_inpad_0_, left_top_grid_bottom_width_0_height_0_subtile_6__pin_inpad_0_, left_top_grid_bottom_width_0_height_0_subtile_7__pin_inpad_0_, left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_, left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_, left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_, left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_, left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_, left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_, left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_, left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_}),
.sram(mux_tree_tapbuf_size17_0_sram[0:4]),
.sram_inv(mux_left_track_1_undriven_sram_inv[0:4]),
.out(chanx_left_out[0]));
mux_tree_tapbuf_size17 mux_left_track_3 (
.in({chany_bottom_in[0], left_top_grid_bottom_width_0_height_0_subtile_0__pin_inpad_0_, left_top_grid_bottom_width_0_height_0_subtile_1__pin_inpad_0_, left_top_grid_bottom_width_0_height_0_subtile_2__pin_inpad_0_, left_top_grid_bottom_width_0_height_0_subtile_3__pin_inpad_0_, left_top_grid_bottom_width_0_height_0_subtile_4__pin_inpad_0_, left_top_grid_bottom_width_0_height_0_subtile_5__pin_inpad_0_, left_top_grid_bottom_width_0_height_0_subtile_6__pin_inpad_0_, left_top_grid_bottom_width_0_height_0_subtile_7__pin_inpad_0_, left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_, left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_, left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_, left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_, left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_, left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_, left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_, left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_}),
.sram(mux_tree_tapbuf_size17_1_sram[0:4]),
.sram_inv(mux_left_track_3_undriven_sram_inv[0:4]),
.out(chanx_left_out[1]));
mux_tree_tapbuf_size17_mem mem_left_track_1 (
.pReset(pReset),
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size2_mem_2_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size17_mem_0_ccff_tail),
.mem_out(mux_tree_tapbuf_size17_0_sram[0:4]));
mux_tree_tapbuf_size17_mem mem_left_track_3 (
.pReset(pReset),
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size17_mem_0_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size17_mem_1_ccff_tail),
.mem_out(mux_tree_tapbuf_size17_1_sram[0:4]));
endmodule
// ----- END Verilog module for sb_1__1_ -----
//----- Default net type -----
`default_nettype none

10
SOFA_A/SOFA_A_verilog/sub_module/arch_encoder.v Normal file
View File

@ -0,0 +1,10 @@
//-------------------------------------------
// FPGA Synthesizable Verilog Netlist
// Description: Decoders for fabric configuration protocol
// Author: Xifan TANG
// Organization: University of Utah
// Date: Sun Feb 19 10:53:27 2023
//-------------------------------------------
//----- Time scale -----
`timescale 1ns / 1ps

54
SOFA_A/SOFA_A_verilog/sub_module/inv_buf_passgate.v Normal file
View File

@ -0,0 +1,54 @@
//-------------------------------------------
// FPGA Synthesizable Verilog Netlist
// Description: Essential gates
// Author: Xifan TANG
// Organization: University of Utah
// Date: Sun Feb 19 10:53:27 2023
//-------------------------------------------
//----- Time scale -----
`timescale 1ns / 1ps
//----- Default net type -----
`default_nettype none
// ----- Verilog module for const0 -----
module const0(const0);
//----- OUTPUT PORTS -----
output [0:0] const0;
//----- BEGIN wire-connection ports -----
//----- END wire-connection ports -----
//----- BEGIN Registered ports -----
//----- END Registered ports -----
assign const0[0] = 1'b0;
endmodule
// ----- END Verilog module for const0 -----
//----- Default net type -----
`default_nettype none
//----- Default net type -----
`default_nettype none
// ----- Verilog module for const1 -----
module const1(const1);
//----- OUTPUT PORTS -----
output [0:0] const1;
//----- BEGIN wire-connection ports -----
//----- END wire-connection ports -----
//----- BEGIN Registered ports -----
//----- END Registered ports -----
assign const1[0] = 1'b1;
endmodule
// ----- END Verilog module for const1 -----
//----- Default net type -----
`default_nettype none

10
SOFA_A/SOFA_A_verilog/sub_module/local_encoder.v Normal file
View File

@ -0,0 +1,10 @@
//-------------------------------------------
// FPGA Synthesizable Verilog Netlist
// Description: Local Decoders for Multiplexers
// Author: Xifan TANG
// Organization: University of Utah
// Date: Sun Feb 19 10:53:27 2023
//-------------------------------------------
//----- Time scale -----
`timescale 1ns / 1ps

119
SOFA_A/SOFA_A_verilog/sub_module/luts.v Normal file
View File

@ -0,0 +1,119 @@
//-------------------------------------------
// FPGA Synthesizable Verilog Netlist
// Description: Look-Up Tables
// Author: Xifan TANG
// Organization: University of Utah
// Date: Sun Feb 19 10:53:27 2023
//-------------------------------------------
//----- Time scale -----
`timescale 1ns / 1ps
//----- Default net type -----
`default_nettype none
// ----- Verilog module for frac_lut4 -----
module frac_lut4(in,
sram,
sram_inv,
mode,
mode_inv,
lut2_out,
lut3_out,
lut4_out);
//----- INPUT PORTS -----
input [0:3] in;
//----- INPUT PORTS -----
input [0:15] sram;
//----- INPUT PORTS -----
input [0:15] sram_inv;
//----- INPUT PORTS -----
input [0:0] mode;
//----- INPUT PORTS -----
input [0:0] mode_inv;
//----- OUTPUT PORTS -----
output [0:1] lut2_out;
//----- OUTPUT PORTS -----
output [0:1] lut3_out;
//----- OUTPUT PORTS -----
output [0:0] lut4_out;
//----- BEGIN wire-connection ports -----
wire [0:3] in;
wire [0:1] lut2_out;
wire [0:1] lut3_out;
wire [0:0] lut4_out;
//----- END wire-connection ports -----
//----- BEGIN Registered ports -----
//----- END Registered ports -----
wire [0:0] sky130_fd_sc_hd__buf_2_0_X;
wire [0:0] sky130_fd_sc_hd__buf_2_1_X;
wire [0:0] sky130_fd_sc_hd__buf_2_2_X;
wire [0:0] sky130_fd_sc_hd__buf_2_3_X;
wire [0:0] sky130_fd_sc_hd__inv_1_0_Y;
wire [0:0] sky130_fd_sc_hd__inv_1_1_Y;
wire [0:0] sky130_fd_sc_hd__inv_1_2_Y;
wire [0:0] sky130_fd_sc_hd__inv_1_3_Y;
wire [0:0] sky130_fd_sc_hd__or2_1_0_X;
// ----- BEGIN Local short connections -----
// ----- END Local short connections -----
// ----- BEGIN Local output short connections -----
// ----- END Local output short connections -----
sky130_fd_sc_hd__or2_1 sky130_fd_sc_hd__or2_1_0_ (
.A(mode),
.B(in[3]),
.X(sky130_fd_sc_hd__or2_1_0_X));
sky130_fd_sc_hd__inv_1 sky130_fd_sc_hd__inv_1_0_ (
.A(in[0]),
.Y(sky130_fd_sc_hd__inv_1_0_Y));
sky130_fd_sc_hd__inv_1 sky130_fd_sc_hd__inv_1_1_ (
.A(in[1]),
.Y(sky130_fd_sc_hd__inv_1_1_Y));
sky130_fd_sc_hd__inv_1 sky130_fd_sc_hd__inv_1_2_ (
.A(in[2]),
.Y(sky130_fd_sc_hd__inv_1_2_Y));
sky130_fd_sc_hd__inv_1 sky130_fd_sc_hd__inv_1_3_ (
.A(sky130_fd_sc_hd__or2_1_0_X),
.Y(sky130_fd_sc_hd__inv_1_3_Y));
sky130_fd_sc_hd__buf_2 sky130_fd_sc_hd__buf_2_0_ (
.A(in[0]),
.X(sky130_fd_sc_hd__buf_2_0_X));
sky130_fd_sc_hd__buf_2 sky130_fd_sc_hd__buf_2_1_ (
.A(in[1]),
.X(sky130_fd_sc_hd__buf_2_1_X));
sky130_fd_sc_hd__buf_2 sky130_fd_sc_hd__buf_2_2_ (
.A(in[2]),
.X(sky130_fd_sc_hd__buf_2_2_X));
sky130_fd_sc_hd__buf_2 sky130_fd_sc_hd__buf_2_3_ (
.A(sky130_fd_sc_hd__or2_1_0_X),
.X(sky130_fd_sc_hd__buf_2_3_X));
frac_lut4_mux frac_lut4_mux_0_ (
.in(sram[0:15]),
.sram({sky130_fd_sc_hd__buf_2_0_X, sky130_fd_sc_hd__buf_2_1_X, sky130_fd_sc_hd__buf_2_2_X, sky130_fd_sc_hd__buf_2_3_X}),
.sram_inv({sky130_fd_sc_hd__inv_1_0_Y, sky130_fd_sc_hd__inv_1_1_Y, sky130_fd_sc_hd__inv_1_2_Y, sky130_fd_sc_hd__inv_1_3_Y}),
.lut2_out(lut2_out[0:1]),
.lut3_out(lut3_out[0:1]),
.lut4_out(lut4_out));
endmodule
// ----- END Verilog module for frac_lut4 -----
//----- Default net type -----
`default_nettype none

652
SOFA_A/SOFA_A_verilog/sub_module/memories.v Normal file
View File

@ -0,0 +1,652 @@
//-------------------------------------------
// FPGA Synthesizable Verilog Netlist
// Description: Memories used in FPGA
// Author: Xifan TANG
// Organization: University of Utah
// Date: Sun Feb 19 10:53:27 2023
//-------------------------------------------
//----- Time scale -----
`timescale 1ns / 1ps
//----- Default net type -----
`default_nettype none
// ----- Verilog module for mux_tree_tapbuf_size10_mem -----
module mux_tree_tapbuf_size10_mem(pReset,
prog_clk,
ccff_head,
ccff_tail,
mem_out);
//----- GLOBAL PORTS -----
input [0:0] pReset;
//----- GLOBAL PORTS -----
input [0:0] prog_clk;
//----- INPUT PORTS -----
input [0:0] ccff_head;
//----- OUTPUT PORTS -----
output [0:0] ccff_tail;
//----- OUTPUT PORTS -----
output [0:3] mem_out;
//----- BEGIN wire-connection ports -----
//----- END wire-connection ports -----
//----- BEGIN Registered ports -----
//----- END Registered ports -----
// ----- BEGIN Local short connections -----
// ----- END Local short connections -----
// ----- BEGIN Local output short connections -----
assign ccff_tail[0] = mem_out[3];
// ----- END Local output short connections -----
sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ (
.RESET_B(pReset),
.CLK(prog_clk),
.D(ccff_head),
.Q(mem_out[0]));
sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ (
.RESET_B(pReset),
.CLK(prog_clk),
.D(mem_out[0]),
.Q(mem_out[1]));
sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ (
.RESET_B(pReset),
.CLK(prog_clk),
.D(mem_out[1]),
.Q(mem_out[2]));
sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ (
.RESET_B(pReset),
.CLK(prog_clk),
.D(mem_out[2]),
.Q(mem_out[3]));
endmodule
// ----- END Verilog module for mux_tree_tapbuf_size10_mem -----
//----- Default net type -----
`default_nettype none
//----- Default net type -----
`default_nettype none
// ----- Verilog module for mux_tree_tapbuf_size6_mem -----
module mux_tree_tapbuf_size6_mem(pReset,
prog_clk,
ccff_head,
ccff_tail,
mem_out);
//----- GLOBAL PORTS -----
input [0:0] pReset;
//----- GLOBAL PORTS -----
input [0:0] prog_clk;
//----- INPUT PORTS -----
input [0:0] ccff_head;
//----- OUTPUT PORTS -----
output [0:0] ccff_tail;
//----- OUTPUT PORTS -----
output [0:2] mem_out;
//----- BEGIN wire-connection ports -----
//----- END wire-connection ports -----
//----- BEGIN Registered ports -----
//----- END Registered ports -----
// ----- BEGIN Local short connections -----
// ----- END Local short connections -----
// ----- BEGIN Local output short connections -----
assign ccff_tail[0] = mem_out[2];
// ----- END Local output short connections -----
sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ (
.RESET_B(pReset),
.CLK(prog_clk),
.D(ccff_head),
.Q(mem_out[0]));
sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ (
.RESET_B(pReset),
.CLK(prog_clk),
.D(mem_out[0]),
.Q(mem_out[1]));
sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ (
.RESET_B(pReset),
.CLK(prog_clk),
.D(mem_out[1]),
.Q(mem_out[2]));
endmodule
// ----- END Verilog module for mux_tree_tapbuf_size6_mem -----
//----- Default net type -----
`default_nettype none
//----- Default net type -----
`default_nettype none
// ----- Verilog module for mux_tree_tapbuf_size2_mem -----
module mux_tree_tapbuf_size2_mem(pReset,
prog_clk,
ccff_head,
ccff_tail,
mem_out);
//----- GLOBAL PORTS -----
input [0:0] pReset;
//----- GLOBAL PORTS -----
input [0:0] prog_clk;
//----- INPUT PORTS -----
input [0:0] ccff_head;
//----- OUTPUT PORTS -----
output [0:0] ccff_tail;
//----- OUTPUT PORTS -----
output [0:1] mem_out;
//----- BEGIN wire-connection ports -----
//----- END wire-connection ports -----
//----- BEGIN Registered ports -----
//----- END Registered ports -----
// ----- BEGIN Local short connections -----
// ----- END Local short connections -----
// ----- BEGIN Local output short connections -----
assign ccff_tail[0] = mem_out[1];
// ----- END Local output short connections -----
sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ (
.RESET_B(pReset),
.CLK(prog_clk),
.D(ccff_head),
.Q(mem_out[0]));
sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ (
.RESET_B(pReset),
.CLK(prog_clk),
.D(mem_out[0]),
.Q(mem_out[1]));
endmodule
// ----- END Verilog module for mux_tree_tapbuf_size2_mem -----
//----- Default net type -----
`default_nettype none
//----- Default net type -----
`default_nettype none
// ----- Verilog module for mux_tree_tapbuf_size17_mem -----
module mux_tree_tapbuf_size17_mem(pReset,
prog_clk,
ccff_head,
ccff_tail,
mem_out);
//----- GLOBAL PORTS -----
input [0:0] pReset;
//----- GLOBAL PORTS -----
input [0:0] prog_clk;
//----- INPUT PORTS -----
input [0:0] ccff_head;
//----- OUTPUT PORTS -----
output [0:0] ccff_tail;
//----- OUTPUT PORTS -----
output [0:4] mem_out;
//----- BEGIN wire-connection ports -----
//----- END wire-connection ports -----
//----- BEGIN Registered ports -----
//----- END Registered ports -----
// ----- BEGIN Local short connections -----
// ----- END Local short connections -----
// ----- BEGIN Local output short connections -----
assign ccff_tail[0] = mem_out[4];
// ----- END Local output short connections -----
sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ (
.RESET_B(pReset),
.CLK(prog_clk),
.D(ccff_head),
.Q(mem_out[0]));
sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ (
.RESET_B(pReset),
.CLK(prog_clk),
.D(mem_out[0]),
.Q(mem_out[1]));
sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ (
.RESET_B(pReset),
.CLK(prog_clk),
.D(mem_out[1]),
.Q(mem_out[2]));
sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ (
.RESET_B(pReset),
.CLK(prog_clk),
.D(mem_out[2]),
.Q(mem_out[3]));
sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_4_ (
.RESET_B(pReset),
.CLK(prog_clk),
.D(mem_out[3]),
.Q(mem_out[4]));
endmodule
// ----- END Verilog module for mux_tree_tapbuf_size17_mem -----
//----- Default net type -----
`default_nettype none
//----- Default net type -----
`default_nettype none
// ----- Verilog module for mux_tree_tapbuf_size3_mem -----
module mux_tree_tapbuf_size3_mem(pReset,
prog_clk,
ccff_head,
ccff_tail,
mem_out);
//----- GLOBAL PORTS -----
input [0:0] pReset;
//----- GLOBAL PORTS -----
input [0:0] prog_clk;
//----- INPUT PORTS -----
input [0:0] ccff_head;
//----- OUTPUT PORTS -----
output [0:0] ccff_tail;
//----- OUTPUT PORTS -----
output [0:1] mem_out;
//----- BEGIN wire-connection ports -----
//----- END wire-connection ports -----
//----- BEGIN Registered ports -----
//----- END Registered ports -----
// ----- BEGIN Local short connections -----
// ----- END Local short connections -----
// ----- BEGIN Local output short connections -----
assign ccff_tail[0] = mem_out[1];
// ----- END Local output short connections -----
sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ (
.RESET_B(pReset),
.CLK(prog_clk),
.D(ccff_head),
.Q(mem_out[0]));
sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ (
.RESET_B(pReset),
.CLK(prog_clk),
.D(mem_out[0]),
.Q(mem_out[1]));
endmodule
// ----- END Verilog module for mux_tree_tapbuf_size3_mem -----
//----- Default net type -----
`default_nettype none
//----- Default net type -----
`default_nettype none
// ----- Verilog module for mux_tree_tapbuf_size16_mem -----
module mux_tree_tapbuf_size16_mem(pReset,
prog_clk,
ccff_head,
ccff_tail,
mem_out);
//----- GLOBAL PORTS -----
input [0:0] pReset;
//----- GLOBAL PORTS -----
input [0:0] prog_clk;
//----- INPUT PORTS -----
input [0:0] ccff_head;
//----- OUTPUT PORTS -----
output [0:0] ccff_tail;
//----- OUTPUT PORTS -----
output [0:4] mem_out;
//----- BEGIN wire-connection ports -----
//----- END wire-connection ports -----
//----- BEGIN Registered ports -----
//----- END Registered ports -----
// ----- BEGIN Local short connections -----
// ----- END Local short connections -----
// ----- BEGIN Local output short connections -----
assign ccff_tail[0] = mem_out[4];
// ----- END Local output short connections -----
sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ (
.RESET_B(pReset),
.CLK(prog_clk),
.D(ccff_head),
.Q(mem_out[0]));
sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ (
.RESET_B(pReset),
.CLK(prog_clk),
.D(mem_out[0]),
.Q(mem_out[1]));
sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ (
.RESET_B(pReset),
.CLK(prog_clk),
.D(mem_out[1]),
.Q(mem_out[2]));
sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ (
.RESET_B(pReset),
.CLK(prog_clk),
.D(mem_out[2]),
.Q(mem_out[3]));
sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_4_ (
.RESET_B(pReset),
.CLK(prog_clk),
.D(mem_out[3]),
.Q(mem_out[4]));
endmodule
// ----- END Verilog module for mux_tree_tapbuf_size16_mem -----
//----- Default net type -----
`default_nettype none
//----- Default net type -----
`default_nettype none
// ----- Verilog module for mux_tree_size2_mem -----
module mux_tree_size2_mem(pReset,
prog_clk,
ccff_head,
ccff_tail,
mem_out);
//----- GLOBAL PORTS -----
input [0:0] pReset;
//----- GLOBAL PORTS -----
input [0:0] prog_clk;
//----- INPUT PORTS -----
input [0:0] ccff_head;
//----- OUTPUT PORTS -----
output [0:0] ccff_tail;
//----- OUTPUT PORTS -----
output [0:1] mem_out;
//----- BEGIN wire-connection ports -----
//----- END wire-connection ports -----
//----- BEGIN Registered ports -----
//----- END Registered ports -----
// ----- BEGIN Local short connections -----
// ----- END Local short connections -----
// ----- BEGIN Local output short connections -----
assign ccff_tail[0] = mem_out[1];
// ----- END Local output short connections -----
sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ (
.RESET_B(pReset),
.CLK(prog_clk),
.D(ccff_head),
.Q(mem_out[0]));
sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ (
.RESET_B(pReset),
.CLK(prog_clk),
.D(mem_out[0]),
.Q(mem_out[1]));
endmodule
// ----- END Verilog module for mux_tree_size2_mem -----
//----- Default net type -----
`default_nettype none
//----- Default net type -----
`default_nettype none
// ----- Verilog module for frac_lut4_sky130_fd_sc_hd__dfrtp_1_mem -----
module frac_lut4_sky130_fd_sc_hd__dfrtp_1_mem(pReset,
prog_clk,
ccff_head,
ccff_tail,
mem_out);
//----- GLOBAL PORTS -----
input [0:0] pReset;
//----- GLOBAL PORTS -----
input [0:0] prog_clk;
//----- INPUT PORTS -----
input [0:0] ccff_head;
//----- OUTPUT PORTS -----
output [0:0] ccff_tail;
//----- OUTPUT PORTS -----
output [0:16] mem_out;
//----- BEGIN wire-connection ports -----
//----- END wire-connection ports -----
//----- BEGIN Registered ports -----
//----- END Registered ports -----
// ----- BEGIN Local short connections -----
// ----- END Local short connections -----
// ----- BEGIN Local output short connections -----
assign ccff_tail[0] = mem_out[16];
// ----- END Local output short connections -----
sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ (
.RESET_B(pReset),
.CLK(prog_clk),
.D(ccff_head),
.Q(mem_out[0]));
sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ (
.RESET_B(pReset),
.CLK(prog_clk),
.D(mem_out[0]),
.Q(mem_out[1]));
sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ (
.RESET_B(pReset),
.CLK(prog_clk),
.D(mem_out[1]),
.Q(mem_out[2]));
sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ (
.RESET_B(pReset),
.CLK(prog_clk),
.D(mem_out[2]),
.Q(mem_out[3]));
sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_4_ (
.RESET_B(pReset),
.CLK(prog_clk),
.D(mem_out[3]),
.Q(mem_out[4]));
sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_5_ (
.RESET_B(pReset),
.CLK(prog_clk),
.D(mem_out[4]),
.Q(mem_out[5]));
sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_6_ (
.RESET_B(pReset),
.CLK(prog_clk),
.D(mem_out[5]),
.Q(mem_out[6]));
sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_7_ (
.RESET_B(pReset),
.CLK(prog_clk),
.D(mem_out[6]),
.Q(mem_out[7]));
sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_8_ (
.RESET_B(pReset),
.CLK(prog_clk),
.D(mem_out[7]),
.Q(mem_out[8]));
sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_9_ (
.RESET_B(pReset),
.CLK(prog_clk),
.D(mem_out[8]),
.Q(mem_out[9]));
sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_10_ (
.RESET_B(pReset),
.CLK(prog_clk),
.D(mem_out[9]),
.Q(mem_out[10]));
sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_11_ (
.RESET_B(pReset),
.CLK(prog_clk),
.D(mem_out[10]),
.Q(mem_out[11]));
sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_12_ (
.RESET_B(pReset),
.CLK(prog_clk),
.D(mem_out[11]),
.Q(mem_out[12]));
sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_13_ (
.RESET_B(pReset),
.CLK(prog_clk),
.D(mem_out[12]),
.Q(mem_out[13]));
sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_14_ (
.RESET_B(pReset),
.CLK(prog_clk),
.D(mem_out[13]),
.Q(mem_out[14]));
sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_15_ (
.RESET_B(pReset),
.CLK(prog_clk),
.D(mem_out[14]),
.Q(mem_out[15]));
sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_16_ (
.RESET_B(pReset),
.CLK(prog_clk),
.D(mem_out[15]),
.Q(mem_out[16]));
endmodule
// ----- END Verilog module for frac_lut4_sky130_fd_sc_hd__dfrtp_1_mem -----
//----- Default net type -----
`default_nettype none
//----- Default net type -----
`default_nettype none
// ----- Verilog module for EMBEDDED_IO_HD_sky130_fd_sc_hd__dfrtp_1_mem -----
module EMBEDDED_IO_HD_sky130_fd_sc_hd__dfrtp_1_mem(pReset,
prog_clk,
ccff_head,
ccff_tail,
mem_out);
//----- GLOBAL PORTS -----
input [0:0] pReset;
//----- GLOBAL PORTS -----
input [0:0] prog_clk;
//----- INPUT PORTS -----
input [0:0] ccff_head;
//----- OUTPUT PORTS -----
output [0:0] ccff_tail;
//----- OUTPUT PORTS -----
output [0:0] mem_out;
//----- BEGIN wire-connection ports -----
//----- END wire-connection ports -----
//----- BEGIN Registered ports -----
//----- END Registered ports -----
// ----- BEGIN Local short connections -----
// ----- END Local short connections -----
// ----- BEGIN Local output short connections -----
assign ccff_tail[0] = mem_out[0];
// ----- END Local output short connections -----
sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ (
.RESET_B(pReset),
.CLK(prog_clk),
.D(ccff_head),
.Q(mem_out));
endmodule
// ----- END Verilog module for EMBEDDED_IO_HD_sky130_fd_sc_hd__dfrtp_1_mem -----
//----- Default net type -----
`default_nettype none

10
SOFA_A/SOFA_A_verilog/sub_module/mux_primitives.v Normal file
View File

@ -0,0 +1,10 @@
//-------------------------------------------
// FPGA Synthesizable Verilog Netlist
// Description: Multiplexer primitives
// Author: Xifan TANG
// Organization: University of Utah
// Date: Sun Feb 19 10:53:27 2023
//-------------------------------------------
//----- Time scale -----
`timescale 1ns / 1ps

914
SOFA_A/SOFA_A_verilog/sub_module/muxes.v Normal file
View File

@ -0,0 +1,914 @@
//-------------------------------------------
// FPGA Synthesizable Verilog Netlist
// Description: Multiplexers
// Author: Xifan TANG
// Organization: University of Utah
// Date: Sun Feb 19 10:53:27 2023
//-------------------------------------------
//----- Time scale -----
`timescale 1ns / 1ps
//----- Default net type -----
`default_nettype none
// ----- Verilog module for mux_tree_tapbuf_size10 -----
module mux_tree_tapbuf_size10(in,
sram,
sram_inv,
out);
//----- INPUT PORTS -----
input [0:9] in;
//----- INPUT PORTS -----
input [0:3] sram;
//----- INPUT PORTS -----
input [0:3] sram_inv;
//----- OUTPUT PORTS -----
output [0:0] out;
//----- BEGIN wire-connection ports -----
//----- END wire-connection ports -----
//----- BEGIN Registered ports -----
//----- END Registered ports -----
wire [0:0] const1_0_const1;
wire [0:0] sky130_fd_sc_hd__mux2_1_0_X;
wire [0:0] sky130_fd_sc_hd__mux2_1_1_X;
wire [0:0] sky130_fd_sc_hd__mux2_1_2_X;
wire [0:0] sky130_fd_sc_hd__mux2_1_3_X;
wire [0:0] sky130_fd_sc_hd__mux2_1_4_X;
wire [0:0] sky130_fd_sc_hd__mux2_1_5_X;
wire [0:0] sky130_fd_sc_hd__mux2_1_6_X;
wire [0:0] sky130_fd_sc_hd__mux2_1_7_X;
wire [0:0] sky130_fd_sc_hd__mux2_1_8_X;
wire [0:0] sky130_fd_sc_hd__mux2_1_9_X;
// ----- BEGIN Local short connections -----
// ----- END Local short connections -----
// ----- BEGIN Local output short connections -----
// ----- END Local output short connections -----
const1 const1_0_ (
.const1(const1_0_const1));
sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ (
.A(sky130_fd_sc_hd__mux2_1_9_X),
.X(out));
sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ (
.A1(in[0]),
.A0(in[1]),
.S(sram[0]),
.X(sky130_fd_sc_hd__mux2_1_0_X));
sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ (
.A1(in[2]),
.A0(in[3]),
.S(sram[0]),
.X(sky130_fd_sc_hd__mux2_1_1_X));
sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ (
.A1(in[4]),
.A0(in[5]),
.S(sram[0]),
.X(sky130_fd_sc_hd__mux2_1_2_X));
sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ (
.A1(sky130_fd_sc_hd__mux2_1_0_X),
.A0(sky130_fd_sc_hd__mux2_1_1_X),
.S(sram[1]),
.X(sky130_fd_sc_hd__mux2_1_3_X));
sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ (
.A1(sky130_fd_sc_hd__mux2_1_2_X),
.A0(in[6]),
.S(sram[1]),
.X(sky130_fd_sc_hd__mux2_1_4_X));
sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ (
.A1(in[7]),
.A0(in[8]),
.S(sram[1]),
.X(sky130_fd_sc_hd__mux2_1_5_X));
sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ (
.A1(in[9]),
.A0(const1_0_const1),
.S(sram[1]),
.X(sky130_fd_sc_hd__mux2_1_6_X));
sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ (
.A1(sky130_fd_sc_hd__mux2_1_3_X),
.A0(sky130_fd_sc_hd__mux2_1_4_X),
.S(sram[2]),
.X(sky130_fd_sc_hd__mux2_1_7_X));
sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ (
.A1(sky130_fd_sc_hd__mux2_1_5_X),
.A0(sky130_fd_sc_hd__mux2_1_6_X),
.S(sram[2]),
.X(sky130_fd_sc_hd__mux2_1_8_X));
sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ (
.A1(sky130_fd_sc_hd__mux2_1_7_X),
.A0(sky130_fd_sc_hd__mux2_1_8_X),
.S(sram[3]),
.X(sky130_fd_sc_hd__mux2_1_9_X));
endmodule
// ----- END Verilog module for mux_tree_tapbuf_size10 -----
//----- Default net type -----
`default_nettype none
//----- Default net type -----
`default_nettype none
// ----- Verilog module for mux_tree_tapbuf_size6 -----
module mux_tree_tapbuf_size6(in,
sram,
sram_inv,
out);
//----- INPUT PORTS -----
input [0:5] in;
//----- INPUT PORTS -----
input [0:2] sram;
//----- INPUT PORTS -----
input [0:2] sram_inv;
//----- OUTPUT PORTS -----
output [0:0] out;
//----- BEGIN wire-connection ports -----
//----- END wire-connection ports -----
//----- BEGIN Registered ports -----
//----- END Registered ports -----
wire [0:0] const1_0_const1;
wire [0:0] sky130_fd_sc_hd__mux2_1_0_X;
wire [0:0] sky130_fd_sc_hd__mux2_1_1_X;
wire [0:0] sky130_fd_sc_hd__mux2_1_2_X;
wire [0:0] sky130_fd_sc_hd__mux2_1_3_X;
wire [0:0] sky130_fd_sc_hd__mux2_1_4_X;
wire [0:0] sky130_fd_sc_hd__mux2_1_5_X;
// ----- BEGIN Local short connections -----
// ----- END Local short connections -----
// ----- BEGIN Local output short connections -----
// ----- END Local output short connections -----
const1 const1_0_ (
.const1(const1_0_const1));
sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ (
.A(sky130_fd_sc_hd__mux2_1_5_X),
.X(out));
sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ (
.A1(in[0]),
.A0(in[1]),
.S(sram[0]),
.X(sky130_fd_sc_hd__mux2_1_0_X));
sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ (
.A1(in[2]),
.A0(in[3]),
.S(sram[0]),
.X(sky130_fd_sc_hd__mux2_1_1_X));
sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ (
.A1(in[4]),
.A0(in[5]),
.S(sram[0]),
.X(sky130_fd_sc_hd__mux2_1_2_X));
sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ (
.A1(sky130_fd_sc_hd__mux2_1_0_X),
.A0(sky130_fd_sc_hd__mux2_1_1_X),
.S(sram[1]),
.X(sky130_fd_sc_hd__mux2_1_3_X));
sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ (
.A1(sky130_fd_sc_hd__mux2_1_2_X),
.A0(const1_0_const1),
.S(sram[1]),
.X(sky130_fd_sc_hd__mux2_1_4_X));
sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ (
.A1(sky130_fd_sc_hd__mux2_1_3_X),
.A0(sky130_fd_sc_hd__mux2_1_4_X),
.S(sram[2]),
.X(sky130_fd_sc_hd__mux2_1_5_X));
endmodule
// ----- END Verilog module for mux_tree_tapbuf_size6 -----
//----- Default net type -----
`default_nettype none
//----- Default net type -----
`default_nettype none
// ----- Verilog module for mux_tree_tapbuf_size2 -----
module mux_tree_tapbuf_size2(in,
sram,
sram_inv,
out);
//----- INPUT PORTS -----
input [0:1] in;
//----- INPUT PORTS -----
input [0:1] sram;
//----- INPUT PORTS -----
input [0:1] sram_inv;
//----- OUTPUT PORTS -----
output [0:0] out;
//----- BEGIN wire-connection ports -----
//----- END wire-connection ports -----
//----- BEGIN Registered ports -----
//----- END Registered ports -----
wire [0:0] const1_0_const1;
wire [0:0] sky130_fd_sc_hd__mux2_1_0_X;
wire [0:0] sky130_fd_sc_hd__mux2_1_1_X;
// ----- BEGIN Local short connections -----
// ----- END Local short connections -----
// ----- BEGIN Local output short connections -----
// ----- END Local output short connections -----
const1 const1_0_ (
.const1(const1_0_const1));
sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ (
.A(sky130_fd_sc_hd__mux2_1_1_X),
.X(out));
sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ (
.A1(in[0]),
.A0(in[1]),
.S(sram[0]),
.X(sky130_fd_sc_hd__mux2_1_0_X));
sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ (
.A1(sky130_fd_sc_hd__mux2_1_0_X),
.A0(const1_0_const1),
.S(sram[1]),
.X(sky130_fd_sc_hd__mux2_1_1_X));
endmodule
// ----- END Verilog module for mux_tree_tapbuf_size2 -----
//----- Default net type -----
`default_nettype none
//----- Default net type -----
`default_nettype none
// ----- Verilog module for mux_tree_tapbuf_size17 -----
module mux_tree_tapbuf_size17(in,
sram,
sram_inv,
out);
//----- INPUT PORTS -----
input [0:16] in;
//----- INPUT PORTS -----
input [0:4] sram;
//----- INPUT PORTS -----
input [0:4] sram_inv;
//----- OUTPUT PORTS -----
output [0:0] out;
//----- BEGIN wire-connection ports -----
//----- END wire-connection ports -----
//----- BEGIN Registered ports -----
//----- END Registered ports -----
wire [0:0] const1_0_const1;
wire [0:0] sky130_fd_sc_hd__mux2_1_0_X;
wire [0:0] sky130_fd_sc_hd__mux2_1_10_X;
wire [0:0] sky130_fd_sc_hd__mux2_1_11_X;
wire [0:0] sky130_fd_sc_hd__mux2_1_12_X;
wire [0:0] sky130_fd_sc_hd__mux2_1_13_X;
wire [0:0] sky130_fd_sc_hd__mux2_1_14_X;
wire [0:0] sky130_fd_sc_hd__mux2_1_15_X;
wire [0:0] sky130_fd_sc_hd__mux2_1_16_X;
wire [0:0] sky130_fd_sc_hd__mux2_1_1_X;
wire [0:0] sky130_fd_sc_hd__mux2_1_2_X;
wire [0:0] sky130_fd_sc_hd__mux2_1_3_X;
wire [0:0] sky130_fd_sc_hd__mux2_1_4_X;
wire [0:0] sky130_fd_sc_hd__mux2_1_5_X;
wire [0:0] sky130_fd_sc_hd__mux2_1_6_X;
wire [0:0] sky130_fd_sc_hd__mux2_1_7_X;
wire [0:0] sky130_fd_sc_hd__mux2_1_8_X;
wire [0:0] sky130_fd_sc_hd__mux2_1_9_X;
// ----- BEGIN Local short connections -----
// ----- END Local short connections -----
// ----- BEGIN Local output short connections -----
// ----- END Local output short connections -----
const1 const1_0_ (
.const1(const1_0_const1));
sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ (
.A(sky130_fd_sc_hd__mux2_1_16_X),
.X(out));
sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ (
.A1(in[0]),
.A0(in[1]),
.S(sram[0]),
.X(sky130_fd_sc_hd__mux2_1_0_X));
sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ (
.A1(in[2]),
.A0(in[3]),
.S(sram[0]),
.X(sky130_fd_sc_hd__mux2_1_1_X));
sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ (
.A1(sky130_fd_sc_hd__mux2_1_0_X),
.A0(sky130_fd_sc_hd__mux2_1_1_X),
.S(sram[1]),
.X(sky130_fd_sc_hd__mux2_1_2_X));
sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ (
.A1(in[4]),
.A0(in[5]),
.S(sram[1]),
.X(sky130_fd_sc_hd__mux2_1_3_X));
sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ (
.A1(in[6]),
.A0(in[7]),
.S(sram[1]),
.X(sky130_fd_sc_hd__mux2_1_4_X));
sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ (
.A1(in[8]),
.A0(in[9]),
.S(sram[1]),
.X(sky130_fd_sc_hd__mux2_1_5_X));
sky130_fd_sc_hd__mux2_1 mux_l2_in_4_ (
.A1(in[10]),
.A0(in[11]),
.S(sram[1]),
.X(sky130_fd_sc_hd__mux2_1_6_X));
sky130_fd_sc_hd__mux2_1 mux_l2_in_5_ (
.A1(in[12]),
.A0(in[13]),
.S(sram[1]),
.X(sky130_fd_sc_hd__mux2_1_7_X));
sky130_fd_sc_hd__mux2_1 mux_l2_in_6_ (
.A1(in[14]),
.A0(in[15]),
.S(sram[1]),
.X(sky130_fd_sc_hd__mux2_1_8_X));
sky130_fd_sc_hd__mux2_1 mux_l2_in_7_ (
.A1(in[16]),
.A0(const1_0_const1),
.S(sram[1]),
.X(sky130_fd_sc_hd__mux2_1_9_X));
sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ (
.A1(sky130_fd_sc_hd__mux2_1_2_X),
.A0(sky130_fd_sc_hd__mux2_1_3_X),
.S(sram[2]),
.X(sky130_fd_sc_hd__mux2_1_10_X));
sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ (
.A1(sky130_fd_sc_hd__mux2_1_4_X),
.A0(sky130_fd_sc_hd__mux2_1_5_X),
.S(sram[2]),
.X(sky130_fd_sc_hd__mux2_1_11_X));
sky130_fd_sc_hd__mux2_1 mux_l3_in_2_ (
.A1(sky130_fd_sc_hd__mux2_1_6_X),
.A0(sky130_fd_sc_hd__mux2_1_7_X),
.S(sram[2]),
.X(sky130_fd_sc_hd__mux2_1_12_X));
sky130_fd_sc_hd__mux2_1 mux_l3_in_3_ (
.A1(sky130_fd_sc_hd__mux2_1_8_X),
.A0(sky130_fd_sc_hd__mux2_1_9_X),
.S(sram[2]),
.X(sky130_fd_sc_hd__mux2_1_13_X));
sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ (
.A1(sky130_fd_sc_hd__mux2_1_10_X),
.A0(sky130_fd_sc_hd__mux2_1_11_X),
.S(sram[3]),
.X(sky130_fd_sc_hd__mux2_1_14_X));
sky130_fd_sc_hd__mux2_1 mux_l4_in_1_ (
.A1(sky130_fd_sc_hd__mux2_1_12_X),
.A0(sky130_fd_sc_hd__mux2_1_13_X),
.S(sram[3]),
.X(sky130_fd_sc_hd__mux2_1_15_X));
sky130_fd_sc_hd__mux2_1 mux_l5_in_0_ (
.A1(sky130_fd_sc_hd__mux2_1_14_X),
.A0(sky130_fd_sc_hd__mux2_1_15_X),
.S(sram[4]),
.X(sky130_fd_sc_hd__mux2_1_16_X));
endmodule
// ----- END Verilog module for mux_tree_tapbuf_size17 -----
//----- Default net type -----
`default_nettype none
//----- Default net type -----
`default_nettype none
// ----- Verilog module for mux_tree_tapbuf_size3 -----
module mux_tree_tapbuf_size3(in,
sram,
sram_inv,
out);
//----- INPUT PORTS -----
input [0:2] in;
//----- INPUT PORTS -----
input [0:1] sram;
//----- INPUT PORTS -----
input [0:1] sram_inv;
//----- OUTPUT PORTS -----
output [0:0] out;
//----- BEGIN wire-connection ports -----
//----- END wire-connection ports -----
//----- BEGIN Registered ports -----
//----- END Registered ports -----
wire [0:0] const1_0_const1;
wire [0:0] sky130_fd_sc_hd__mux2_1_0_X;
wire [0:0] sky130_fd_sc_hd__mux2_1_1_X;
wire [0:0] sky130_fd_sc_hd__mux2_1_2_X;
// ----- BEGIN Local short connections -----
// ----- END Local short connections -----
// ----- BEGIN Local output short connections -----
// ----- END Local output short connections -----
const1 const1_0_ (
.const1(const1_0_const1));
sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ (
.A(sky130_fd_sc_hd__mux2_1_2_X),
.X(out));
sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ (
.A1(in[0]),
.A0(in[1]),
.S(sram[0]),
.X(sky130_fd_sc_hd__mux2_1_0_X));
sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ (
.A1(in[2]),
.A0(const1_0_const1),
.S(sram[0]),
.X(sky130_fd_sc_hd__mux2_1_1_X));
sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ (
.A1(sky130_fd_sc_hd__mux2_1_0_X),
.A0(sky130_fd_sc_hd__mux2_1_1_X),
.S(sram[1]),
.X(sky130_fd_sc_hd__mux2_1_2_X));
endmodule
// ----- END Verilog module for mux_tree_tapbuf_size3 -----
//----- Default net type -----
`default_nettype none
//----- Default net type -----
`default_nettype none
// ----- Verilog module for mux_tree_tapbuf_size16 -----
module mux_tree_tapbuf_size16(in,
sram,
sram_inv,
out);
//----- INPUT PORTS -----
input [0:15] in;
//----- INPUT PORTS -----
input [0:4] sram;
//----- INPUT PORTS -----
input [0:4] sram_inv;
//----- OUTPUT PORTS -----
output [0:0] out;
//----- BEGIN wire-connection ports -----
//----- END wire-connection ports -----
//----- BEGIN Registered ports -----
//----- END Registered ports -----
wire [0:0] const1_0_const1;
wire [0:0] sky130_fd_sc_hd__mux2_1_0_X;
wire [0:0] sky130_fd_sc_hd__mux2_1_10_X;
wire [0:0] sky130_fd_sc_hd__mux2_1_11_X;
wire [0:0] sky130_fd_sc_hd__mux2_1_12_X;
wire [0:0] sky130_fd_sc_hd__mux2_1_13_X;
wire [0:0] sky130_fd_sc_hd__mux2_1_14_X;
wire [0:0] sky130_fd_sc_hd__mux2_1_15_X;
wire [0:0] sky130_fd_sc_hd__mux2_1_1_X;
wire [0:0] sky130_fd_sc_hd__mux2_1_2_X;
wire [0:0] sky130_fd_sc_hd__mux2_1_3_X;
wire [0:0] sky130_fd_sc_hd__mux2_1_4_X;
wire [0:0] sky130_fd_sc_hd__mux2_1_5_X;
wire [0:0] sky130_fd_sc_hd__mux2_1_6_X;
wire [0:0] sky130_fd_sc_hd__mux2_1_7_X;
wire [0:0] sky130_fd_sc_hd__mux2_1_8_X;
wire [0:0] sky130_fd_sc_hd__mux2_1_9_X;
// ----- BEGIN Local short connections -----
// ----- END Local short connections -----
// ----- BEGIN Local output short connections -----
// ----- END Local output short connections -----
const1 const1_0_ (
.const1(const1_0_const1));
sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ (
.A(sky130_fd_sc_hd__mux2_1_15_X),
.X(out));
sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ (
.A1(in[0]),
.A0(in[1]),
.S(sram[0]),
.X(sky130_fd_sc_hd__mux2_1_0_X));
sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ (
.A1(sky130_fd_sc_hd__mux2_1_0_X),
.A0(in[2]),
.S(sram[1]),
.X(sky130_fd_sc_hd__mux2_1_1_X));
sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ (
.A1(in[3]),
.A0(in[4]),
.S(sram[1]),
.X(sky130_fd_sc_hd__mux2_1_2_X));
sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ (
.A1(in[5]),
.A0(in[6]),
.S(sram[1]),
.X(sky130_fd_sc_hd__mux2_1_3_X));
sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ (
.A1(in[7]),
.A0(in[8]),
.S(sram[1]),
.X(sky130_fd_sc_hd__mux2_1_4_X));
sky130_fd_sc_hd__mux2_1 mux_l2_in_4_ (
.A1(in[9]),
.A0(in[10]),
.S(sram[1]),
.X(sky130_fd_sc_hd__mux2_1_5_X));
sky130_fd_sc_hd__mux2_1 mux_l2_in_5_ (
.A1(in[11]),
.A0(in[12]),
.S(sram[1]),
.X(sky130_fd_sc_hd__mux2_1_6_X));
sky130_fd_sc_hd__mux2_1 mux_l2_in_6_ (
.A1(in[13]),
.A0(in[14]),
.S(sram[1]),
.X(sky130_fd_sc_hd__mux2_1_7_X));
sky130_fd_sc_hd__mux2_1 mux_l2_in_7_ (
.A1(in[15]),
.A0(const1_0_const1),
.S(sram[1]),
.X(sky130_fd_sc_hd__mux2_1_8_X));
sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ (
.A1(sky130_fd_sc_hd__mux2_1_1_X),
.A0(sky130_fd_sc_hd__mux2_1_2_X),
.S(sram[2]),
.X(sky130_fd_sc_hd__mux2_1_9_X));
sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ (
.A1(sky130_fd_sc_hd__mux2_1_3_X),
.A0(sky130_fd_sc_hd__mux2_1_4_X),
.S(sram[2]),
.X(sky130_fd_sc_hd__mux2_1_10_X));
sky130_fd_sc_hd__mux2_1 mux_l3_in_2_ (
.A1(sky130_fd_sc_hd__mux2_1_5_X),
.A0(sky130_fd_sc_hd__mux2_1_6_X),
.S(sram[2]),
.X(sky130_fd_sc_hd__mux2_1_11_X));
sky130_fd_sc_hd__mux2_1 mux_l3_in_3_ (
.A1(sky130_fd_sc_hd__mux2_1_7_X),
.A0(sky130_fd_sc_hd__mux2_1_8_X),
.S(sram[2]),
.X(sky130_fd_sc_hd__mux2_1_12_X));
sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ (
.A1(sky130_fd_sc_hd__mux2_1_9_X),
.A0(sky130_fd_sc_hd__mux2_1_10_X),
.S(sram[3]),
.X(sky130_fd_sc_hd__mux2_1_13_X));
sky130_fd_sc_hd__mux2_1 mux_l4_in_1_ (
.A1(sky130_fd_sc_hd__mux2_1_11_X),
.A0(sky130_fd_sc_hd__mux2_1_12_X),
.S(sram[3]),
.X(sky130_fd_sc_hd__mux2_1_14_X));
sky130_fd_sc_hd__mux2_1 mux_l5_in_0_ (
.A1(sky130_fd_sc_hd__mux2_1_13_X),
.A0(sky130_fd_sc_hd__mux2_1_14_X),
.S(sram[4]),
.X(sky130_fd_sc_hd__mux2_1_15_X));
endmodule
// ----- END Verilog module for mux_tree_tapbuf_size16 -----
//----- Default net type -----
`default_nettype none
//----- Default net type -----
`default_nettype none
// ----- Verilog module for mux_tree_size2 -----
module mux_tree_size2(in,
sram,
sram_inv,
out);
//----- INPUT PORTS -----
input [0:1] in;
//----- INPUT PORTS -----
input [0:1] sram;
//----- INPUT PORTS -----
input [0:1] sram_inv;
//----- OUTPUT PORTS -----
output [0:0] out;
//----- BEGIN wire-connection ports -----
//----- END wire-connection ports -----
//----- BEGIN Registered ports -----
//----- END Registered ports -----
wire [0:0] const1_0_const1;
wire [0:0] sky130_fd_sc_hd__mux2_1_0_X;
// ----- BEGIN Local short connections -----
// ----- END Local short connections -----
// ----- BEGIN Local output short connections -----
// ----- END Local output short connections -----
const1 const1_0_ (
.const1(const1_0_const1));
sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ (
.A1(in[0]),
.A0(in[1]),
.S(sram[0]),
.X(sky130_fd_sc_hd__mux2_1_0_X));
sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ (
.A1(sky130_fd_sc_hd__mux2_1_0_X),
.A0(const1_0_const1),
.S(sram[1]),
.X(out));
endmodule
// ----- END Verilog module for mux_tree_size2 -----
//----- Default net type -----
`default_nettype none
//----- Default net type -----
`default_nettype none
// ----- Verilog module for frac_lut4_mux -----
module frac_lut4_mux(in,
sram,
sram_inv,
lut2_out,
lut3_out,
lut4_out);
//----- INPUT PORTS -----
input [0:15] in;
//----- INPUT PORTS -----
input [0:3] sram;
//----- INPUT PORTS -----
input [0:3] sram_inv;
//----- OUTPUT PORTS -----
output [0:1] lut2_out;
//----- OUTPUT PORTS -----
output [0:1] lut3_out;
//----- OUTPUT PORTS -----
output [0:0] lut4_out;
//----- BEGIN wire-connection ports -----
//----- END wire-connection ports -----
//----- BEGIN Registered ports -----
//----- END Registered ports -----
wire [0:0] sky130_fd_sc_hd__buf_2_5_X;
wire [0:0] sky130_fd_sc_hd__buf_2_6_X;
wire [0:0] sky130_fd_sc_hd__mux2_1_0_X;
wire [0:0] sky130_fd_sc_hd__mux2_1_10_X;
wire [0:0] sky130_fd_sc_hd__mux2_1_11_X;
wire [0:0] sky130_fd_sc_hd__mux2_1_12_X;
wire [0:0] sky130_fd_sc_hd__mux2_1_13_X;
wire [0:0] sky130_fd_sc_hd__mux2_1_14_X;
wire [0:0] sky130_fd_sc_hd__mux2_1_1_X;
wire [0:0] sky130_fd_sc_hd__mux2_1_2_X;
wire [0:0] sky130_fd_sc_hd__mux2_1_3_X;
wire [0:0] sky130_fd_sc_hd__mux2_1_4_X;
wire [0:0] sky130_fd_sc_hd__mux2_1_5_X;
wire [0:0] sky130_fd_sc_hd__mux2_1_6_X;
wire [0:0] sky130_fd_sc_hd__mux2_1_7_X;
wire [0:0] sky130_fd_sc_hd__mux2_1_8_X;
wire [0:0] sky130_fd_sc_hd__mux2_1_9_X;
// ----- BEGIN Local short connections -----
// ----- END Local short connections -----
// ----- BEGIN Local output short connections -----
// ----- END Local output short connections -----
sky130_fd_sc_hd__buf_2 sky130_fd_sc_hd__buf_2_0_ (
.A(sky130_fd_sc_hd__mux2_1_10_X),
.X(lut2_out[0]));
sky130_fd_sc_hd__buf_2 sky130_fd_sc_hd__buf_2_1_ (
.A(sky130_fd_sc_hd__mux2_1_11_X),
.X(lut2_out[1]));
sky130_fd_sc_hd__buf_2 sky130_fd_sc_hd__buf_2_2_ (
.A(sky130_fd_sc_hd__mux2_1_12_X),
.X(lut3_out[0]));
sky130_fd_sc_hd__buf_2 sky130_fd_sc_hd__buf_2_3_ (
.A(sky130_fd_sc_hd__mux2_1_13_X),
.X(lut3_out[1]));
sky130_fd_sc_hd__buf_2 sky130_fd_sc_hd__buf_2_4_ (
.A(sky130_fd_sc_hd__mux2_1_14_X),
.X(lut4_out));
sky130_fd_sc_hd__buf_2 sky130_fd_sc_hd__buf_2_5_ (
.A(sky130_fd_sc_hd__mux2_1_8_X),
.X(sky130_fd_sc_hd__buf_2_5_X));
sky130_fd_sc_hd__buf_2 sky130_fd_sc_hd__buf_2_6_ (
.A(sky130_fd_sc_hd__mux2_1_9_X),
.X(sky130_fd_sc_hd__buf_2_6_X));
sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ (
.A1(in[0]),
.A0(in[1]),
.S(sram[0]),
.X(sky130_fd_sc_hd__mux2_1_0_X));
sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ (
.A1(in[2]),
.A0(in[3]),
.S(sram[0]),
.X(sky130_fd_sc_hd__mux2_1_1_X));
sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ (
.A1(in[4]),
.A0(in[5]),
.S(sram[0]),
.X(sky130_fd_sc_hd__mux2_1_2_X));
sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ (
.A1(in[6]),
.A0(in[7]),
.S(sram[0]),
.X(sky130_fd_sc_hd__mux2_1_3_X));
sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ (
.A1(in[8]),
.A0(in[9]),
.S(sram[0]),
.X(sky130_fd_sc_hd__mux2_1_4_X));
sky130_fd_sc_hd__mux2_1 mux_l1_in_5_ (
.A1(in[10]),
.A0(in[11]),
.S(sram[0]),
.X(sky130_fd_sc_hd__mux2_1_5_X));
sky130_fd_sc_hd__mux2_1 mux_l1_in_6_ (
.A1(in[12]),
.A0(in[13]),
.S(sram[0]),
.X(sky130_fd_sc_hd__mux2_1_6_X));
sky130_fd_sc_hd__mux2_1 mux_l1_in_7_ (
.A1(in[14]),
.A0(in[15]),
.S(sram[0]),
.X(sky130_fd_sc_hd__mux2_1_7_X));
sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ (
.A1(sky130_fd_sc_hd__mux2_1_0_X),
.A0(sky130_fd_sc_hd__mux2_1_1_X),
.S(sram[1]),
.X(sky130_fd_sc_hd__mux2_1_8_X));
sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ (
.A1(sky130_fd_sc_hd__mux2_1_2_X),
.A0(sky130_fd_sc_hd__mux2_1_3_X),
.S(sram[1]),
.X(sky130_fd_sc_hd__mux2_1_9_X));
sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ (
.A1(sky130_fd_sc_hd__mux2_1_4_X),
.A0(sky130_fd_sc_hd__mux2_1_5_X),
.S(sram[1]),
.X(sky130_fd_sc_hd__mux2_1_10_X));
sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ (
.A1(sky130_fd_sc_hd__mux2_1_6_X),
.A0(sky130_fd_sc_hd__mux2_1_7_X),
.S(sram[1]),
.X(sky130_fd_sc_hd__mux2_1_11_X));
sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ (
.A1(sky130_fd_sc_hd__buf_2_5_X),
.A0(sky130_fd_sc_hd__buf_2_6_X),
.S(sram[2]),
.X(sky130_fd_sc_hd__mux2_1_12_X));
sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ (
.A1(sky130_fd_sc_hd__mux2_1_10_X),
.A0(sky130_fd_sc_hd__mux2_1_11_X),
.S(sram[2]),
.X(sky130_fd_sc_hd__mux2_1_13_X));
sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ (
.A1(sky130_fd_sc_hd__mux2_1_12_X),
.A0(sky130_fd_sc_hd__mux2_1_13_X),
.S(sram[3]),
.X(sky130_fd_sc_hd__mux2_1_14_X));
endmodule
// ----- END Verilog module for frac_lut4_mux -----
//----- Default net type -----
`default_nettype none

10
SOFA_A/SOFA_A_verilog/sub_module/shift_register_banks.v Normal file
View File

@ -0,0 +1,10 @@
//-------------------------------------------
// FPGA Synthesizable Verilog Netlist
// Description: Shift register banks used in FPGA
// Author: Xifan TANG
// Organization: University of Utah
// Date: Sun Feb 19 10:53:27 2023
//-------------------------------------------
//----- Time scale -----
`timescale 1ns / 1ps

358
SOFA_A/SOFA_A_verilog/sub_module/user_defined_templates.v Normal file
View File

@ -0,0 +1,358 @@
//-------------------------------------------
// FPGA Synthesizable Verilog Netlist
// Description: Template for user-defined Verilog modules
// Author: Xifan TANG
// Organization: University of Utah
// Date: Sun Feb 19 10:53:27 2023
//-------------------------------------------
//----- Time scale -----
`timescale 1ns / 1ps
// ----- Template Verilog module for sky130_fd_sc_hd__inv_1 -----
//----- Default net type -----
`default_nettype none
// ----- Verilog module for sky130_fd_sc_hd__inv_1 -----
module sky130_fd_sc_hd__inv_1(A,
Y);
//----- INPUT PORTS -----
input [0:0] A;
//----- OUTPUT PORTS -----
output [0:0] Y;
//----- BEGIN wire-connection ports -----
//----- END wire-connection ports -----
//----- BEGIN Registered ports -----
//----- END Registered ports -----
// ----- Internal logic should start here -----
// ----- Internal logic should end here -----
endmodule
// ----- END Verilog module for sky130_fd_sc_hd__inv_1 -----
//----- Default net type -----
`default_nettype none
// ----- Template Verilog module for sky130_fd_sc_hd__buf_2 -----
//----- Default net type -----
`default_nettype none
// ----- Verilog module for sky130_fd_sc_hd__buf_2 -----
module sky130_fd_sc_hd__buf_2(A,
X);
//----- INPUT PORTS -----
input [0:0] A;
//----- OUTPUT PORTS -----
output [0:0] X;
//----- BEGIN wire-connection ports -----
//----- END wire-connection ports -----
//----- BEGIN Registered ports -----
//----- END Registered ports -----
// ----- Internal logic should start here -----
// ----- Internal logic should end here -----
endmodule
// ----- END Verilog module for sky130_fd_sc_hd__buf_2 -----
//----- Default net type -----
`default_nettype none
// ----- Template Verilog module for sky130_fd_sc_hd__buf_4 -----
//----- Default net type -----
`default_nettype none
// ----- Verilog module for sky130_fd_sc_hd__buf_4 -----
module sky130_fd_sc_hd__buf_4(A,
X);
//----- INPUT PORTS -----
input [0:0] A;
//----- OUTPUT PORTS -----
output [0:0] X;
//----- BEGIN wire-connection ports -----
//----- END wire-connection ports -----
//----- BEGIN Registered ports -----
//----- END Registered ports -----
// ----- Internal logic should start here -----
// ----- Internal logic should end here -----
endmodule
// ----- END Verilog module for sky130_fd_sc_hd__buf_4 -----
//----- Default net type -----
`default_nettype none
// ----- Template Verilog module for sky130_fd_sc_hd__inv_2 -----
//----- Default net type -----
`default_nettype none
// ----- Verilog module for sky130_fd_sc_hd__inv_2 -----
module sky130_fd_sc_hd__inv_2(A,
Y);
//----- INPUT PORTS -----
input [0:0] A;
//----- OUTPUT PORTS -----
output [0:0] Y;
//----- BEGIN wire-connection ports -----
//----- END wire-connection ports -----
//----- BEGIN Registered ports -----
//----- END Registered ports -----
// ----- Internal logic should start here -----
// ----- Internal logic should end here -----
endmodule
// ----- END Verilog module for sky130_fd_sc_hd__inv_2 -----
//----- Default net type -----
`default_nettype none
// ----- Template Verilog module for sky130_fd_sc_hd__or2_1 -----
//----- Default net type -----
`default_nettype none
// ----- Verilog module for sky130_fd_sc_hd__or2_1 -----
module sky130_fd_sc_hd__or2_1(A,
B,
X);
//----- INPUT PORTS -----
input [0:0] A;
//----- INPUT PORTS -----
input [0:0] B;
//----- OUTPUT PORTS -----
output [0:0] X;
//----- BEGIN wire-connection ports -----
//----- END wire-connection ports -----
//----- BEGIN Registered ports -----
//----- END Registered ports -----
// ----- Internal logic should start here -----
// ----- Internal logic should end here -----
endmodule
// ----- END Verilog module for sky130_fd_sc_hd__or2_1 -----
//----- Default net type -----
`default_nettype none
// ----- Template Verilog module for sky130_fd_sc_hd__mux2_1 -----
//----- Default net type -----
`default_nettype none
// ----- Verilog module for sky130_fd_sc_hd__mux2_1 -----
module sky130_fd_sc_hd__mux2_1(A1,
A0,
S,
X);
//----- INPUT PORTS -----
input [0:0] A1;
//----- INPUT PORTS -----
input [0:0] A0;
//----- INPUT PORTS -----
input [0:0] S;
//----- OUTPUT PORTS -----
output [0:0] X;
//----- BEGIN wire-connection ports -----
//----- END wire-connection ports -----
//----- BEGIN Registered ports -----
//----- END Registered ports -----
// ----- Internal logic should start here -----
// ----- Internal logic should end here -----
endmodule
// ----- END Verilog module for sky130_fd_sc_hd__mux2_1 -----
//----- Default net type -----
`default_nettype none
// ----- Template Verilog module for sky130_fd_sc_hd__sdfrtp_1 -----
//----- Default net type -----
`default_nettype none
// ----- Verilog module for sky130_fd_sc_hd__sdfrtp_1 -----
module sky130_fd_sc_hd__sdfrtp_1(SCE,
D,
SCD,
RESET_B,
CLK,
Q);
//----- GLOBAL PORTS -----
input [0:0] SCE;
//----- INPUT PORTS -----
input [0:0] D;
//----- INPUT PORTS -----
input [0:0] SCD;
//----- INPUT PORTS -----
input [0:0] RESET_B;
//----- INPUT PORTS -----
input [0:0] CLK;
//----- OUTPUT PORTS -----
output [0:0] Q;
//----- BEGIN wire-connection ports -----
//----- END wire-connection ports -----
//----- BEGIN Registered ports -----
//----- END Registered ports -----
// ----- Internal logic should start here -----
// ----- Internal logic should end here -----
endmodule
// ----- END Verilog module for sky130_fd_sc_hd__sdfrtp_1 -----
//----- Default net type -----
`default_nettype none
// ----- Template Verilog module for sky130_fd_sc_hd__dfrtp_1 -----
//----- Default net type -----
`default_nettype none
// ----- Verilog module for sky130_fd_sc_hd__dfrtp_1 -----
module sky130_fd_sc_hd__dfrtp_1(RESET_B,
CLK,
D,
Q);
//----- GLOBAL PORTS -----
input [0:0] RESET_B;
//----- GLOBAL PORTS -----
input [0:0] CLK;
//----- INPUT PORTS -----
input [0:0] D;
//----- OUTPUT PORTS -----
output [0:0] Q;
//----- BEGIN wire-connection ports -----
//----- END wire-connection ports -----
//----- BEGIN Registered ports -----
//----- END Registered ports -----
// ----- Internal logic should start here -----
// ----- Internal logic should end here -----
endmodule
// ----- END Verilog module for sky130_fd_sc_hd__dfrtp_1 -----
//----- Default net type -----
`default_nettype none
// ----- Template Verilog module for EMBEDDED_IO_HD -----
//----- Default net type -----
`default_nettype none
// ----- Verilog module for EMBEDDED_IO_HD -----
module EMBEDDED_IO_HD(IO_ISOL_N,
SOC_IN,
SOC_OUT,
SOC_DIR,
FPGA_OUT,
FPGA_DIR,
FPGA_IN);
//----- GLOBAL PORTS -----
input [0:0] IO_ISOL_N;
//----- GPIN PORTS -----
input [0:0] SOC_IN;
//----- GPOUT PORTS -----
output [0:0] SOC_OUT;
//----- GPOUT PORTS -----
output [0:0] SOC_DIR;
//----- INPUT PORTS -----
input [0:0] FPGA_OUT;
//----- INPUT PORTS -----
input [0:0] FPGA_DIR;
//----- OUTPUT PORTS -----
output [0:0] FPGA_IN;
//----- BEGIN wire-connection ports -----
//----- END wire-connection ports -----
//----- BEGIN Registered ports -----
//----- END Registered ports -----
// ----- Internal logic should start here -----
// ----- Internal logic should end here -----
endmodule
// ----- END Verilog module for EMBEDDED_IO_HD -----
//----- Default net type -----
`default_nettype none
// ----- Template Verilog module for sky130_fd_sc_hd__mux2_1_wrapper -----
//----- Default net type -----
`default_nettype none
// ----- Verilog module for sky130_fd_sc_hd__mux2_1_wrapper -----
module sky130_fd_sc_hd__mux2_1_wrapper(A0,
A1,
S,
X);
//----- INPUT PORTS -----
input [0:0] A0;
//----- INPUT PORTS -----
input [0:0] A1;
//----- INPUT PORTS -----
input [0:0] S;
//----- OUTPUT PORTS -----
output [0:0] X;
//----- BEGIN wire-connection ports -----
//----- END wire-connection ports -----
//----- BEGIN Registered ports -----
//----- END Registered ports -----
// ----- Internal logic should start here -----
// ----- Internal logic should end here -----
endmodule
// ----- END Verilog module for sky130_fd_sc_hd__mux2_1_wrapper -----
//----- Default net type -----
`default_nettype none

40
SOFA_A/SOFA_A_verilog/sub_module/wires.v Normal file
View File

@ -0,0 +1,40 @@
//-------------------------------------------
// FPGA Synthesizable Verilog Netlist
// Description: Wires
// Author: Xifan TANG
// Organization: University of Utah
// Date: Sun Feb 19 10:53:27 2023
//-------------------------------------------
//----- Time scale -----
`timescale 1ns / 1ps
// ----- BEGIN Verilog modules for regular wires -----
//----- Default net type -----
`default_nettype none
// ----- Verilog module for direct_interc -----
module direct_interc(in,
out);
//----- INPUT PORTS -----
input [0:0] in;
//----- OUTPUT PORTS -----
output [0:0] out;
//----- BEGIN wire-connection ports -----
//----- END wire-connection ports -----
//----- BEGIN Registered ports -----
//----- END Registered ports -----
wire [0:0] in;
wire [0:0] out;
assign out[0] = in[0];
endmodule
// ----- END Verilog module for direct_interc -----
//----- Default net type -----
`default_nettype none
// ----- END Verilog modules for regular wires -----

6608
SOFA_A/SOFA_A_verilog/top_autocheck_top_tb.v Normal file
View File

File diff suppressed because it is too large Load Diff

127
SOFA_A/SOFA_A_verilog/top_formal_random_top_tb.v Normal file
View File

@ -0,0 +1,127 @@
//-------------------------------------------
// FPGA Synthesizable Verilog Netlist
// Description: FPGA Verilog Testbench for Formal Top-level netlist of Design: top
// Author: Xifan TANG
// Organization: University of Utah
// Date: Sun Feb 19 10:53:27 2023
//-------------------------------------------
//----- Time scale -----
`timescale 1ns / 1ps
//----- Default net type -----
`default_nettype none
module top_top_formal_verification_random_tb;
// ----- Default clock port is added here since benchmark does not contain one -------
reg [0:0] clk;
// ----- Shared inputs -------
reg [0:0] a;
reg [0:0] b;
// ----- FPGA fabric outputs -------
wire [0:0] c_gfpga;
// ----- Benchmark outputs -------
wire [0:0] c_bench;
// ----- Output vectors checking flags -------
reg [0:0] c_flag;
// ----- Error counter -------
integer nb_error= 0;
// ----- FPGA fabric instanciation -------
top_top_formal_verification FPGA_DUT(
.a(a),
.b(b),
.c(c_gfpga)
);
// ----- End FPGA Fabric Instanication -------
// ----- Reference Benchmark Instanication -------
top REF_DUT(
.a(a),
.b(b),
.c(c_bench)
);
// ----- End reference Benchmark Instanication -------
// ----- Clock 'clk' Initialization -------
initial begin
clk[0] <= 1'b0;
while(1) begin
#6.660000324
clk[0] <= !clk[0];
end
end
// ----- Begin reset signal generation -----
// ----- End reset signal generation -----
// ----- Input Initialization -------
initial begin
a <= 1'b0;
b <= 1'b0;
c_flag[0] <= 1'b0;
end
// ----- Input Stimulus -------
always@(negedge clk[0]) begin
a <= $random;
b <= $random;
end
// ----- Begin checking output vectors -------
// ----- Skip the first falling edge of clock, it is for initialization -------
reg [0:0] sim_start;
always@(negedge clk[0]) begin
if (1'b1 == sim_start[0]) begin
sim_start[0] <= ~sim_start[0];
end else
begin
if(!(c_gfpga === c_bench) && !(c_bench === 1'bx)) begin
c_flag <= 1'b1;
end else begin
c_flag<= 1'b0;
end
end
end
always@(posedge c_flag) begin
if(c_flag) begin
nb_error = nb_error + 1;
$display("Mismatch on c_gfpga at time = %t", $realtime);
end
end
// ----- Begin output waveform to VCD file-------
initial begin
$dumpfile("top_formal.vcd");
$dumpvars(1, top_top_formal_verification_random_tb);
end
// ----- END output waveform to VCD file -------
initial begin
sim_start[0] <= 1'b1;
$timeformat(-9, 2, "ns", 20);
$display("Simulation start");
// ----- Can be changed by the user for his/her need -------
#26.6400013
if(nb_error == 0) begin
$display("Simulation Succeed");
end else begin
$display("Simulation Failed with %d error(s)", nb_error);
end
$finish;
end
endmodule
// ----- END Verilog module for top_top_formal_verification_random_tb -----
//----- Default net type -----
`default_nettype none

17
SOFA_A/SOFA_A_verilog/top_include_netlists.v Normal file
View File

@ -0,0 +1,17 @@
//-------------------------------------------
// FPGA Synthesizable Verilog Netlist
// Description: Netlist Summary
// Author: Xifan TANG
// Organization: University of Utah
// Date: Sun Feb 19 10:53:27 2023
//-------------------------------------------
//----- Time scale -----
`timescale 1ns / 1ps
// ------ Include fabric top-level netlists -----
`include "./SRC/fabric_netlists.v"
`include "top_output_verilog.v"
`include "./SRC/top_top_formal_verification.v"
`include "./SRC/top_formal_random_top_tb.v"

315
SOFA_A/SOFA_A_verilog/top_top_formal_verification.v Normal file
View File

@ -0,0 +1,315 @@
//-------------------------------------------
// FPGA Synthesizable Verilog Netlist
// Description: Verilog netlist for pre-configured FPGA fabric by design: top
// Author: Xifan TANG
// Organization: University of Utah
// Date: Sun Feb 19 10:53:27 2023
//-------------------------------------------
//----- Time scale -----
`timescale 1ns / 1ps
//----- Default net type -----
`default_nettype none
module top_top_formal_verification (
input [0:0] a,
input [0:0] b,
output [0:0] c);
// ----- Local wires for FPGA fabric -----
wire [0:0] clk_fm;
wire [0:0] Reset_fm;
wire [0:25] gfpga_pad_EMBEDDED_IO_HD_SOC_IN_fm;
wire [0:25] gfpga_pad_EMBEDDED_IO_HD_SOC_OUT_fm;
wire [0:25] gfpga_pad_EMBEDDED_IO_HD_SOC_DIR_fm;
wire [0:0] ccff_head_fm;
wire [0:0] ccff_tail_fm;
wire [0:0] IO_ISOL_N_fm;
wire [0:0] pReset_fm;
wire [0:0] prog_clk_fm;
wire [0:0] Test_en_fm;
// ----- FPGA top-level module to be capsulated -----
fpga_top U0_formal_verification (
.clk(clk_fm[0]),
.Reset(Reset_fm[0]),
.IO_ISOL_N(IO_ISOL_N_fm[0]),
.pReset(pReset_fm[0]),
.prog_clk(prog_clk_fm[0]),
.Test_en(Test_en_fm[0]),
.gfpga_pad_EMBEDDED_IO_HD_SOC_IN(gfpga_pad_EMBEDDED_IO_HD_SOC_IN_fm[0:25]),
.gfpga_pad_EMBEDDED_IO_HD_SOC_OUT(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT_fm[0:25]),
.gfpga_pad_EMBEDDED_IO_HD_SOC_DIR(gfpga_pad_EMBEDDED_IO_HD_SOC_DIR_fm[0:25]),
.ccff_head(ccff_head_fm[0]),
.ccff_tail(ccff_tail_fm[0]));
// ----- Begin Connect Global ports of FPGA top module -----
assign Test_en_fm[0] = 1'b0;
assign prog_clk_fm[0] = 1'b0;
assign pReset_fm[0] = 1'b1;
assign IO_ISOL_N_fm[0] = 1'b1;
assign clk_fm[0] = 1'b0;
assign Reset_fm[0] = 1'b1;
// ----- End Connect Global ports of FPGA top module -----
// ----- Link BLIF Benchmark I/Os to FPGA I/Os -----
// ----- Blif Benchmark input a is mapped to FPGA IOPAD gfpga_pad_EMBEDDED_IO_HD_SOC_IN_fm[18] -----
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN_fm[18] = a[0];
// ----- Blif Benchmark input b is mapped to FPGA IOPAD gfpga_pad_EMBEDDED_IO_HD_SOC_IN_fm[3] -----
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN_fm[3] = b[0];
// ----- Blif Benchmark output c is mapped to FPGA IOPAD gfpga_pad_EMBEDDED_IO_HD_SOC_OUT_fm[24] -----
assign c[0] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT_fm[24];
// ----- Wire unused FPGA I/Os to constants -----
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN_fm[0] = 1'b0;
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN_fm[1] = 1'b0;
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN_fm[2] = 1'b0;
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN_fm[4] = 1'b0;
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN_fm[5] = 1'b0;
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN_fm[6] = 1'b0;
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN_fm[7] = 1'b0;
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN_fm[8] = 1'b0;
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN_fm[9] = 1'b0;
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN_fm[10] = 1'b0;
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN_fm[11] = 1'b0;
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN_fm[12] = 1'b0;
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN_fm[13] = 1'b0;
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN_fm[14] = 1'b0;
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN_fm[15] = 1'b0;
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN_fm[16] = 1'b0;
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN_fm[17] = 1'b0;
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN_fm[19] = 1'b0;
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN_fm[20] = 1'b0;
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN_fm[21] = 1'b0;
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN_fm[22] = 1'b0;
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN_fm[23] = 1'b0;
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN_fm[24] = 1'b0;
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN_fm[25] = 1'b0;
// ----- Begin load bitstream to configuration memories -----
// ----- Begin assign bitstream to configuration memories -----
initial begin
force U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfrtp_1_mem.mem_out[0:16] = {17{1'b0}};
force U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.mem_frac_logic_out_0.mem_out[0:1] = {2{1'b0}};
force U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.mem_frac_lut4_0_in_2.mem_out[0:1] = {2{1'b0}};
force U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_fabric_out_0.mem_out[0:1] = {2{1'b0}};
force U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_fabric_out_1.mem_out[0:1] = {2{1'b0}};
force U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_ff_0_D_0.mem_out[0:1] = {2{1'b0}};
force U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_ff_1_D_0.mem_out[0:1] = {2{1'b0}};
force U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_1.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfrtp_1_mem.mem_out[0:16] = {17{1'b0}};
force U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_1.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.mem_frac_logic_out_0.mem_out[0:1] = {2{1'b0}};
force U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_1.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.mem_frac_lut4_0_in_2.mem_out[0:1] = {2{1'b0}};
force U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_1.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_fabric_out_0.mem_out[0:1] = {2{1'b0}};
force U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_1.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_fabric_out_1.mem_out[0:1] = {2{1'b0}};
force U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_1.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_ff_0_D_0.mem_out[0:1] = {2{1'b0}};
force U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_1.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_ff_1_D_0.mem_out[0:1] = {2{1'b0}};
force U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_2.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfrtp_1_mem.mem_out[0:16] = {17{1'b0}};
force U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_2.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.mem_frac_logic_out_0.mem_out[0:1] = {2{1'b0}};
force U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_2.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.mem_frac_lut4_0_in_2.mem_out[0:1] = {2{1'b0}};
force U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_2.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_fabric_out_0.mem_out[0:1] = {2{1'b0}};
force U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_2.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_fabric_out_1.mem_out[0:1] = {2{1'b0}};
force U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_2.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_ff_0_D_0.mem_out[0:1] = {2{1'b0}};
force U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_2.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_ff_1_D_0.mem_out[0:1] = {2{1'b0}};
force U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_3.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfrtp_1_mem.mem_out[0:16] = {17{1'b0}};
force U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_3.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.mem_frac_logic_out_0.mem_out[0:1] = {2{1'b0}};
force U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_3.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.mem_frac_lut4_0_in_2.mem_out[0:1] = {2{1'b0}};
force U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_3.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_fabric_out_0.mem_out[0:1] = {2{1'b0}};
force U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_3.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_fabric_out_1.mem_out[0:1] = {2{1'b0}};
force U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_3.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_ff_0_D_0.mem_out[0:1] = {2{1'b0}};
force U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_3.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_ff_1_D_0.mem_out[0:1] = {2{1'b0}};
force U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_4.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfrtp_1_mem.mem_out[0:16] = {17{1'b0}};
force U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_4.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.mem_frac_logic_out_0.mem_out[0:1] = {2{1'b0}};
force U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_4.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.mem_frac_lut4_0_in_2.mem_out[0:1] = {2{1'b0}};
force U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_4.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_fabric_out_0.mem_out[0:1] = {2{1'b0}};
force U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_4.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_fabric_out_1.mem_out[0:1] = {2{1'b0}};
force U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_4.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_ff_0_D_0.mem_out[0:1] = {2{1'b0}};
force U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_4.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_ff_1_D_0.mem_out[0:1] = {2{1'b0}};
force U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_5.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfrtp_1_mem.mem_out[0:16] = {17{1'b0}};
force U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_5.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.mem_frac_logic_out_0.mem_out[0:1] = {2{1'b0}};
force U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_5.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.mem_frac_lut4_0_in_2.mem_out[0:1] = {2{1'b0}};
force U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_5.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_fabric_out_0.mem_out[0:1] = {2{1'b0}};
force U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_5.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_fabric_out_1.mem_out[0:1] = {2{1'b0}};
force U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_5.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_ff_0_D_0.mem_out[0:1] = {2{1'b0}};
force U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_5.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_ff_1_D_0.mem_out[0:1] = {2{1'b0}};
force U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_6.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfrtp_1_mem.mem_out[0:16] = {17{1'b0}};
force U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_6.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.mem_frac_logic_out_0.mem_out[0:1] = {2{1'b0}};
force U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_6.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.mem_frac_lut4_0_in_2.mem_out[0:1] = {2{1'b0}};
force U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_6.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_fabric_out_0.mem_out[0:1] = {2{1'b0}};
force U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_6.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_fabric_out_1.mem_out[0:1] = {2{1'b0}};
force U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_6.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_ff_0_D_0.mem_out[0:1] = {2{1'b0}};
force U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_6.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_ff_1_D_0.mem_out[0:1] = {2{1'b0}};
force U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_7.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfrtp_1_mem.mem_out[0:16] = 17'b00000000110000001;
force U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_7.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.mem_frac_logic_out_0.mem_out[0:1] = {2{1'b0}};
force U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_7.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.mem_frac_lut4_0_in_2.mem_out[0:1] = 2'b01;
force U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_7.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_fabric_out_0.mem_out[0:1] = {2{1'b0}};
force U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_7.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_fabric_out_1.mem_out[0:1] = 2'b01;
force U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_7.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_ff_0_D_0.mem_out[0:1] = {2{1'b0}};
force U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_7.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_ff_1_D_0.mem_out[0:1] = {2{1'b0}};
force U0_formal_verification.grid_io_top_top_1__2_.logical_tile_io_mode_io__0.logical_tile_io_mode_physical__iopad_0.EMBEDDED_IO_HD_sky130_fd_sc_hd__dfrtp_1_mem.mem_out[0] = 1'b1;
force U0_formal_verification.grid_io_top_top_1__2_.logical_tile_io_mode_io__1.logical_tile_io_mode_physical__iopad_0.EMBEDDED_IO_HD_sky130_fd_sc_hd__dfrtp_1_mem.mem_out[0] = 1'b1;
force U0_formal_verification.grid_io_top_top_1__2_.logical_tile_io_mode_io__2.logical_tile_io_mode_physical__iopad_0.EMBEDDED_IO_HD_sky130_fd_sc_hd__dfrtp_1_mem.mem_out[0] = 1'b1;
force U0_formal_verification.grid_io_top_top_1__2_.logical_tile_io_mode_io__3.logical_tile_io_mode_physical__iopad_0.EMBEDDED_IO_HD_sky130_fd_sc_hd__dfrtp_1_mem.mem_out[0] = 1'b1;
force U0_formal_verification.grid_io_top_top_1__2_.logical_tile_io_mode_io__4.logical_tile_io_mode_physical__iopad_0.EMBEDDED_IO_HD_sky130_fd_sc_hd__dfrtp_1_mem.mem_out[0] = 1'b1;
force U0_formal_verification.grid_io_top_top_1__2_.logical_tile_io_mode_io__5.logical_tile_io_mode_physical__iopad_0.EMBEDDED_IO_HD_sky130_fd_sc_hd__dfrtp_1_mem.mem_out[0] = 1'b1;
force U0_formal_verification.grid_io_top_top_1__2_.logical_tile_io_mode_io__6.logical_tile_io_mode_physical__iopad_0.EMBEDDED_IO_HD_sky130_fd_sc_hd__dfrtp_1_mem.mem_out[0] = 1'b1;
force U0_formal_verification.grid_io_top_top_1__2_.logical_tile_io_mode_io__7.logical_tile_io_mode_physical__iopad_0.EMBEDDED_IO_HD_sky130_fd_sc_hd__dfrtp_1_mem.mem_out[0] = 1'b1;
force U0_formal_verification.grid_io_right_right_2__1_.logical_tile_io_mode_io__0.logical_tile_io_mode_physical__iopad_0.EMBEDDED_IO_HD_sky130_fd_sc_hd__dfrtp_1_mem.mem_out[0] = 1'b1;
force U0_formal_verification.grid_io_right_right_2__1_.logical_tile_io_mode_io__1.logical_tile_io_mode_physical__iopad_0.EMBEDDED_IO_HD_sky130_fd_sc_hd__dfrtp_1_mem.mem_out[0] = 1'b1;
force U0_formal_verification.grid_io_right_right_2__1_.logical_tile_io_mode_io__2.logical_tile_io_mode_physical__iopad_0.EMBEDDED_IO_HD_sky130_fd_sc_hd__dfrtp_1_mem.mem_out[0] = 1'b1;
force U0_formal_verification.grid_io_right_right_2__1_.logical_tile_io_mode_io__3.logical_tile_io_mode_physical__iopad_0.EMBEDDED_IO_HD_sky130_fd_sc_hd__dfrtp_1_mem.mem_out[0] = 1'b1;
force U0_formal_verification.grid_io_right_right_2__1_.logical_tile_io_mode_io__4.logical_tile_io_mode_physical__iopad_0.EMBEDDED_IO_HD_sky130_fd_sc_hd__dfrtp_1_mem.mem_out[0] = 1'b1;
force U0_formal_verification.grid_io_right_right_2__1_.logical_tile_io_mode_io__5.logical_tile_io_mode_physical__iopad_0.EMBEDDED_IO_HD_sky130_fd_sc_hd__dfrtp_1_mem.mem_out[0] = 1'b1;
force U0_formal_verification.grid_io_right_right_2__1_.logical_tile_io_mode_io__6.logical_tile_io_mode_physical__iopad_0.EMBEDDED_IO_HD_sky130_fd_sc_hd__dfrtp_1_mem.mem_out[0] = 1'b1;
force U0_formal_verification.grid_io_right_right_2__1_.logical_tile_io_mode_io__7.logical_tile_io_mode_physical__iopad_0.EMBEDDED_IO_HD_sky130_fd_sc_hd__dfrtp_1_mem.mem_out[0] = 1'b1;
force U0_formal_verification.grid_io_bottom_bottom_1__0_.logical_tile_io_mode_io__0.logical_tile_io_mode_physical__iopad_0.EMBEDDED_IO_HD_sky130_fd_sc_hd__dfrtp_1_mem.mem_out[0] = 1'b1;
force U0_formal_verification.grid_io_bottom_bottom_1__0_.logical_tile_io_mode_io__1.logical_tile_io_mode_physical__iopad_0.EMBEDDED_IO_HD_sky130_fd_sc_hd__dfrtp_1_mem.mem_out[0] = 1'b1;
force U0_formal_verification.grid_io_bottom_bottom_1__0_.logical_tile_io_mode_io__2.logical_tile_io_mode_physical__iopad_0.EMBEDDED_IO_HD_sky130_fd_sc_hd__dfrtp_1_mem.mem_out[0] = 1'b1;
force U0_formal_verification.grid_io_bottom_bottom_1__0_.logical_tile_io_mode_io__3.logical_tile_io_mode_physical__iopad_0.EMBEDDED_IO_HD_sky130_fd_sc_hd__dfrtp_1_mem.mem_out[0] = 1'b1;
force U0_formal_verification.grid_io_bottom_bottom_1__0_.logical_tile_io_mode_io__4.logical_tile_io_mode_physical__iopad_0.EMBEDDED_IO_HD_sky130_fd_sc_hd__dfrtp_1_mem.mem_out[0] = 1'b1;
force U0_formal_verification.grid_io_bottom_bottom_1__0_.logical_tile_io_mode_io__5.logical_tile_io_mode_physical__iopad_0.EMBEDDED_IO_HD_sky130_fd_sc_hd__dfrtp_1_mem.mem_out[0] = 1'b1;
force U0_formal_verification.grid_io_bottom_bottom_1__0_.logical_tile_io_mode_io__6.logical_tile_io_mode_physical__iopad_0.EMBEDDED_IO_HD_sky130_fd_sc_hd__dfrtp_1_mem.mem_out[0] = 1'b1;
force U0_formal_verification.grid_io_bottom_bottom_1__0_.logical_tile_io_mode_io__7.logical_tile_io_mode_physical__iopad_0.EMBEDDED_IO_HD_sky130_fd_sc_hd__dfrtp_1_mem.mem_out[0] = 1'b1;
force U0_formal_verification.grid_io_bottom_bottom_1__0_.logical_tile_io_mode_io__8.logical_tile_io_mode_physical__iopad_0.EMBEDDED_IO_HD_sky130_fd_sc_hd__dfrtp_1_mem.mem_out[0] = 1'b0;
force U0_formal_verification.grid_io_left_left_0__1_.logical_tile_io_mode_io__0.logical_tile_io_mode_physical__iopad_0.EMBEDDED_IO_HD_sky130_fd_sc_hd__dfrtp_1_mem.mem_out[0] = 1'b1;
force U0_formal_verification.sb_0__0_.mem_top_track_0.mem_out[0:1] = {2{1'b0}};
force U0_formal_verification.sb_0__0_.mem_top_track_2.mem_out[0:1] = {2{1'b0}};
force U0_formal_verification.sb_0__0_.mem_top_track_4.mem_out[0:1] = {2{1'b0}};
force U0_formal_verification.sb_0__0_.mem_right_track_0.mem_out[0:3] = 4'b0011;
force U0_formal_verification.sb_0__0_.mem_right_track_2.mem_out[0:3] = {4{1'b0}};
force U0_formal_verification.sb_0__0_.mem_right_track_4.mem_out[0:1] = {2{1'b0}};
force U0_formal_verification.sb_0__0_.mem_right_track_6.mem_out[0:1] = {2{1'b0}};
force U0_formal_verification.sb_0__0_.mem_right_track_8.mem_out[0:1] = {2{1'b0}};
force U0_formal_verification.sb_0__0_.mem_right_track_10.mem_out[0:1] = {2{1'b0}};
force U0_formal_verification.sb_0__0_.mem_right_track_12.mem_out[0:1] = {2{1'b0}};
force U0_formal_verification.sb_0__0_.mem_right_track_14.mem_out[0:1] = {2{1'b0}};
force U0_formal_verification.sb_0__0_.mem_right_track_16.mem_out[0:1] = {2{1'b0}};
force U0_formal_verification.sb_0__0_.mem_right_track_18.mem_out[0:1] = {2{1'b0}};
force U0_formal_verification.sb_0__0_.mem_right_track_20.mem_out[0:1] = {2{1'b0}};
force U0_formal_verification.sb_0__1_.mem_right_track_0.mem_out[0:4] = {5{1'b0}};
force U0_formal_verification.sb_0__1_.mem_right_track_2.mem_out[0:4] = 5'b00111;
force U0_formal_verification.sb_0__1_.mem_right_track_4.mem_out[0:1] = {2{1'b0}};
force U0_formal_verification.sb_0__1_.mem_right_track_6.mem_out[0:1] = {2{1'b0}};
force U0_formal_verification.sb_0__1_.mem_right_track_8.mem_out[0:1] = {2{1'b0}};
force U0_formal_verification.sb_0__1_.mem_right_track_10.mem_out[0:1] = {2{1'b0}};
force U0_formal_verification.sb_0__1_.mem_right_track_12.mem_out[0:1] = {2{1'b0}};
force U0_formal_verification.sb_0__1_.mem_right_track_14.mem_out[0:1] = {2{1'b0}};
force U0_formal_verification.sb_0__1_.mem_right_track_16.mem_out[0:1] = {2{1'b0}};
force U0_formal_verification.sb_0__1_.mem_right_track_18.mem_out[0:1] = {2{1'b0}};
force U0_formal_verification.sb_0__1_.mem_right_track_20.mem_out[0:1] = {2{1'b0}};
force U0_formal_verification.sb_0__1_.mem_bottom_track_1.mem_out[0:1] = {2{1'b0}};
force U0_formal_verification.sb_0__1_.mem_bottom_track_3.mem_out[0:1] = {2{1'b0}};
force U0_formal_verification.sb_0__1_.mem_bottom_track_5.mem_out[0:1] = {2{1'b0}};
force U0_formal_verification.sb_1__0_.mem_top_track_0.mem_out[0:4] = 5'b01000;
force U0_formal_verification.sb_1__0_.mem_top_track_2.mem_out[0:4] = {5{1'b0}};
force U0_formal_verification.sb_1__0_.mem_top_track_4.mem_out[0:1] = {2{1'b0}};
force U0_formal_verification.sb_1__0_.mem_top_track_6.mem_out[0:1] = {2{1'b0}};
force U0_formal_verification.sb_1__0_.mem_top_track_8.mem_out[0:1] = {2{1'b0}};
force U0_formal_verification.sb_1__0_.mem_top_track_10.mem_out[0:1] = {2{1'b0}};
force U0_formal_verification.sb_1__0_.mem_top_track_12.mem_out[0:1] = {2{1'b0}};
force U0_formal_verification.sb_1__0_.mem_top_track_14.mem_out[0:1] = {2{1'b0}};
force U0_formal_verification.sb_1__0_.mem_top_track_16.mem_out[0:1] = {2{1'b0}};
force U0_formal_verification.sb_1__0_.mem_top_track_18.mem_out[0:1] = {2{1'b0}};
force U0_formal_verification.sb_1__0_.mem_top_track_20.mem_out[0:1] = {2{1'b0}};
force U0_formal_verification.sb_1__0_.mem_left_track_1.mem_out[0:3] = {4{1'b0}};
force U0_formal_verification.sb_1__0_.mem_left_track_3.mem_out[0:3] = {4{1'b0}};
force U0_formal_verification.sb_1__0_.mem_left_track_5.mem_out[0:1] = {2{1'b0}};
force U0_formal_verification.sb_1__0_.mem_left_track_7.mem_out[0:1] = {2{1'b0}};
force U0_formal_verification.sb_1__0_.mem_left_track_9.mem_out[0:1] = {2{1'b0}};
force U0_formal_verification.sb_1__0_.mem_left_track_11.mem_out[0:1] = {2{1'b0}};
force U0_formal_verification.sb_1__0_.mem_left_track_13.mem_out[0:1] = {2{1'b0}};
force U0_formal_verification.sb_1__0_.mem_left_track_15.mem_out[0:1] = {2{1'b0}};
force U0_formal_verification.sb_1__0_.mem_left_track_17.mem_out[0:1] = {2{1'b0}};
force U0_formal_verification.sb_1__0_.mem_left_track_19.mem_out[0:1] = {2{1'b0}};
force U0_formal_verification.sb_1__0_.mem_left_track_21.mem_out[0:1] = {2{1'b1}};
force U0_formal_verification.sb_1__1_.mem_bottom_track_1.mem_out[0:4] = 5'b01000;
force U0_formal_verification.sb_1__1_.mem_bottom_track_3.mem_out[0:4] = 5'b00100;
force U0_formal_verification.sb_1__1_.mem_bottom_track_5.mem_out[0:1] = {2{1'b0}};
force U0_formal_verification.sb_1__1_.mem_bottom_track_7.mem_out[0:1] = {2{1'b0}};
force U0_formal_verification.sb_1__1_.mem_bottom_track_9.mem_out[0:1] = {2{1'b0}};
force U0_formal_verification.sb_1__1_.mem_bottom_track_11.mem_out[0:1] = {2{1'b0}};
force U0_formal_verification.sb_1__1_.mem_bottom_track_13.mem_out[0:1] = {2{1'b0}};
force U0_formal_verification.sb_1__1_.mem_bottom_track_15.mem_out[0:1] = {2{1'b0}};
force U0_formal_verification.sb_1__1_.mem_bottom_track_17.mem_out[0:1] = {2{1'b0}};
force U0_formal_verification.sb_1__1_.mem_bottom_track_19.mem_out[0:1] = {2{1'b0}};
force U0_formal_verification.sb_1__1_.mem_bottom_track_21.mem_out[0:1] = {2{1'b0}};
force U0_formal_verification.sb_1__1_.mem_left_track_1.mem_out[0:4] = {5{1'b0}};
force U0_formal_verification.sb_1__1_.mem_left_track_3.mem_out[0:4] = {5{1'b0}};
force U0_formal_verification.sb_1__1_.mem_left_track_5.mem_out[0:1] = {2{1'b0}};
force U0_formal_verification.sb_1__1_.mem_left_track_7.mem_out[0:1] = {2{1'b0}};
force U0_formal_verification.sb_1__1_.mem_left_track_9.mem_out[0:1] = {2{1'b0}};
force U0_formal_verification.sb_1__1_.mem_left_track_11.mem_out[0:1] = {2{1'b0}};
force U0_formal_verification.sb_1__1_.mem_left_track_13.mem_out[0:1] = {2{1'b0}};
force U0_formal_verification.sb_1__1_.mem_left_track_15.mem_out[0:1] = {2{1'b0}};
force U0_formal_verification.sb_1__1_.mem_left_track_17.mem_out[0:1] = {2{1'b0}};
force U0_formal_verification.sb_1__1_.mem_left_track_19.mem_out[0:1] = {2{1'b0}};
force U0_formal_verification.sb_1__1_.mem_left_track_21.mem_out[0:1] = {2{1'b0}};
force U0_formal_verification.cbx_1__0_.mem_top_ipin_0.mem_out[0:3] = {4{1'b0}};
force U0_formal_verification.cbx_1__0_.mem_top_ipin_1.mem_out[0:3] = {4{1'b0}};
force U0_formal_verification.cbx_1__0_.mem_top_ipin_2.mem_out[0:3] = {4{1'b0}};
force U0_formal_verification.cbx_1__0_.mem_top_ipin_3.mem_out[0:3] = {4{1'b0}};
force U0_formal_verification.cbx_1__0_.mem_top_ipin_4.mem_out[0:3] = {4{1'b0}};
force U0_formal_verification.cbx_1__0_.mem_top_ipin_5.mem_out[0:3] = {4{1'b0}};
force U0_formal_verification.cbx_1__0_.mem_top_ipin_6.mem_out[0:3] = {4{1'b0}};
force U0_formal_verification.cbx_1__0_.mem_top_ipin_7.mem_out[0:3] = {4{1'b0}};
force U0_formal_verification.cbx_1__0_.mem_top_ipin_8.mem_out[0:3] = 4'b0100;
force U0_formal_verification.cbx_1__1_.mem_bottom_ipin_0.mem_out[0:3] = {4{1'b0}};
force U0_formal_verification.cbx_1__1_.mem_bottom_ipin_1.mem_out[0:3] = {4{1'b0}};
force U0_formal_verification.cbx_1__1_.mem_bottom_ipin_2.mem_out[0:3] = {4{1'b0}};
force U0_formal_verification.cbx_1__1_.mem_bottom_ipin_3.mem_out[0:3] = {4{1'b0}};
force U0_formal_verification.cbx_1__1_.mem_bottom_ipin_4.mem_out[0:3] = {4{1'b0}};
force U0_formal_verification.cbx_1__1_.mem_bottom_ipin_5.mem_out[0:3] = {4{1'b0}};
force U0_formal_verification.cbx_1__1_.mem_bottom_ipin_6.mem_out[0:3] = {4{1'b0}};
force U0_formal_verification.cbx_1__1_.mem_bottom_ipin_7.mem_out[0:3] = {4{1'b0}};
force U0_formal_verification.cbx_1__1_.mem_top_ipin_0.mem_out[0:3] = {4{1'b0}};
force U0_formal_verification.cbx_1__1_.mem_top_ipin_1.mem_out[0:2] = {3{1'b0}};
force U0_formal_verification.cbx_1__1_.mem_top_ipin_2.mem_out[0:3] = {4{1'b0}};
force U0_formal_verification.cbx_1__1_.mem_top_ipin_3.mem_out[0:2] = {3{1'b0}};
force U0_formal_verification.cbx_1__1_.mem_top_ipin_4.mem_out[0:3] = {4{1'b0}};
force U0_formal_verification.cbx_1__1_.mem_top_ipin_5.mem_out[0:2] = {3{1'b0}};
force U0_formal_verification.cbx_1__1_.mem_top_ipin_6.mem_out[0:3] = {4{1'b0}};
force U0_formal_verification.cbx_1__1_.mem_top_ipin_7.mem_out[0:2] = {3{1'b0}};
force U0_formal_verification.cbx_1__1_.mem_top_ipin_8.mem_out[0:3] = {4{1'b0}};
force U0_formal_verification.cbx_1__1_.mem_top_ipin_9.mem_out[0:2] = {3{1'b0}};
force U0_formal_verification.cbx_1__1_.mem_top_ipin_10.mem_out[0:3] = {4{1'b0}};
force U0_formal_verification.cbx_1__1_.mem_top_ipin_11.mem_out[0:2] = {3{1'b0}};
force U0_formal_verification.cbx_1__1_.mem_top_ipin_12.mem_out[0:3] = {4{1'b0}};
force U0_formal_verification.cbx_1__1_.mem_top_ipin_13.mem_out[0:2] = {3{1'b0}};
force U0_formal_verification.cbx_1__1_.mem_top_ipin_14.mem_out[0:3] = {4{1'b0}};
force U0_formal_verification.cbx_1__1_.mem_top_ipin_15.mem_out[0:2] = {3{1'b0}};
force U0_formal_verification.cby_0__1_.mem_right_ipin_0.mem_out[0:3] = {4{1'b0}};
force U0_formal_verification.cby_1__1_.mem_left_ipin_0.mem_out[0:3] = {4{1'b0}};
force U0_formal_verification.cby_1__1_.mem_left_ipin_1.mem_out[0:3] = {4{1'b0}};
force U0_formal_verification.cby_1__1_.mem_left_ipin_2.mem_out[0:3] = {4{1'b0}};
force U0_formal_verification.cby_1__1_.mem_left_ipin_3.mem_out[0:3] = {4{1'b0}};
force U0_formal_verification.cby_1__1_.mem_left_ipin_4.mem_out[0:3] = {4{1'b0}};
force U0_formal_verification.cby_1__1_.mem_left_ipin_5.mem_out[0:3] = {4{1'b0}};
force U0_formal_verification.cby_1__1_.mem_left_ipin_6.mem_out[0:3] = {4{1'b0}};
force U0_formal_verification.cby_1__1_.mem_left_ipin_7.mem_out[0:3] = {4{1'b0}};
force U0_formal_verification.cby_1__1_.mem_right_ipin_0.mem_out[0:3] = {4{1'b0}};
force U0_formal_verification.cby_1__1_.mem_right_ipin_1.mem_out[0:2] = {3{1'b0}};
force U0_formal_verification.cby_1__1_.mem_right_ipin_2.mem_out[0:3] = {4{1'b0}};
force U0_formal_verification.cby_1__1_.mem_right_ipin_3.mem_out[0:2] = {3{1'b0}};
force U0_formal_verification.cby_1__1_.mem_right_ipin_4.mem_out[0:3] = {4{1'b0}};
force U0_formal_verification.cby_1__1_.mem_right_ipin_5.mem_out[0:2] = {3{1'b0}};
force U0_formal_verification.cby_1__1_.mem_right_ipin_6.mem_out[0:3] = {4{1'b0}};
force U0_formal_verification.cby_1__1_.mem_right_ipin_7.mem_out[0:2] = {3{1'b0}};
force U0_formal_verification.cby_1__1_.mem_right_ipin_8.mem_out[0:3] = {4{1'b0}};
force U0_formal_verification.cby_1__1_.mem_right_ipin_9.mem_out[0:2] = {3{1'b0}};
force U0_formal_verification.cby_1__1_.mem_right_ipin_10.mem_out[0:3] = {4{1'b0}};
force U0_formal_verification.cby_1__1_.mem_right_ipin_11.mem_out[0:2] = {3{1'b0}};
force U0_formal_verification.cby_1__1_.mem_right_ipin_12.mem_out[0:3] = {4{1'b0}};
force U0_formal_verification.cby_1__1_.mem_right_ipin_13.mem_out[0:2] = 3'b011;
force U0_formal_verification.cby_1__1_.mem_right_ipin_14.mem_out[0:3] = {4{1'b1}};
force U0_formal_verification.cby_1__1_.mem_right_ipin_15.mem_out[0:2] = {3{1'b0}};
end
// ----- End assign bitstream to configuration memories -----
// ----- End load bitstream to configuration memories -----
endmodule
// ----- END Verilog module for top_top_formal_verification -----
//----- Default net type -----
`default_nettype none

51
SOFA_A/config.sh Normal file
View File

@ -0,0 +1,51 @@
# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
# = = = = = = = = = = = = = = Variables Sections = = = = = = = = = = = = = = =
# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
export PROJ_NAME=FPGA1212_QLSOFA_HD # Project Name
export FPGA_SIZE_X=12 # Grid X Size
export FPGA_SIZE_Y=12 # Grid Y Size
# Design Style [hier/flat], mostly hier
export DESIGN_STYLE=hier
export TECHNOLOGY="skywater"
# Complete Chip (fpga_top) or eFPGA (fpga_core)
export DESIGN_NAME=fpga_core
# Pin Information Source Automatic or Sheet
export PIN_MAP=Automatic
export PIN_MAP_CSV_SPREADSHEET_LINK="" # Required only if PIN_MAP==Sheet
# Core Dimension, requires if DESIGN_NAME=fpga_core
# if DESIGN_NAME=fpga_top its Optional if defined it overrides the
# Calculated DIE_DIMENSION
export DIE_DIMENSION=3200
# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
# Derived Or Fixed Variables
# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
export OPENFPGA_ENGINE_PATH=${OPENFPGA_PATH}
export TASK_DIR_NAME=${PROJ_NAME}_task
export VERILOG_PROJ_DIR=${PROJ_NAME}_Verilog
export SPY_HACK_FILE=${TASK_DIR_NAME}/spy_hack.txt
export POST_OPENFPGA_SCRIPT=./PostOpenFPGAScript.sh
export RESTRUCT_NETLIST=../utils/RestructureNetlistSkywater.py
export POST_GENERATION_SCRIPT=./generate_scandef_and_case_analysis.sh
export TAPEOUT_DIRECTORY=/research/ece/lnis/USERS/DARPA_ERI/Tapeout/SOFA
export TAPEOUT_SCRIPT=
# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
# Restructure Netlist Varaibles
# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
# export RESTRUCTURE_skipClockRestructure=""
# export RESTRUCTURE_Skeleton=""
# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
# PNR RELATED FLOW
# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
export INIT_DESIGN_INPUT="ASCII"
# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
# Extra variables availble during flow (suuffix FLOWVAR_)
# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
export FLOWVAR_STANDARD_CELLS="sc_hd"