mirror of https://github.com/lnis-uofu/SOFA.git
915 lines
22 KiB
Verilog
915 lines
22 KiB
Verilog
//-------------------------------------------
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// FPGA Synthesizable Verilog Netlist
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// Description: Multiplexers
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// Author: Xifan TANG
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// Organization: University of Utah
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// Date: Sun Feb 19 10:53:27 2023
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//-------------------------------------------
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//----- Time scale -----
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`timescale 1ns / 1ps
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//----- Default net type -----
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`default_nettype none
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// ----- Verilog module for mux_tree_tapbuf_size10 -----
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module mux_tree_tapbuf_size10(in,
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sram,
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sram_inv,
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out);
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//----- INPUT PORTS -----
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input [0:9] in;
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//----- INPUT PORTS -----
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input [0:3] sram;
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//----- INPUT PORTS -----
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input [0:3] sram_inv;
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//----- OUTPUT PORTS -----
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output [0:0] out;
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//----- BEGIN wire-connection ports -----
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//----- END wire-connection ports -----
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//----- BEGIN Registered ports -----
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//----- END Registered ports -----
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wire [0:0] const1_0_const1;
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wire [0:0] sky130_fd_sc_hd__mux2_1_0_X;
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wire [0:0] sky130_fd_sc_hd__mux2_1_1_X;
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wire [0:0] sky130_fd_sc_hd__mux2_1_2_X;
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wire [0:0] sky130_fd_sc_hd__mux2_1_3_X;
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wire [0:0] sky130_fd_sc_hd__mux2_1_4_X;
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wire [0:0] sky130_fd_sc_hd__mux2_1_5_X;
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wire [0:0] sky130_fd_sc_hd__mux2_1_6_X;
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wire [0:0] sky130_fd_sc_hd__mux2_1_7_X;
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wire [0:0] sky130_fd_sc_hd__mux2_1_8_X;
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wire [0:0] sky130_fd_sc_hd__mux2_1_9_X;
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// ----- BEGIN Local short connections -----
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// ----- END Local short connections -----
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// ----- BEGIN Local output short connections -----
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// ----- END Local output short connections -----
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const1 const1_0_ (
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.const1(const1_0_const1));
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sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ (
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.A(sky130_fd_sc_hd__mux2_1_9_X),
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.X(out));
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sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ (
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.A1(in[0]),
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.A0(in[1]),
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.S(sram[0]),
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.X(sky130_fd_sc_hd__mux2_1_0_X));
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sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ (
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.A1(in[2]),
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.A0(in[3]),
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.S(sram[0]),
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.X(sky130_fd_sc_hd__mux2_1_1_X));
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sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ (
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.A1(in[4]),
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.A0(in[5]),
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.S(sram[0]),
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.X(sky130_fd_sc_hd__mux2_1_2_X));
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sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ (
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.A1(sky130_fd_sc_hd__mux2_1_0_X),
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.A0(sky130_fd_sc_hd__mux2_1_1_X),
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.S(sram[1]),
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.X(sky130_fd_sc_hd__mux2_1_3_X));
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sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ (
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.A1(sky130_fd_sc_hd__mux2_1_2_X),
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.A0(in[6]),
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.S(sram[1]),
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.X(sky130_fd_sc_hd__mux2_1_4_X));
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sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ (
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.A1(in[7]),
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.A0(in[8]),
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.S(sram[1]),
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.X(sky130_fd_sc_hd__mux2_1_5_X));
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sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ (
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.A1(in[9]),
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.A0(const1_0_const1),
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.S(sram[1]),
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.X(sky130_fd_sc_hd__mux2_1_6_X));
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sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ (
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.A1(sky130_fd_sc_hd__mux2_1_3_X),
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.A0(sky130_fd_sc_hd__mux2_1_4_X),
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.S(sram[2]),
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.X(sky130_fd_sc_hd__mux2_1_7_X));
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sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ (
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.A1(sky130_fd_sc_hd__mux2_1_5_X),
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.A0(sky130_fd_sc_hd__mux2_1_6_X),
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.S(sram[2]),
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.X(sky130_fd_sc_hd__mux2_1_8_X));
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sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ (
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.A1(sky130_fd_sc_hd__mux2_1_7_X),
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.A0(sky130_fd_sc_hd__mux2_1_8_X),
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.S(sram[3]),
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.X(sky130_fd_sc_hd__mux2_1_9_X));
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endmodule
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// ----- END Verilog module for mux_tree_tapbuf_size10 -----
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//----- Default net type -----
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`default_nettype none
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//----- Default net type -----
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`default_nettype none
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// ----- Verilog module for mux_tree_tapbuf_size6 -----
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module mux_tree_tapbuf_size6(in,
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sram,
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sram_inv,
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out);
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//----- INPUT PORTS -----
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input [0:5] in;
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//----- INPUT PORTS -----
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input [0:2] sram;
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//----- INPUT PORTS -----
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input [0:2] sram_inv;
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//----- OUTPUT PORTS -----
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output [0:0] out;
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//----- BEGIN wire-connection ports -----
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//----- END wire-connection ports -----
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//----- BEGIN Registered ports -----
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//----- END Registered ports -----
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wire [0:0] const1_0_const1;
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wire [0:0] sky130_fd_sc_hd__mux2_1_0_X;
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wire [0:0] sky130_fd_sc_hd__mux2_1_1_X;
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wire [0:0] sky130_fd_sc_hd__mux2_1_2_X;
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wire [0:0] sky130_fd_sc_hd__mux2_1_3_X;
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wire [0:0] sky130_fd_sc_hd__mux2_1_4_X;
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wire [0:0] sky130_fd_sc_hd__mux2_1_5_X;
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// ----- BEGIN Local short connections -----
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// ----- END Local short connections -----
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// ----- BEGIN Local output short connections -----
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// ----- END Local output short connections -----
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const1 const1_0_ (
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.const1(const1_0_const1));
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sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ (
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.A(sky130_fd_sc_hd__mux2_1_5_X),
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.X(out));
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sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ (
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.A1(in[0]),
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.A0(in[1]),
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.S(sram[0]),
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.X(sky130_fd_sc_hd__mux2_1_0_X));
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sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ (
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.A1(in[2]),
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.A0(in[3]),
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.S(sram[0]),
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.X(sky130_fd_sc_hd__mux2_1_1_X));
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sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ (
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.A1(in[4]),
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.A0(in[5]),
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.S(sram[0]),
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.X(sky130_fd_sc_hd__mux2_1_2_X));
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sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ (
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.A1(sky130_fd_sc_hd__mux2_1_0_X),
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.A0(sky130_fd_sc_hd__mux2_1_1_X),
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.S(sram[1]),
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.X(sky130_fd_sc_hd__mux2_1_3_X));
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sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ (
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.A1(sky130_fd_sc_hd__mux2_1_2_X),
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.A0(const1_0_const1),
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.S(sram[1]),
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.X(sky130_fd_sc_hd__mux2_1_4_X));
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sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ (
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.A1(sky130_fd_sc_hd__mux2_1_3_X),
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.A0(sky130_fd_sc_hd__mux2_1_4_X),
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.S(sram[2]),
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.X(sky130_fd_sc_hd__mux2_1_5_X));
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endmodule
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// ----- END Verilog module for mux_tree_tapbuf_size6 -----
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//----- Default net type -----
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`default_nettype none
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//----- Default net type -----
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`default_nettype none
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// ----- Verilog module for mux_tree_tapbuf_size2 -----
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module mux_tree_tapbuf_size2(in,
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sram,
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sram_inv,
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out);
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//----- INPUT PORTS -----
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input [0:1] in;
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//----- INPUT PORTS -----
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input [0:1] sram;
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//----- INPUT PORTS -----
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input [0:1] sram_inv;
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//----- OUTPUT PORTS -----
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output [0:0] out;
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//----- BEGIN wire-connection ports -----
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//----- END wire-connection ports -----
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//----- BEGIN Registered ports -----
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//----- END Registered ports -----
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wire [0:0] const1_0_const1;
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wire [0:0] sky130_fd_sc_hd__mux2_1_0_X;
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wire [0:0] sky130_fd_sc_hd__mux2_1_1_X;
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// ----- BEGIN Local short connections -----
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// ----- END Local short connections -----
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// ----- BEGIN Local output short connections -----
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// ----- END Local output short connections -----
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const1 const1_0_ (
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.const1(const1_0_const1));
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sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ (
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.A(sky130_fd_sc_hd__mux2_1_1_X),
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.X(out));
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sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ (
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.A1(in[0]),
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.A0(in[1]),
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.S(sram[0]),
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.X(sky130_fd_sc_hd__mux2_1_0_X));
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sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ (
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.A1(sky130_fd_sc_hd__mux2_1_0_X),
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.A0(const1_0_const1),
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.S(sram[1]),
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.X(sky130_fd_sc_hd__mux2_1_1_X));
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endmodule
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// ----- END Verilog module for mux_tree_tapbuf_size2 -----
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//----- Default net type -----
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`default_nettype none
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//----- Default net type -----
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`default_nettype none
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// ----- Verilog module for mux_tree_tapbuf_size17 -----
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module mux_tree_tapbuf_size17(in,
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sram,
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sram_inv,
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out);
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//----- INPUT PORTS -----
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input [0:16] in;
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//----- INPUT PORTS -----
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input [0:4] sram;
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//----- INPUT PORTS -----
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input [0:4] sram_inv;
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//----- OUTPUT PORTS -----
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output [0:0] out;
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//----- BEGIN wire-connection ports -----
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//----- END wire-connection ports -----
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//----- BEGIN Registered ports -----
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//----- END Registered ports -----
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wire [0:0] const1_0_const1;
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wire [0:0] sky130_fd_sc_hd__mux2_1_0_X;
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wire [0:0] sky130_fd_sc_hd__mux2_1_10_X;
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wire [0:0] sky130_fd_sc_hd__mux2_1_11_X;
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wire [0:0] sky130_fd_sc_hd__mux2_1_12_X;
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wire [0:0] sky130_fd_sc_hd__mux2_1_13_X;
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wire [0:0] sky130_fd_sc_hd__mux2_1_14_X;
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wire [0:0] sky130_fd_sc_hd__mux2_1_15_X;
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wire [0:0] sky130_fd_sc_hd__mux2_1_16_X;
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wire [0:0] sky130_fd_sc_hd__mux2_1_1_X;
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wire [0:0] sky130_fd_sc_hd__mux2_1_2_X;
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wire [0:0] sky130_fd_sc_hd__mux2_1_3_X;
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wire [0:0] sky130_fd_sc_hd__mux2_1_4_X;
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wire [0:0] sky130_fd_sc_hd__mux2_1_5_X;
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wire [0:0] sky130_fd_sc_hd__mux2_1_6_X;
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wire [0:0] sky130_fd_sc_hd__mux2_1_7_X;
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wire [0:0] sky130_fd_sc_hd__mux2_1_8_X;
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wire [0:0] sky130_fd_sc_hd__mux2_1_9_X;
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// ----- BEGIN Local short connections -----
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// ----- END Local short connections -----
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// ----- BEGIN Local output short connections -----
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// ----- END Local output short connections -----
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const1 const1_0_ (
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.const1(const1_0_const1));
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sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ (
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.A(sky130_fd_sc_hd__mux2_1_16_X),
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.X(out));
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sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ (
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.A1(in[0]),
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.A0(in[1]),
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.S(sram[0]),
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.X(sky130_fd_sc_hd__mux2_1_0_X));
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sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ (
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.A1(in[2]),
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.A0(in[3]),
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.S(sram[0]),
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.X(sky130_fd_sc_hd__mux2_1_1_X));
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sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ (
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.A1(sky130_fd_sc_hd__mux2_1_0_X),
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.A0(sky130_fd_sc_hd__mux2_1_1_X),
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.S(sram[1]),
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.X(sky130_fd_sc_hd__mux2_1_2_X));
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sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ (
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.A1(in[4]),
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.A0(in[5]),
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.S(sram[1]),
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.X(sky130_fd_sc_hd__mux2_1_3_X));
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sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ (
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.A1(in[6]),
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.A0(in[7]),
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.S(sram[1]),
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.X(sky130_fd_sc_hd__mux2_1_4_X));
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sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ (
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.A1(in[8]),
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.A0(in[9]),
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.S(sram[1]),
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.X(sky130_fd_sc_hd__mux2_1_5_X));
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sky130_fd_sc_hd__mux2_1 mux_l2_in_4_ (
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.A1(in[10]),
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.A0(in[11]),
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.S(sram[1]),
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.X(sky130_fd_sc_hd__mux2_1_6_X));
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sky130_fd_sc_hd__mux2_1 mux_l2_in_5_ (
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.A1(in[12]),
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.A0(in[13]),
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.S(sram[1]),
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.X(sky130_fd_sc_hd__mux2_1_7_X));
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sky130_fd_sc_hd__mux2_1 mux_l2_in_6_ (
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.A1(in[14]),
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.A0(in[15]),
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.S(sram[1]),
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.X(sky130_fd_sc_hd__mux2_1_8_X));
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sky130_fd_sc_hd__mux2_1 mux_l2_in_7_ (
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.A1(in[16]),
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.A0(const1_0_const1),
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.S(sram[1]),
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.X(sky130_fd_sc_hd__mux2_1_9_X));
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sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ (
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.A1(sky130_fd_sc_hd__mux2_1_2_X),
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.A0(sky130_fd_sc_hd__mux2_1_3_X),
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.S(sram[2]),
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.X(sky130_fd_sc_hd__mux2_1_10_X));
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sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ (
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.A1(sky130_fd_sc_hd__mux2_1_4_X),
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.A0(sky130_fd_sc_hd__mux2_1_5_X),
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.S(sram[2]),
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.X(sky130_fd_sc_hd__mux2_1_11_X));
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sky130_fd_sc_hd__mux2_1 mux_l3_in_2_ (
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.A1(sky130_fd_sc_hd__mux2_1_6_X),
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.A0(sky130_fd_sc_hd__mux2_1_7_X),
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.S(sram[2]),
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.X(sky130_fd_sc_hd__mux2_1_12_X));
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sky130_fd_sc_hd__mux2_1 mux_l3_in_3_ (
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.A1(sky130_fd_sc_hd__mux2_1_8_X),
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.A0(sky130_fd_sc_hd__mux2_1_9_X),
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.S(sram[2]),
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.X(sky130_fd_sc_hd__mux2_1_13_X));
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sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ (
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.A1(sky130_fd_sc_hd__mux2_1_10_X),
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.A0(sky130_fd_sc_hd__mux2_1_11_X),
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.S(sram[3]),
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.X(sky130_fd_sc_hd__mux2_1_14_X));
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sky130_fd_sc_hd__mux2_1 mux_l4_in_1_ (
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.A1(sky130_fd_sc_hd__mux2_1_12_X),
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.A0(sky130_fd_sc_hd__mux2_1_13_X),
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.S(sram[3]),
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.X(sky130_fd_sc_hd__mux2_1_15_X));
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|
|
sky130_fd_sc_hd__mux2_1 mux_l5_in_0_ (
|
|
.A1(sky130_fd_sc_hd__mux2_1_14_X),
|
|
.A0(sky130_fd_sc_hd__mux2_1_15_X),
|
|
.S(sram[4]),
|
|
.X(sky130_fd_sc_hd__mux2_1_16_X));
|
|
|
|
endmodule
|
|
// ----- END Verilog module for mux_tree_tapbuf_size17 -----
|
|
|
|
//----- Default net type -----
|
|
`default_nettype none
|
|
|
|
|
|
|
|
|
|
//----- Default net type -----
|
|
`default_nettype none
|
|
|
|
// ----- Verilog module for mux_tree_tapbuf_size3 -----
|
|
module mux_tree_tapbuf_size3(in,
|
|
sram,
|
|
sram_inv,
|
|
out);
|
|
//----- INPUT PORTS -----
|
|
input [0:2] in;
|
|
//----- INPUT PORTS -----
|
|
input [0:1] sram;
|
|
//----- INPUT PORTS -----
|
|
input [0:1] sram_inv;
|
|
//----- OUTPUT PORTS -----
|
|
output [0:0] out;
|
|
|
|
//----- BEGIN wire-connection ports -----
|
|
//----- END wire-connection ports -----
|
|
|
|
|
|
//----- BEGIN Registered ports -----
|
|
//----- END Registered ports -----
|
|
|
|
|
|
wire [0:0] const1_0_const1;
|
|
wire [0:0] sky130_fd_sc_hd__mux2_1_0_X;
|
|
wire [0:0] sky130_fd_sc_hd__mux2_1_1_X;
|
|
wire [0:0] sky130_fd_sc_hd__mux2_1_2_X;
|
|
|
|
// ----- BEGIN Local short connections -----
|
|
// ----- END Local short connections -----
|
|
// ----- BEGIN Local output short connections -----
|
|
// ----- END Local output short connections -----
|
|
|
|
const1 const1_0_ (
|
|
.const1(const1_0_const1));
|
|
|
|
sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ (
|
|
.A(sky130_fd_sc_hd__mux2_1_2_X),
|
|
.X(out));
|
|
|
|
sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ (
|
|
.A1(in[0]),
|
|
.A0(in[1]),
|
|
.S(sram[0]),
|
|
.X(sky130_fd_sc_hd__mux2_1_0_X));
|
|
|
|
sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ (
|
|
.A1(in[2]),
|
|
.A0(const1_0_const1),
|
|
.S(sram[0]),
|
|
.X(sky130_fd_sc_hd__mux2_1_1_X));
|
|
|
|
sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ (
|
|
.A1(sky130_fd_sc_hd__mux2_1_0_X),
|
|
.A0(sky130_fd_sc_hd__mux2_1_1_X),
|
|
.S(sram[1]),
|
|
.X(sky130_fd_sc_hd__mux2_1_2_X));
|
|
|
|
endmodule
|
|
// ----- END Verilog module for mux_tree_tapbuf_size3 -----
|
|
|
|
//----- Default net type -----
|
|
`default_nettype none
|
|
|
|
|
|
|
|
|
|
//----- Default net type -----
|
|
`default_nettype none
|
|
|
|
// ----- Verilog module for mux_tree_tapbuf_size16 -----
|
|
module mux_tree_tapbuf_size16(in,
|
|
sram,
|
|
sram_inv,
|
|
out);
|
|
//----- INPUT PORTS -----
|
|
input [0:15] in;
|
|
//----- INPUT PORTS -----
|
|
input [0:4] sram;
|
|
//----- INPUT PORTS -----
|
|
input [0:4] sram_inv;
|
|
//----- OUTPUT PORTS -----
|
|
output [0:0] out;
|
|
|
|
//----- BEGIN wire-connection ports -----
|
|
//----- END wire-connection ports -----
|
|
|
|
|
|
//----- BEGIN Registered ports -----
|
|
//----- END Registered ports -----
|
|
|
|
|
|
wire [0:0] const1_0_const1;
|
|
wire [0:0] sky130_fd_sc_hd__mux2_1_0_X;
|
|
wire [0:0] sky130_fd_sc_hd__mux2_1_10_X;
|
|
wire [0:0] sky130_fd_sc_hd__mux2_1_11_X;
|
|
wire [0:0] sky130_fd_sc_hd__mux2_1_12_X;
|
|
wire [0:0] sky130_fd_sc_hd__mux2_1_13_X;
|
|
wire [0:0] sky130_fd_sc_hd__mux2_1_14_X;
|
|
wire [0:0] sky130_fd_sc_hd__mux2_1_15_X;
|
|
wire [0:0] sky130_fd_sc_hd__mux2_1_1_X;
|
|
wire [0:0] sky130_fd_sc_hd__mux2_1_2_X;
|
|
wire [0:0] sky130_fd_sc_hd__mux2_1_3_X;
|
|
wire [0:0] sky130_fd_sc_hd__mux2_1_4_X;
|
|
wire [0:0] sky130_fd_sc_hd__mux2_1_5_X;
|
|
wire [0:0] sky130_fd_sc_hd__mux2_1_6_X;
|
|
wire [0:0] sky130_fd_sc_hd__mux2_1_7_X;
|
|
wire [0:0] sky130_fd_sc_hd__mux2_1_8_X;
|
|
wire [0:0] sky130_fd_sc_hd__mux2_1_9_X;
|
|
|
|
// ----- BEGIN Local short connections -----
|
|
// ----- END Local short connections -----
|
|
// ----- BEGIN Local output short connections -----
|
|
// ----- END Local output short connections -----
|
|
|
|
const1 const1_0_ (
|
|
.const1(const1_0_const1));
|
|
|
|
sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ (
|
|
.A(sky130_fd_sc_hd__mux2_1_15_X),
|
|
.X(out));
|
|
|
|
sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ (
|
|
.A1(in[0]),
|
|
.A0(in[1]),
|
|
.S(sram[0]),
|
|
.X(sky130_fd_sc_hd__mux2_1_0_X));
|
|
|
|
sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ (
|
|
.A1(sky130_fd_sc_hd__mux2_1_0_X),
|
|
.A0(in[2]),
|
|
.S(sram[1]),
|
|
.X(sky130_fd_sc_hd__mux2_1_1_X));
|
|
|
|
sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ (
|
|
.A1(in[3]),
|
|
.A0(in[4]),
|
|
.S(sram[1]),
|
|
.X(sky130_fd_sc_hd__mux2_1_2_X));
|
|
|
|
sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ (
|
|
.A1(in[5]),
|
|
.A0(in[6]),
|
|
.S(sram[1]),
|
|
.X(sky130_fd_sc_hd__mux2_1_3_X));
|
|
|
|
sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ (
|
|
.A1(in[7]),
|
|
.A0(in[8]),
|
|
.S(sram[1]),
|
|
.X(sky130_fd_sc_hd__mux2_1_4_X));
|
|
|
|
sky130_fd_sc_hd__mux2_1 mux_l2_in_4_ (
|
|
.A1(in[9]),
|
|
.A0(in[10]),
|
|
.S(sram[1]),
|
|
.X(sky130_fd_sc_hd__mux2_1_5_X));
|
|
|
|
sky130_fd_sc_hd__mux2_1 mux_l2_in_5_ (
|
|
.A1(in[11]),
|
|
.A0(in[12]),
|
|
.S(sram[1]),
|
|
.X(sky130_fd_sc_hd__mux2_1_6_X));
|
|
|
|
sky130_fd_sc_hd__mux2_1 mux_l2_in_6_ (
|
|
.A1(in[13]),
|
|
.A0(in[14]),
|
|
.S(sram[1]),
|
|
.X(sky130_fd_sc_hd__mux2_1_7_X));
|
|
|
|
sky130_fd_sc_hd__mux2_1 mux_l2_in_7_ (
|
|
.A1(in[15]),
|
|
.A0(const1_0_const1),
|
|
.S(sram[1]),
|
|
.X(sky130_fd_sc_hd__mux2_1_8_X));
|
|
|
|
sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ (
|
|
.A1(sky130_fd_sc_hd__mux2_1_1_X),
|
|
.A0(sky130_fd_sc_hd__mux2_1_2_X),
|
|
.S(sram[2]),
|
|
.X(sky130_fd_sc_hd__mux2_1_9_X));
|
|
|
|
sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ (
|
|
.A1(sky130_fd_sc_hd__mux2_1_3_X),
|
|
.A0(sky130_fd_sc_hd__mux2_1_4_X),
|
|
.S(sram[2]),
|
|
.X(sky130_fd_sc_hd__mux2_1_10_X));
|
|
|
|
sky130_fd_sc_hd__mux2_1 mux_l3_in_2_ (
|
|
.A1(sky130_fd_sc_hd__mux2_1_5_X),
|
|
.A0(sky130_fd_sc_hd__mux2_1_6_X),
|
|
.S(sram[2]),
|
|
.X(sky130_fd_sc_hd__mux2_1_11_X));
|
|
|
|
sky130_fd_sc_hd__mux2_1 mux_l3_in_3_ (
|
|
.A1(sky130_fd_sc_hd__mux2_1_7_X),
|
|
.A0(sky130_fd_sc_hd__mux2_1_8_X),
|
|
.S(sram[2]),
|
|
.X(sky130_fd_sc_hd__mux2_1_12_X));
|
|
|
|
sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ (
|
|
.A1(sky130_fd_sc_hd__mux2_1_9_X),
|
|
.A0(sky130_fd_sc_hd__mux2_1_10_X),
|
|
.S(sram[3]),
|
|
.X(sky130_fd_sc_hd__mux2_1_13_X));
|
|
|
|
sky130_fd_sc_hd__mux2_1 mux_l4_in_1_ (
|
|
.A1(sky130_fd_sc_hd__mux2_1_11_X),
|
|
.A0(sky130_fd_sc_hd__mux2_1_12_X),
|
|
.S(sram[3]),
|
|
.X(sky130_fd_sc_hd__mux2_1_14_X));
|
|
|
|
sky130_fd_sc_hd__mux2_1 mux_l5_in_0_ (
|
|
.A1(sky130_fd_sc_hd__mux2_1_13_X),
|
|
.A0(sky130_fd_sc_hd__mux2_1_14_X),
|
|
.S(sram[4]),
|
|
.X(sky130_fd_sc_hd__mux2_1_15_X));
|
|
|
|
endmodule
|
|
// ----- END Verilog module for mux_tree_tapbuf_size16 -----
|
|
|
|
//----- Default net type -----
|
|
`default_nettype none
|
|
|
|
|
|
|
|
|
|
//----- Default net type -----
|
|
`default_nettype none
|
|
|
|
// ----- Verilog module for mux_tree_size2 -----
|
|
module mux_tree_size2(in,
|
|
sram,
|
|
sram_inv,
|
|
out);
|
|
//----- INPUT PORTS -----
|
|
input [0:1] in;
|
|
//----- INPUT PORTS -----
|
|
input [0:1] sram;
|
|
//----- INPUT PORTS -----
|
|
input [0:1] sram_inv;
|
|
//----- OUTPUT PORTS -----
|
|
output [0:0] out;
|
|
|
|
//----- BEGIN wire-connection ports -----
|
|
//----- END wire-connection ports -----
|
|
|
|
|
|
//----- BEGIN Registered ports -----
|
|
//----- END Registered ports -----
|
|
|
|
|
|
wire [0:0] const1_0_const1;
|
|
wire [0:0] sky130_fd_sc_hd__mux2_1_0_X;
|
|
|
|
// ----- BEGIN Local short connections -----
|
|
// ----- END Local short connections -----
|
|
// ----- BEGIN Local output short connections -----
|
|
// ----- END Local output short connections -----
|
|
|
|
const1 const1_0_ (
|
|
.const1(const1_0_const1));
|
|
|
|
sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ (
|
|
.A1(in[0]),
|
|
.A0(in[1]),
|
|
.S(sram[0]),
|
|
.X(sky130_fd_sc_hd__mux2_1_0_X));
|
|
|
|
sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ (
|
|
.A1(sky130_fd_sc_hd__mux2_1_0_X),
|
|
.A0(const1_0_const1),
|
|
.S(sram[1]),
|
|
.X(out));
|
|
|
|
endmodule
|
|
// ----- END Verilog module for mux_tree_size2 -----
|
|
|
|
//----- Default net type -----
|
|
`default_nettype none
|
|
|
|
|
|
|
|
|
|
//----- Default net type -----
|
|
`default_nettype none
|
|
|
|
// ----- Verilog module for frac_lut4_mux -----
|
|
module frac_lut4_mux(in,
|
|
sram,
|
|
sram_inv,
|
|
lut2_out,
|
|
lut3_out,
|
|
lut4_out);
|
|
//----- INPUT PORTS -----
|
|
input [0:15] in;
|
|
//----- INPUT PORTS -----
|
|
input [0:3] sram;
|
|
//----- INPUT PORTS -----
|
|
input [0:3] sram_inv;
|
|
//----- OUTPUT PORTS -----
|
|
output [0:1] lut2_out;
|
|
//----- OUTPUT PORTS -----
|
|
output [0:1] lut3_out;
|
|
//----- OUTPUT PORTS -----
|
|
output [0:0] lut4_out;
|
|
|
|
//----- BEGIN wire-connection ports -----
|
|
//----- END wire-connection ports -----
|
|
|
|
|
|
//----- BEGIN Registered ports -----
|
|
//----- END Registered ports -----
|
|
|
|
|
|
wire [0:0] sky130_fd_sc_hd__buf_2_5_X;
|
|
wire [0:0] sky130_fd_sc_hd__buf_2_6_X;
|
|
wire [0:0] sky130_fd_sc_hd__mux2_1_0_X;
|
|
wire [0:0] sky130_fd_sc_hd__mux2_1_10_X;
|
|
wire [0:0] sky130_fd_sc_hd__mux2_1_11_X;
|
|
wire [0:0] sky130_fd_sc_hd__mux2_1_12_X;
|
|
wire [0:0] sky130_fd_sc_hd__mux2_1_13_X;
|
|
wire [0:0] sky130_fd_sc_hd__mux2_1_14_X;
|
|
wire [0:0] sky130_fd_sc_hd__mux2_1_1_X;
|
|
wire [0:0] sky130_fd_sc_hd__mux2_1_2_X;
|
|
wire [0:0] sky130_fd_sc_hd__mux2_1_3_X;
|
|
wire [0:0] sky130_fd_sc_hd__mux2_1_4_X;
|
|
wire [0:0] sky130_fd_sc_hd__mux2_1_5_X;
|
|
wire [0:0] sky130_fd_sc_hd__mux2_1_6_X;
|
|
wire [0:0] sky130_fd_sc_hd__mux2_1_7_X;
|
|
wire [0:0] sky130_fd_sc_hd__mux2_1_8_X;
|
|
wire [0:0] sky130_fd_sc_hd__mux2_1_9_X;
|
|
|
|
// ----- BEGIN Local short connections -----
|
|
// ----- END Local short connections -----
|
|
// ----- BEGIN Local output short connections -----
|
|
// ----- END Local output short connections -----
|
|
|
|
sky130_fd_sc_hd__buf_2 sky130_fd_sc_hd__buf_2_0_ (
|
|
.A(sky130_fd_sc_hd__mux2_1_10_X),
|
|
.X(lut2_out[0]));
|
|
|
|
sky130_fd_sc_hd__buf_2 sky130_fd_sc_hd__buf_2_1_ (
|
|
.A(sky130_fd_sc_hd__mux2_1_11_X),
|
|
.X(lut2_out[1]));
|
|
|
|
sky130_fd_sc_hd__buf_2 sky130_fd_sc_hd__buf_2_2_ (
|
|
.A(sky130_fd_sc_hd__mux2_1_12_X),
|
|
.X(lut3_out[0]));
|
|
|
|
sky130_fd_sc_hd__buf_2 sky130_fd_sc_hd__buf_2_3_ (
|
|
.A(sky130_fd_sc_hd__mux2_1_13_X),
|
|
.X(lut3_out[1]));
|
|
|
|
sky130_fd_sc_hd__buf_2 sky130_fd_sc_hd__buf_2_4_ (
|
|
.A(sky130_fd_sc_hd__mux2_1_14_X),
|
|
.X(lut4_out));
|
|
|
|
sky130_fd_sc_hd__buf_2 sky130_fd_sc_hd__buf_2_5_ (
|
|
.A(sky130_fd_sc_hd__mux2_1_8_X),
|
|
.X(sky130_fd_sc_hd__buf_2_5_X));
|
|
|
|
sky130_fd_sc_hd__buf_2 sky130_fd_sc_hd__buf_2_6_ (
|
|
.A(sky130_fd_sc_hd__mux2_1_9_X),
|
|
.X(sky130_fd_sc_hd__buf_2_6_X));
|
|
|
|
sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ (
|
|
.A1(in[0]),
|
|
.A0(in[1]),
|
|
.S(sram[0]),
|
|
.X(sky130_fd_sc_hd__mux2_1_0_X));
|
|
|
|
sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ (
|
|
.A1(in[2]),
|
|
.A0(in[3]),
|
|
.S(sram[0]),
|
|
.X(sky130_fd_sc_hd__mux2_1_1_X));
|
|
|
|
sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ (
|
|
.A1(in[4]),
|
|
.A0(in[5]),
|
|
.S(sram[0]),
|
|
.X(sky130_fd_sc_hd__mux2_1_2_X));
|
|
|
|
sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ (
|
|
.A1(in[6]),
|
|
.A0(in[7]),
|
|
.S(sram[0]),
|
|
.X(sky130_fd_sc_hd__mux2_1_3_X));
|
|
|
|
sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ (
|
|
.A1(in[8]),
|
|
.A0(in[9]),
|
|
.S(sram[0]),
|
|
.X(sky130_fd_sc_hd__mux2_1_4_X));
|
|
|
|
sky130_fd_sc_hd__mux2_1 mux_l1_in_5_ (
|
|
.A1(in[10]),
|
|
.A0(in[11]),
|
|
.S(sram[0]),
|
|
.X(sky130_fd_sc_hd__mux2_1_5_X));
|
|
|
|
sky130_fd_sc_hd__mux2_1 mux_l1_in_6_ (
|
|
.A1(in[12]),
|
|
.A0(in[13]),
|
|
.S(sram[0]),
|
|
.X(sky130_fd_sc_hd__mux2_1_6_X));
|
|
|
|
sky130_fd_sc_hd__mux2_1 mux_l1_in_7_ (
|
|
.A1(in[14]),
|
|
.A0(in[15]),
|
|
.S(sram[0]),
|
|
.X(sky130_fd_sc_hd__mux2_1_7_X));
|
|
|
|
sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ (
|
|
.A1(sky130_fd_sc_hd__mux2_1_0_X),
|
|
.A0(sky130_fd_sc_hd__mux2_1_1_X),
|
|
.S(sram[1]),
|
|
.X(sky130_fd_sc_hd__mux2_1_8_X));
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sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ (
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.A1(sky130_fd_sc_hd__mux2_1_2_X),
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.A0(sky130_fd_sc_hd__mux2_1_3_X),
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.S(sram[1]),
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.X(sky130_fd_sc_hd__mux2_1_9_X));
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sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ (
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.A1(sky130_fd_sc_hd__mux2_1_4_X),
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.A0(sky130_fd_sc_hd__mux2_1_5_X),
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.S(sram[1]),
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.X(sky130_fd_sc_hd__mux2_1_10_X));
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sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ (
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.A1(sky130_fd_sc_hd__mux2_1_6_X),
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.A0(sky130_fd_sc_hd__mux2_1_7_X),
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.S(sram[1]),
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|
.X(sky130_fd_sc_hd__mux2_1_11_X));
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sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ (
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.A1(sky130_fd_sc_hd__buf_2_5_X),
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.A0(sky130_fd_sc_hd__buf_2_6_X),
|
|
.S(sram[2]),
|
|
.X(sky130_fd_sc_hd__mux2_1_12_X));
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sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ (
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.A1(sky130_fd_sc_hd__mux2_1_10_X),
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|
.A0(sky130_fd_sc_hd__mux2_1_11_X),
|
|
.S(sram[2]),
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|
.X(sky130_fd_sc_hd__mux2_1_13_X));
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|
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sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ (
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|
.A1(sky130_fd_sc_hd__mux2_1_12_X),
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.A0(sky130_fd_sc_hd__mux2_1_13_X),
|
|
.S(sram[3]),
|
|
.X(sky130_fd_sc_hd__mux2_1_14_X));
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|
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endmodule
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// ----- END Verilog module for frac_lut4_mux -----
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//----- Default net type -----
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`default_nettype none
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