SOFA/SOFA_A/SOFA_A_verilog/sub_module
Ganesh Gore f5ff147ddb Added sofa fpga lite design 2023-02-19 10:59:18 -07:00
..
arch_encoder.v Added sofa fpga lite design 2023-02-19 10:59:18 -07:00
inv_buf_passgate.v Added sofa fpga lite design 2023-02-19 10:59:18 -07:00
local_encoder.v Added sofa fpga lite design 2023-02-19 10:59:18 -07:00
luts.v Added sofa fpga lite design 2023-02-19 10:59:18 -07:00
memories.v Added sofa fpga lite design 2023-02-19 10:59:18 -07:00
mux_primitives.v Added sofa fpga lite design 2023-02-19 10:59:18 -07:00
muxes.v Added sofa fpga lite design 2023-02-19 10:59:18 -07:00
shift_register_banks.v Added sofa fpga lite design 2023-02-19 10:59:18 -07:00
user_defined_templates.v Added sofa fpga lite design 2023-02-19 10:59:18 -07:00
wires.v Added sofa fpga lite design 2023-02-19 10:59:18 -07:00