mirror of https://github.com/lnis-uofu/SOFA.git
41 lines
971 B
Verilog
41 lines
971 B
Verilog
//-------------------------------------------
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// FPGA Synthesizable Verilog Netlist
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// Description: Wires
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// Author: Xifan TANG
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// Organization: University of Utah
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// Date: Sun Feb 19 10:53:27 2023
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//-------------------------------------------
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//----- Time scale -----
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`timescale 1ns / 1ps
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// ----- BEGIN Verilog modules for regular wires -----
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//----- Default net type -----
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`default_nettype none
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// ----- Verilog module for direct_interc -----
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module direct_interc(in,
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out);
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//----- INPUT PORTS -----
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input [0:0] in;
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//----- OUTPUT PORTS -----
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output [0:0] out;
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//----- BEGIN wire-connection ports -----
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//----- END wire-connection ports -----
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//----- BEGIN Registered ports -----
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//----- END Registered ports -----
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wire [0:0] in;
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wire [0:0] out;
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assign out[0] = in[0];
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endmodule
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// ----- END Verilog module for direct_interc -----
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//----- Default net type -----
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`default_nettype none
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// ----- END Verilog modules for regular wires -----
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