mirror of https://github.com/lnis-uofu/SOFA.git
653 lines
15 KiB
Verilog
653 lines
15 KiB
Verilog
//-------------------------------------------
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// FPGA Synthesizable Verilog Netlist
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// Description: Memories used in FPGA
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// Author: Xifan TANG
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// Organization: University of Utah
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// Date: Sun Feb 19 10:53:27 2023
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//-------------------------------------------
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//----- Time scale -----
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`timescale 1ns / 1ps
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//----- Default net type -----
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`default_nettype none
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// ----- Verilog module for mux_tree_tapbuf_size10_mem -----
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module mux_tree_tapbuf_size10_mem(pReset,
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prog_clk,
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ccff_head,
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ccff_tail,
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mem_out);
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//----- GLOBAL PORTS -----
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input [0:0] pReset;
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//----- GLOBAL PORTS -----
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input [0:0] prog_clk;
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//----- INPUT PORTS -----
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input [0:0] ccff_head;
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//----- OUTPUT PORTS -----
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output [0:0] ccff_tail;
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//----- OUTPUT PORTS -----
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output [0:3] mem_out;
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//----- BEGIN wire-connection ports -----
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//----- END wire-connection ports -----
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//----- BEGIN Registered ports -----
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//----- END Registered ports -----
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// ----- BEGIN Local short connections -----
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// ----- END Local short connections -----
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// ----- BEGIN Local output short connections -----
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assign ccff_tail[0] = mem_out[3];
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// ----- END Local output short connections -----
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sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ (
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.RESET_B(pReset),
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.CLK(prog_clk),
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.D(ccff_head),
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.Q(mem_out[0]));
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sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ (
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.RESET_B(pReset),
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.CLK(prog_clk),
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.D(mem_out[0]),
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.Q(mem_out[1]));
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sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ (
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.RESET_B(pReset),
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.CLK(prog_clk),
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.D(mem_out[1]),
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.Q(mem_out[2]));
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sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ (
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.RESET_B(pReset),
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.CLK(prog_clk),
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.D(mem_out[2]),
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.Q(mem_out[3]));
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endmodule
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// ----- END Verilog module for mux_tree_tapbuf_size10_mem -----
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//----- Default net type -----
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`default_nettype none
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//----- Default net type -----
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`default_nettype none
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// ----- Verilog module for mux_tree_tapbuf_size6_mem -----
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module mux_tree_tapbuf_size6_mem(pReset,
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prog_clk,
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ccff_head,
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ccff_tail,
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mem_out);
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//----- GLOBAL PORTS -----
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input [0:0] pReset;
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//----- GLOBAL PORTS -----
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input [0:0] prog_clk;
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//----- INPUT PORTS -----
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input [0:0] ccff_head;
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//----- OUTPUT PORTS -----
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output [0:0] ccff_tail;
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//----- OUTPUT PORTS -----
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output [0:2] mem_out;
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//----- BEGIN wire-connection ports -----
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//----- END wire-connection ports -----
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//----- BEGIN Registered ports -----
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//----- END Registered ports -----
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// ----- BEGIN Local short connections -----
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// ----- END Local short connections -----
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// ----- BEGIN Local output short connections -----
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assign ccff_tail[0] = mem_out[2];
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// ----- END Local output short connections -----
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sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ (
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.RESET_B(pReset),
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.CLK(prog_clk),
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.D(ccff_head),
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.Q(mem_out[0]));
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sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ (
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.RESET_B(pReset),
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.CLK(prog_clk),
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.D(mem_out[0]),
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.Q(mem_out[1]));
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sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ (
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.RESET_B(pReset),
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.CLK(prog_clk),
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.D(mem_out[1]),
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.Q(mem_out[2]));
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endmodule
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// ----- END Verilog module for mux_tree_tapbuf_size6_mem -----
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//----- Default net type -----
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`default_nettype none
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//----- Default net type -----
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`default_nettype none
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// ----- Verilog module for mux_tree_tapbuf_size2_mem -----
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module mux_tree_tapbuf_size2_mem(pReset,
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prog_clk,
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ccff_head,
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ccff_tail,
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mem_out);
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//----- GLOBAL PORTS -----
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input [0:0] pReset;
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//----- GLOBAL PORTS -----
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input [0:0] prog_clk;
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//----- INPUT PORTS -----
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input [0:0] ccff_head;
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//----- OUTPUT PORTS -----
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output [0:0] ccff_tail;
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//----- OUTPUT PORTS -----
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output [0:1] mem_out;
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//----- BEGIN wire-connection ports -----
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//----- END wire-connection ports -----
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//----- BEGIN Registered ports -----
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//----- END Registered ports -----
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// ----- BEGIN Local short connections -----
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// ----- END Local short connections -----
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// ----- BEGIN Local output short connections -----
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assign ccff_tail[0] = mem_out[1];
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// ----- END Local output short connections -----
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sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ (
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.RESET_B(pReset),
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.CLK(prog_clk),
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.D(ccff_head),
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.Q(mem_out[0]));
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sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ (
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.RESET_B(pReset),
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.CLK(prog_clk),
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.D(mem_out[0]),
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.Q(mem_out[1]));
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endmodule
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// ----- END Verilog module for mux_tree_tapbuf_size2_mem -----
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//----- Default net type -----
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`default_nettype none
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//----- Default net type -----
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`default_nettype none
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// ----- Verilog module for mux_tree_tapbuf_size17_mem -----
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module mux_tree_tapbuf_size17_mem(pReset,
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prog_clk,
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ccff_head,
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ccff_tail,
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mem_out);
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//----- GLOBAL PORTS -----
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input [0:0] pReset;
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//----- GLOBAL PORTS -----
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input [0:0] prog_clk;
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//----- INPUT PORTS -----
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input [0:0] ccff_head;
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//----- OUTPUT PORTS -----
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output [0:0] ccff_tail;
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//----- OUTPUT PORTS -----
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output [0:4] mem_out;
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//----- BEGIN wire-connection ports -----
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//----- END wire-connection ports -----
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//----- BEGIN Registered ports -----
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//----- END Registered ports -----
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// ----- BEGIN Local short connections -----
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// ----- END Local short connections -----
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// ----- BEGIN Local output short connections -----
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assign ccff_tail[0] = mem_out[4];
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// ----- END Local output short connections -----
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sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ (
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.RESET_B(pReset),
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.CLK(prog_clk),
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.D(ccff_head),
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.Q(mem_out[0]));
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sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ (
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.RESET_B(pReset),
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.CLK(prog_clk),
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.D(mem_out[0]),
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.Q(mem_out[1]));
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sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ (
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.RESET_B(pReset),
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.CLK(prog_clk),
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.D(mem_out[1]),
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.Q(mem_out[2]));
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sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ (
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.RESET_B(pReset),
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.CLK(prog_clk),
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.D(mem_out[2]),
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.Q(mem_out[3]));
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sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_4_ (
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.RESET_B(pReset),
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.CLK(prog_clk),
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.D(mem_out[3]),
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.Q(mem_out[4]));
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endmodule
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// ----- END Verilog module for mux_tree_tapbuf_size17_mem -----
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//----- Default net type -----
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`default_nettype none
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//----- Default net type -----
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`default_nettype none
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// ----- Verilog module for mux_tree_tapbuf_size3_mem -----
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module mux_tree_tapbuf_size3_mem(pReset,
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prog_clk,
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ccff_head,
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ccff_tail,
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mem_out);
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//----- GLOBAL PORTS -----
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input [0:0] pReset;
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//----- GLOBAL PORTS -----
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input [0:0] prog_clk;
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//----- INPUT PORTS -----
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input [0:0] ccff_head;
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//----- OUTPUT PORTS -----
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output [0:0] ccff_tail;
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//----- OUTPUT PORTS -----
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output [0:1] mem_out;
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//----- BEGIN wire-connection ports -----
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//----- END wire-connection ports -----
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//----- BEGIN Registered ports -----
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//----- END Registered ports -----
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// ----- BEGIN Local short connections -----
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// ----- END Local short connections -----
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// ----- BEGIN Local output short connections -----
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assign ccff_tail[0] = mem_out[1];
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// ----- END Local output short connections -----
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sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ (
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.RESET_B(pReset),
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.CLK(prog_clk),
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.D(ccff_head),
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.Q(mem_out[0]));
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sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ (
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.RESET_B(pReset),
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.CLK(prog_clk),
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.D(mem_out[0]),
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.Q(mem_out[1]));
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endmodule
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// ----- END Verilog module for mux_tree_tapbuf_size3_mem -----
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//----- Default net type -----
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`default_nettype none
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//----- Default net type -----
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`default_nettype none
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// ----- Verilog module for mux_tree_tapbuf_size16_mem -----
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module mux_tree_tapbuf_size16_mem(pReset,
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prog_clk,
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ccff_head,
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ccff_tail,
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mem_out);
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//----- GLOBAL PORTS -----
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input [0:0] pReset;
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//----- GLOBAL PORTS -----
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input [0:0] prog_clk;
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//----- INPUT PORTS -----
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input [0:0] ccff_head;
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//----- OUTPUT PORTS -----
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output [0:0] ccff_tail;
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//----- OUTPUT PORTS -----
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output [0:4] mem_out;
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//----- BEGIN wire-connection ports -----
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//----- END wire-connection ports -----
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//----- BEGIN Registered ports -----
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//----- END Registered ports -----
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// ----- BEGIN Local short connections -----
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// ----- END Local short connections -----
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// ----- BEGIN Local output short connections -----
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assign ccff_tail[0] = mem_out[4];
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// ----- END Local output short connections -----
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sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ (
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.RESET_B(pReset),
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.CLK(prog_clk),
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.D(ccff_head),
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.Q(mem_out[0]));
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sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ (
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.RESET_B(pReset),
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.CLK(prog_clk),
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.D(mem_out[0]),
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.Q(mem_out[1]));
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sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ (
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.RESET_B(pReset),
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.CLK(prog_clk),
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.D(mem_out[1]),
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.Q(mem_out[2]));
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sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ (
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.RESET_B(pReset),
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.CLK(prog_clk),
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.D(mem_out[2]),
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.Q(mem_out[3]));
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sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_4_ (
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.RESET_B(pReset),
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.CLK(prog_clk),
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.D(mem_out[3]),
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.Q(mem_out[4]));
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endmodule
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// ----- END Verilog module for mux_tree_tapbuf_size16_mem -----
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//----- Default net type -----
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`default_nettype none
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//----- Default net type -----
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`default_nettype none
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// ----- Verilog module for mux_tree_size2_mem -----
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module mux_tree_size2_mem(pReset,
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prog_clk,
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ccff_head,
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ccff_tail,
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mem_out);
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//----- GLOBAL PORTS -----
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input [0:0] pReset;
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//----- GLOBAL PORTS -----
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input [0:0] prog_clk;
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//----- INPUT PORTS -----
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input [0:0] ccff_head;
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//----- OUTPUT PORTS -----
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output [0:0] ccff_tail;
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//----- OUTPUT PORTS -----
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output [0:1] mem_out;
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//----- BEGIN wire-connection ports -----
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//----- END wire-connection ports -----
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//----- BEGIN Registered ports -----
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//----- END Registered ports -----
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// ----- BEGIN Local short connections -----
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// ----- END Local short connections -----
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// ----- BEGIN Local output short connections -----
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assign ccff_tail[0] = mem_out[1];
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// ----- END Local output short connections -----
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sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ (
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.RESET_B(pReset),
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.CLK(prog_clk),
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.D(ccff_head),
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.Q(mem_out[0]));
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sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ (
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.RESET_B(pReset),
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.CLK(prog_clk),
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.D(mem_out[0]),
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.Q(mem_out[1]));
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endmodule
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// ----- END Verilog module for mux_tree_size2_mem -----
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//----- Default net type -----
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`default_nettype none
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//----- Default net type -----
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`default_nettype none
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// ----- Verilog module for frac_lut4_sky130_fd_sc_hd__dfrtp_1_mem -----
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module frac_lut4_sky130_fd_sc_hd__dfrtp_1_mem(pReset,
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prog_clk,
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ccff_head,
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ccff_tail,
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mem_out);
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//----- GLOBAL PORTS -----
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input [0:0] pReset;
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//----- GLOBAL PORTS -----
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input [0:0] prog_clk;
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//----- INPUT PORTS -----
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input [0:0] ccff_head;
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//----- OUTPUT PORTS -----
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output [0:0] ccff_tail;
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//----- OUTPUT PORTS -----
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output [0:16] mem_out;
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//----- BEGIN wire-connection ports -----
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//----- END wire-connection ports -----
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//----- BEGIN Registered ports -----
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//----- END Registered ports -----
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// ----- BEGIN Local short connections -----
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// ----- END Local short connections -----
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// ----- BEGIN Local output short connections -----
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assign ccff_tail[0] = mem_out[16];
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// ----- END Local output short connections -----
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sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ (
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.RESET_B(pReset),
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.CLK(prog_clk),
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.D(ccff_head),
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.Q(mem_out[0]));
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sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ (
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.RESET_B(pReset),
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.CLK(prog_clk),
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.D(mem_out[0]),
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.Q(mem_out[1]));
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sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ (
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.RESET_B(pReset),
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.CLK(prog_clk),
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.D(mem_out[1]),
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.Q(mem_out[2]));
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sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ (
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.RESET_B(pReset),
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.CLK(prog_clk),
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.D(mem_out[2]),
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.Q(mem_out[3]));
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sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_4_ (
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.RESET_B(pReset),
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.CLK(prog_clk),
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.D(mem_out[3]),
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.Q(mem_out[4]));
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sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_5_ (
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.RESET_B(pReset),
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.CLK(prog_clk),
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.D(mem_out[4]),
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.Q(mem_out[5]));
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sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_6_ (
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.RESET_B(pReset),
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.CLK(prog_clk),
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.D(mem_out[5]),
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.Q(mem_out[6]));
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|
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sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_7_ (
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.RESET_B(pReset),
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.CLK(prog_clk),
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|
.D(mem_out[6]),
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.Q(mem_out[7]));
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|
|
|
sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_8_ (
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.RESET_B(pReset),
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|
.CLK(prog_clk),
|
|
.D(mem_out[7]),
|
|
.Q(mem_out[8]));
|
|
|
|
sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_9_ (
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.RESET_B(pReset),
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|
.CLK(prog_clk),
|
|
.D(mem_out[8]),
|
|
.Q(mem_out[9]));
|
|
|
|
sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_10_ (
|
|
.RESET_B(pReset),
|
|
.CLK(prog_clk),
|
|
.D(mem_out[9]),
|
|
.Q(mem_out[10]));
|
|
|
|
sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_11_ (
|
|
.RESET_B(pReset),
|
|
.CLK(prog_clk),
|
|
.D(mem_out[10]),
|
|
.Q(mem_out[11]));
|
|
|
|
sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_12_ (
|
|
.RESET_B(pReset),
|
|
.CLK(prog_clk),
|
|
.D(mem_out[11]),
|
|
.Q(mem_out[12]));
|
|
|
|
sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_13_ (
|
|
.RESET_B(pReset),
|
|
.CLK(prog_clk),
|
|
.D(mem_out[12]),
|
|
.Q(mem_out[13]));
|
|
|
|
sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_14_ (
|
|
.RESET_B(pReset),
|
|
.CLK(prog_clk),
|
|
.D(mem_out[13]),
|
|
.Q(mem_out[14]));
|
|
|
|
sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_15_ (
|
|
.RESET_B(pReset),
|
|
.CLK(prog_clk),
|
|
.D(mem_out[14]),
|
|
.Q(mem_out[15]));
|
|
|
|
sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_16_ (
|
|
.RESET_B(pReset),
|
|
.CLK(prog_clk),
|
|
.D(mem_out[15]),
|
|
.Q(mem_out[16]));
|
|
|
|
endmodule
|
|
// ----- END Verilog module for frac_lut4_sky130_fd_sc_hd__dfrtp_1_mem -----
|
|
|
|
//----- Default net type -----
|
|
`default_nettype none
|
|
|
|
|
|
|
|
|
|
//----- Default net type -----
|
|
`default_nettype none
|
|
|
|
// ----- Verilog module for EMBEDDED_IO_HD_sky130_fd_sc_hd__dfrtp_1_mem -----
|
|
module EMBEDDED_IO_HD_sky130_fd_sc_hd__dfrtp_1_mem(pReset,
|
|
prog_clk,
|
|
ccff_head,
|
|
ccff_tail,
|
|
mem_out);
|
|
//----- GLOBAL PORTS -----
|
|
input [0:0] pReset;
|
|
//----- GLOBAL PORTS -----
|
|
input [0:0] prog_clk;
|
|
//----- INPUT PORTS -----
|
|
input [0:0] ccff_head;
|
|
//----- OUTPUT PORTS -----
|
|
output [0:0] ccff_tail;
|
|
//----- OUTPUT PORTS -----
|
|
output [0:0] mem_out;
|
|
|
|
//----- BEGIN wire-connection ports -----
|
|
//----- END wire-connection ports -----
|
|
|
|
|
|
//----- BEGIN Registered ports -----
|
|
//----- END Registered ports -----
|
|
|
|
|
|
|
|
// ----- BEGIN Local short connections -----
|
|
// ----- END Local short connections -----
|
|
// ----- BEGIN Local output short connections -----
|
|
assign ccff_tail[0] = mem_out[0];
|
|
// ----- END Local output short connections -----
|
|
|
|
sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ (
|
|
.RESET_B(pReset),
|
|
.CLK(prog_clk),
|
|
.D(ccff_head),
|
|
.Q(mem_out));
|
|
|
|
endmodule
|
|
// ----- END Verilog module for EMBEDDED_IO_HD_sky130_fd_sc_hd__dfrtp_1_mem -----
|
|
|
|
//----- Default net type -----
|
|
`default_nettype none
|
|
|
|
|
|
|
|
|