AurelienUoU fb0992bd85 Update go.sh and Makefile		2018-12-11 15:31:32 -07:00
..
ARCH	Add scan-chain and timed architecture + update simulation script script (add script for autochecked testbench)	2018-12-08 22:57:54 -07:00
Circuits	Add pip_add benchmark	2018-12-11 15:29:48 -07:00
SRC	Add an autochecked configuration free testbench	2018-12-11 14:44:13 -07:00
SpiceNetlists	rename customized vpr7 to vpr7 XML to Production	2018-09-17 23:10:45 -06:00
VerilogNetlists	Add timing and initialization for simulation	2018-12-04 17:32:09 -07:00
picorv	Changed for the naming	2018-12-08 16:19:38 -07:00
Makefile	rename customized vpr7 to vpr7 XML to Production	2018-09-17 23:10:45 -06:00
go.sh	Update go.sh and Makefile	2018-12-11 15:31:32 -07:00
picorv.sh	Changed for the naming	2018-12-08 16:19:38 -07:00