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OpenFPGA/openfpga/src/fpga_verilog
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Emin Cetin 6c2c4e8b14 adding comment 2022-01-28 08:57:45 +03:00
..
fabric_verilog_options.cpp [Engine] Now FPGA-Verilog commands have a new option ``--no_time_stamp`` 2022-01-25 12:09:08 -08:00
fabric_verilog_options.h [Engine] Now FPGA-Verilog commands have a new option ``--no_time_stamp`` 2022-01-25 12:09:08 -08:00
verilog_api.cpp [Engine] Now FPGA-Verilog commands have a new option ``--no_time_stamp`` 2022-01-25 12:09:08 -08:00
verilog_api.h [FPGA-Bitstream] Upgrade bitstream generator to support multiple shift register banks in a configuration region for QuickLogic memory bank 2021-10-09 20:39:45 -07:00
verilog_auxiliary_netlists.cpp [Engine] Now FPGA-Verilog commands have a new option ``--no_time_stamp`` 2022-01-25 12:09:08 -08:00
verilog_auxiliary_netlists.h [Engine] Now FPGA-Verilog commands have a new option ``--no_time_stamp`` 2022-01-25 12:09:08 -08:00
verilog_constants.h [FPGA-Verilog] Now FPGA-Verilog can output shift register bank netlists 2021-09-29 20:56:02 -07:00
verilog_decoders.cpp [Engine] Now FPGA-Verilog commands have a new option ``--no_time_stamp`` 2022-01-25 12:09:08 -08:00
verilog_decoders.h [Engine] Now FPGA-Verilog commands have a new option ``--no_time_stamp`` 2022-01-25 12:09:08 -08:00
verilog_essential_gates.cpp [Engine] Now FPGA-Verilog commands have a new option ``--no_time_stamp`` 2022-01-25 12:09:08 -08:00
verilog_essential_gates.h [Engine] Now FPGA-Verilog commands have a new option ``--no_time_stamp`` 2022-01-25 12:09:08 -08:00
verilog_formal_random_top_testbench.cpp [Engine] Now FPGA-Verilog commands have a new option ``--no_time_stamp`` 2022-01-25 12:09:08 -08:00
verilog_formal_random_top_testbench.h [Tool] Added default net type options to verilog testbench generator command 2021-06-14 11:37:49 -06:00
verilog_grid.cpp [Engine] Now FPGA-Verilog commands have a new option ``--no_time_stamp`` 2022-01-25 12:09:08 -08:00
verilog_grid.h [Tool] Support default_net_type Verilog syntex in fabric generator 2021-02-28 11:57:40 -07:00
verilog_lut.cpp [Engine] Now FPGA-Verilog commands have a new option ``--no_time_stamp`` 2022-01-25 12:09:08 -08:00
verilog_lut.h [Tool] Support default_net_type Verilog syntex in fabric generator 2021-02-28 11:57:40 -07:00
verilog_memory.cpp [Engine] Now FPGA-Verilog commands have a new option ``--no_time_stamp`` 2022-01-25 12:09:08 -08:00
verilog_memory.h [Tool] Support default_net_type Verilog syntex in fabric generator 2021-02-28 11:57:40 -07:00
verilog_module_writer.cpp [Tool] Bug fix for printing single-bit ports in Verilog netlists 2021-02-28 16:12:57 -07:00
verilog_module_writer.h [Tool] Support default_net_type Verilog syntex in fabric generator 2021-02-28 11:57:40 -07:00
verilog_mux.cpp [Engine] Now FPGA-Verilog commands have a new option ``--no_time_stamp`` 2022-01-25 12:09:08 -08:00
verilog_mux.h [Tool] Support default_net_type Verilog syntex in fabric generator 2021-02-28 11:57:40 -07:00
verilog_port_types.h [Tool] Support default_net_type Verilog syntex in fabric generator 2021-02-28 11:57:40 -07:00
verilog_preconfig_top_module.cpp [Engine] Now FPGA-Verilog commands have a new option ``--no_time_stamp`` 2022-01-25 12:09:08 -08:00
verilog_preconfig_top_module.h [Tool] Added default net type options to verilog testbench generator command 2021-06-14 11:37:49 -06:00
verilog_routing.cpp [Engine] Now FPGA-Verilog commands have a new option ``--no_time_stamp`` 2022-01-25 12:09:08 -08:00
verilog_routing.h [Tool] Support default_net_type Verilog syntex in fabric generator 2021-02-28 11:57:40 -07:00
verilog_shift_register_banks.cpp [Engine] Now FPGA-Verilog commands have a new option ``--no_time_stamp`` 2022-01-25 12:09:08 -08:00
verilog_shift_register_banks.h [Engine] Now the MemoryBankShiftRegisterBanks data structure combines both BL/WL data structures as the unified interface 2021-10-08 15:25:37 -07:00
verilog_simulation_info_writer.cpp [Tool] Add a new option ``--no_self_checking`` so that users can output a simple testbench without self checking codes 2021-06-29 15:26:40 -06:00
verilog_simulation_info_writer.h [Tool] Add new option 'testbench_type' so that simulation task can write different information for different testbenches 2021-06-25 10:10:16 -06:00
verilog_submodule.cpp [Engine] Now FPGA-Verilog commands have a new option ``--no_time_stamp`` 2022-01-25 12:09:08 -08:00
verilog_submodule.h [Engine] Now the MemoryBankShiftRegisterBanks data structure combines both BL/WL data structures as the unified interface 2021-10-08 15:25:37 -07:00
verilog_submodule_utils.cpp [Engine] Now FPGA-Verilog commands have a new option ``--no_time_stamp`` 2022-01-25 12:09:08 -08:00
verilog_submodule_utils.h [Engine] Now FPGA-Verilog commands have a new option ``--no_time_stamp`` 2022-01-25 12:09:08 -08:00
verilog_testbench_options.cpp [Engine] Now FPGA-Verilog commands have a new option ``--no_time_stamp`` 2022-01-25 12:09:08 -08:00
verilog_testbench_options.h [Engine] Now FPGA-Verilog commands have a new option ``--no_time_stamp`` 2022-01-25 12:09:08 -08:00
verilog_testbench_utils.cpp [Engine] Support programming shift register clock in XML syntax 2021-10-01 11:00:38 -07:00
verilog_testbench_utils.h [Tool] Patch the critical bug in the use of signal polarity in pin constraints 2021-07-02 15:26:21 -06:00
verilog_top_module.cpp [Engine] Now FPGA-Verilog commands have a new option ``--no_time_stamp`` 2022-01-25 12:09:08 -08:00
verilog_top_module.h [Tool] Support default_net_type Verilog syntex in fabric generator 2021-02-28 11:57:40 -07:00
verilog_top_testbench.cpp adding comment 2022-01-28 08:57:45 +03:00
verilog_top_testbench.h [FPGA-Bitstream] Upgrade bitstream generator to support multiple shift register banks in a configuration region for QuickLogic memory bank 2021-10-09 20:39:45 -07:00
verilog_top_testbench_constants.h [FPGA-Verilog] Upgrade testbench generator to support QL memory bank 2021-09-05 21:38:00 -07:00
verilog_top_testbench_memory_bank.cpp [FPGA-Verilog] Revert back to the previous precomputing strategy for shift register clocks 2021-10-10 23:19:39 -07:00
verilog_top_testbench_memory_bank.h [FPGA-Bitstream] Upgrade bitstream generator to support multiple shift register banks in a configuration region for QuickLogic memory bank 2021-10-09 20:39:45 -07:00
verilog_wire.cpp [Engine] Now FPGA-Verilog commands have a new option ``--no_time_stamp`` 2022-01-25 12:09:08 -08:00
verilog_wire.h [Engine] Now FPGA-Verilog commands have a new option ``--no_time_stamp`` 2022-01-25 12:09:08 -08:00
verilog_writer_utils.cpp [Engine] Now FPGA-Verilog commands have a new option ``--no_time_stamp`` 2022-01-25 12:09:08 -08:00
verilog_writer_utils.h [Engine] Now FPGA-Verilog commands have a new option ``--no_time_stamp`` 2022-01-25 12:09:08 -08:00