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bitstream_context.h
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Start developing BitstreamContext
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2019-09-13 21:27:47 -06:00 |
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bitstream_context_fwd.h
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Start developing BitstreamContext
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2019-09-13 21:27:47 -06:00 |
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device_coordinator.cpp
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Add copy constructor for RRChan, RRSwitchBlock etc.
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2019-05-27 15:44:34 -06:00 |
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device_coordinator.h
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Add copy constructor for RRChan, RRSwitchBlock etc.
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2019-05-27 15:44:34 -06:00 |
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fpga_x2p_api.c
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move mux_lib to fpga_x2p_setup
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2019-10-19 19:13:52 -06:00 |
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fpga_x2p_api.h
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rename rr_switch_block to rr_gsb, a generic block
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2019-06-06 17:41:01 -06:00 |
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fpga_x2p_backannotate_utils.c
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fixed critical bugs in pass_tracks identification and update regression test for tileable arch
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2019-06-25 21:59:38 -06:00 |
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fpga_x2p_backannotate_utils.h
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rename rr_switch_block to rr_gsb, a generic block
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2019-06-06 17:41:01 -06:00 |
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fpga_x2p_bitstream_utils.c
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Rename SCFF to CCFF, configuration chain flip flop
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2019-09-26 11:32:57 -06:00 |
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fpga_x2p_bitstream_utils.h
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Finish renaming SCFF to CCFF
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2019-09-26 14:04:40 -06:00 |
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fpga_x2p_globals.c
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rename rr_switch_block to rr_gsb, a generic block
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2019-06-06 17:41:01 -06:00 |
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fpga_x2p_globals.h
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rename rr_switch_block to rr_gsb, a generic block
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2019-06-06 17:41:01 -06:00 |
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fpga_x2p_lut_utils.c
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cleaned unused variables
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2019-05-13 14:45:02 -06:00 |
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fpga_x2p_lut_utils.h
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Update VPR7 X2P with new engine
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2019-04-26 12:23:47 -06:00 |
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fpga_x2p_mem_utils.cpp
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Refactoring Verilog generation intermediate level of pb_types and SRAM port generation
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2019-10-11 21:43:47 -06:00 |
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fpga_x2p_mem_utils.h
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Refactoring Verilog generation intermediate level of pb_types and SRAM port generation
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2019-10-11 21:43:47 -06:00 |
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fpga_x2p_mux_utils.c
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refactoring mux Verilog generation for switch blocks
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2019-09-26 20:59:19 -06:00 |
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fpga_x2p_mux_utils.h
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updated bitstream generator for local encoders
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2019-08-06 14:17:56 -06:00 |
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fpga_x2p_naming.cpp
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add const 0 and 1 module Verilog generation
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2019-10-21 14:17:09 -06:00 |
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fpga_x2p_naming.h
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plug in MUX module graph generation, still local encoders contain dangling net, bug fixing
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2019-10-21 00:00:30 -06:00 |
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fpga_x2p_pbtypes_utils.c
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refactoring top-level module with clb2clb direct connection
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2019-10-17 17:29:04 -06:00 |
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fpga_x2p_pbtypes_utils.h
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refactoring top-level module with clb2clb direct connection
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2019-10-17 17:29:04 -06:00 |
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fpga_x2p_rr_graph_utils.c
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many bug fixing and now start improving the routability of tileable rr_graph
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2019-06-24 17:33:29 -06:00 |
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fpga_x2p_rr_graph_utils.h
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many bug fixing and now start improving the routability of tileable rr_graph
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2019-06-24 17:33:29 -06:00 |
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fpga_x2p_setup.c
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Rename SCFF to CCFF, configuration chain flip flop
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2019-09-26 11:32:57 -06:00 |
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fpga_x2p_setup.h
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Update VPR7 X2P with new engine
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2019-04-26 12:23:47 -06:00 |
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fpga_x2p_timing_utils.c
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developed new rotating methods for RRSwitchBlocks, debugging ongoing
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2019-05-26 23:35:30 -06:00 |
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fpga_x2p_timing_utils.h
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Update VPR7 X2P with new engine
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2019-04-26 12:23:47 -06:00 |
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fpga_x2p_types.h
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keep developing tileable rr_graph, track2ipin and opin2track to go
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2019-06-19 21:30:16 -06:00 |
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fpga_x2p_unique_routing.c
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speeding up identifying unique modules in routing
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2019-07-14 13:49:20 -06:00 |
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fpga_x2p_unique_routing.h
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rename rr_switch_block to rr_gsb, a generic block
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2019-06-06 17:41:01 -06:00 |
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fpga_x2p_utils.c
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start adding memory circuit to Switch blocks
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2019-09-27 18:08:37 -06:00 |
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fpga_x2p_utils.h
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Rename SCFF to CCFF, configuration chain flip flop
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2019-09-26 11:32:57 -06:00 |
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link_arch_circuit_lib.cpp
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refactored port addition for pb_types in Verilog generation
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2019-10-08 14:03:17 -06:00 |
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link_arch_circuit_lib.h
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rework on the circuit model ports and start prototyping mux Verilog generation
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2019-08-20 15:24:53 -06:00 |
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module_manager.cpp
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plug in MUX module graph generation, still local encoders contain dangling net, bug fixing
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2019-10-21 00:00:30 -06:00 |
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module_manager.h
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plug in MUX module graph generation, still local encoders contain dangling net, bug fixing
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2019-10-21 00:00:30 -06:00 |
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module_manager_fwd.h
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plug in MUX module graph generation, still local encoders contain dangling net, bug fixing
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2019-10-21 00:00:30 -06:00 |
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module_manager_utils.cpp
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refactor memory organization at the top-level module
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2019-10-18 15:33:25 -06:00 |
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module_manager_utils.h
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refactor memory organization at the top-level module
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2019-10-18 15:33:25 -06:00 |
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netlist_manager.cpp
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add netlist manager class
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2019-10-18 17:59:03 -06:00 |
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netlist_manager.h
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add netlist manager class
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2019-10-18 17:59:03 -06:00 |
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netlist_manager_fwd.h
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add netlist manager class
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2019-10-18 17:59:03 -06:00 |
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quicksort.c
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upgrade Verilog SB generator using the RRSwitchBlock
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2019-05-23 17:37:39 -06:00 |
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quicksort.h
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upgrade Verilog SB generator using the RRSwitchBlock
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2019-05-23 17:37:39 -06:00 |
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rr_blocks.cpp
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refactor memory organization at the top-level module
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2019-10-18 15:33:25 -06:00 |
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rr_blocks.h
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refactor memory organization at the top-level module
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2019-10-18 15:33:25 -06:00 |
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rr_blocks_naming.cpp
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c++ string is not working, use char which is stable
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2019-06-13 18:38:46 -06:00 |
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rr_blocks_naming.h
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add new class port to simplify codes in outputting codes, upgrade RRSwitch to RRGSB
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2019-06-06 23:45:21 -06:00 |
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rr_blocks_utils.cpp
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refactored shared config bits calculation
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2019-10-06 16:57:53 -06:00 |
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rr_blocks_utils.h
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refactored shared config bits calculation
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2019-10-06 16:57:53 -06:00 |
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write_rr_blocks.cpp
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fixed the bug in determine passing wires for rr_gsb
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2019-06-26 10:50:23 -06:00 |
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write_rr_blocks.h
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update rr_block writer to include IPINs in XML files
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2019-06-25 11:17:22 -06:00 |
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