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dont_care_bits
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Changed HDL files reading to be as a single compilation unit in yosys_vpr flow for Verific mode. Changed '' variable to 'read_verilog ' in yosys template scripts. Updated task configs accordingly.
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2022-01-17 13:21:29 +05:00 |
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extract_dsp_mode_bit/config
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Support extracting data that is not affecting fabric bitstream (#1566)
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2024-03-09 17:38:31 -08:00 |
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filter_value0/config
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[test] add new tests to cover the new features
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2023-10-06 18:41:57 -07:00 |
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filter_value1/config
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[test] add new tests to cover the new features
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2023-10-06 18:41:57 -07:00 |
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force_clock_tap_routing/config
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[test] fixed a bug
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2024-11-26 18:09:39 -08:00 |
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generate_bitstream
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Update test flow
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2024-07-27 23:52:54 -07:00 |
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load_external_architecture_bitstream/config
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[test] update arch bitstream and force a pin placement for the test case where external bistream is fixed
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2022-09-20 14:14:18 -07:00 |
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overload_default_mode_bit/config
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[test] add new test to validate default mode bit overwrite
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2024-11-25 16:06:40 -08:00 |
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overload_dsp_mode_bit/config
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[test] debugging
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2023-01-24 17:57:34 -08:00 |
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overload_mux_default_path/config
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Changed HDL files reading to be as a single compilation unit in yosys_vpr flow for Verific mode. Changed '' variable to 'read_verilog ' in yosys template scripts. Updated task configs accordingly.
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2022-01-17 13:21:29 +05:00 |
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overwrite_bitstream/device_4x4/config
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Pass in the OpenFPGA root dir
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2024-07-29 11:04:03 -07:00 |
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path_only/config
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[test] add new tests to cover the new features
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2023-10-06 18:41:57 -07:00 |
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repack_ignore_nets/config
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[test] add and deploy new benchmark
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2024-06-02 14:27:02 -07:00 |
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repack_wire_lut/config
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[Test] bug fix
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2021-10-30 16:50:57 -07:00 |
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repack_wire_lut_strong/config
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[script] add missing files
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2022-09-29 16:14:38 -07:00 |
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report_bitstream_distribution
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Changed HDL files reading to be as a single compilation unit in yosys_vpr flow for Verific mode. Changed '' variable to 'read_verilog ' in yosys template scripts. Updated task configs accordingly.
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2022-01-17 13:21:29 +05:00 |
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trim_path/config
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[core] ad a new test case
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2023-10-06 18:31:54 -07:00 |
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value_only/config
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[test] add new tests to cover the new features
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2023-10-06 18:41:57 -07:00 |
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write_io_mapping/config
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Changed HDL files reading to be as a single compilation unit in yosys_vpr flow for Verific mode. Changed '' variable to 'read_verilog ' in yosys template scripts. Updated task configs accordingly.
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2022-01-17 13:21:29 +05:00 |
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