tangxifan 3b2a4c5387 [Tool] Add signal initialization to Verilog testbench generator and remove it from fabric netlists		2020-11-22 20:25:03 -07:00
..
fabric_verilog_options.cpp	[Tool] Move icarus and signal initialization options to testbench generator	2020-11-22 16:01:31 -07:00
fabric_verilog_options.h	[Tool] Move icarus and signal initialization options to testbench generator	2020-11-22 16:01:31 -07:00
verilog_api.cpp	[Tool] Add signal initialization to Verilog testbench generator and remove it from fabric netlists	2020-11-22 20:25:03 -07:00
verilog_api.h	[Tool] Use use standard data structure to store global port information	2020-11-10 19:07:28 -07:00
verilog_auxiliary_netlists.cpp	[Tool] Move icarus and signal initialization options to testbench generator	2020-11-22 16:01:31 -07:00
verilog_auxiliary_netlists.h	[Tool] Now users can specify a different fabric netlist when generating Verilog testbench	2020-10-12 12:31:51 -06:00
verilog_constants.h	[FPGA-Verilog] Rename files and functions to distinguish from FPGA-SPICE files and functions	2020-09-20 12:58:55 -06:00
verilog_decoders.cpp	[Tool] Bug fixed for multi-region configuration frame	2020-10-30 21:19:20 -06:00
verilog_decoders.h	add architecture decoder (for frame-based config memory) to Verilog writer	2020-06-11 19:31:09 -06:00
verilog_essential_gates.cpp	[Tool] Add signal initialization to Verilog testbench generator and remove it from fabric netlists	2020-11-22 20:25:03 -07:00
verilog_essential_gates.h	removed redundant include files in all the verilog netlists except the top one	2020-06-11 19:28:13 -06:00
verilog_formal_random_top_testbench.cpp	add explicit port mapping support to Verilog testbench generator	2020-06-11 19:31:07 -06:00
verilog_formal_random_top_testbench.h	add explicit port mapping support to Verilog testbench generator	2020-06-11 19:31:07 -06:00
verilog_grid.cpp	split logical tile netlists to keep good Verilog hierarchy	2020-07-24 12:53:21 -06:00
verilog_grid.h	removed redundant include files in all the verilog netlists except the top one	2020-06-11 19:28:13 -06:00
verilog_lut.cpp	removed redundant include files in all the verilog netlists except the top one	2020-06-11 19:28:13 -06:00
verilog_lut.h	removed redundant include files in all the verilog netlists except the top one	2020-06-11 19:28:13 -06:00
verilog_memory.cpp	removed redundant include files in all the verilog netlists except the top one	2020-06-11 19:28:13 -06:00
verilog_memory.h	removed redundant include files in all the verilog netlists except the top one	2020-06-11 19:28:13 -06:00
verilog_module_writer.cpp	[Tool] Bug fix in multi-region memory bank; Basic test passed	2020-10-29 16:26:45 -06:00
verilog_module_writer.h	print verilog module writer online	2020-02-16 12:04:03 -07:00
verilog_mux.cpp	removed redundant include files in all the verilog netlists except the top one	2020-06-11 19:28:13 -06:00
verilog_mux.h	removed redundant include files in all the verilog netlists except the top one	2020-06-11 19:28:13 -06:00
verilog_port_types.h	start transplanting fpga_verilog	2020-02-15 15:03:00 -07:00
verilog_preconfig_top_module.cpp	[Tool] Add signal initialization to Verilog testbench generator and remove it from fabric netlists	2020-11-22 20:25:03 -07:00
verilog_preconfig_top_module.h	[Tool] Use use standard data structure to store global port information	2020-11-10 19:07:28 -07:00
verilog_routing.cpp	removed redundant include files in all the verilog netlists except the top one	2020-06-11 19:28:13 -06:00
verilog_routing.h	removed redundant include files in all the verilog netlists except the top one	2020-06-11 19:28:13 -06:00
verilog_simulation_info_writer.cpp	[Tool] Split io location mapping builder from fabric builder	2020-11-02 18:27:34 -07:00
verilog_simulation_info_writer.h	[FPGA-Verilog] Rename files and functions to distinguish from FPGA-SPICE files and functions	2020-09-20 12:58:55 -06:00
verilog_submodule.cpp	add architecture decoder (for frame-based config memory) to Verilog writer	2020-06-11 19:31:09 -06:00
verilog_submodule.h	add architecture decoder (for frame-based config memory) to Verilog writer	2020-06-11 19:31:09 -06:00
verilog_submodule_utils.cpp	[Tool] Add signal initialization to Verilog testbench generator and remove it from fabric netlists	2020-11-22 20:25:03 -07:00
verilog_submodule_utils.h	[Tool] Add signal initialization to Verilog testbench generator and remove it from fabric netlists	2020-11-22 20:25:03 -07:00
verilog_testbench_options.cpp	[Tool] Move icarus and signal initialization options to testbench generator	2020-11-22 16:01:31 -07:00
verilog_testbench_options.h	[Tool] Move icarus and signal initialization options to testbench generator	2020-11-22 16:01:31 -07:00
verilog_testbench_utils.cpp	[Tool] Add signal initialization to Verilog testbench generator and remove it from fabric netlists	2020-11-22 20:25:03 -07:00
verilog_testbench_utils.h	[Tool] Add signal initialization to Verilog testbench generator and remove it from fabric netlists	2020-11-22 20:25:03 -07:00
verilog_top_module.cpp	removed redundant include files in all the verilog netlists except the top one	2020-06-11 19:28:13 -06:00
verilog_top_module.h	plug in netlist manager and now the include_netlist appears in one unique file	2020-04-23 20:42:11 -06:00
verilog_top_testbench.cpp	[Tool] Add signal initialization to Verilog testbench generator and remove it from fabric netlists	2020-11-22 20:25:03 -07:00
verilog_top_testbench.h	[Tool] Add signal initialization to Verilog testbench generator and remove it from fabric netlists	2020-11-22 20:25:03 -07:00
verilog_wire.cpp	removed redundant include files in all the verilog netlists except the top one	2020-06-11 19:28:13 -06:00
verilog_wire.h	removed redundant include files in all the verilog netlists except the top one	2020-06-11 19:28:13 -06:00
verilog_writer_utils.cpp	[OpenFPGA Tool] Critical bug fix for Verilog testbenches for memory bank and frame-based configuration protocol	2020-09-25 21:05:20 -06:00
verilog_writer_utils.h	[OpenFPGA Tool] Critical bug fix for Verilog testbenches for memory bank and frame-based configuration protocol	2020-09-25 21:05:20 -06:00