| .. |
|
verilog_api.c
|
use const RRGSB to be more runtime and memory efficient, updating SDC generator to use RRGSB
|
2019-06-10 12:50:10 -06:00 |
|
verilog_api.h
|
Update VPR7 X2P with new engine
|
2019-04-26 12:23:47 -06:00 |
|
verilog_autocheck_top_testbench.c
|
clean warnings
|
2019-05-24 16:48:08 -06:00 |
|
verilog_autocheck_top_testbench.h
|
clean warnings
|
2019-05-24 16:48:08 -06:00 |
|
verilog_compact_netlist.c
|
merge from multimode_clb bug fixing
|
2019-06-13 15:59:34 -06:00 |
|
verilog_compact_netlist.h
|
fix a critical bug in num_reserved_sram_ports
|
2019-06-05 17:31:01 -06:00 |
|
verilog_decoder.c
|
fixed a bug in Verilog generator supporting SRAM5T
|
2019-06-13 14:42:39 -06:00 |
|
verilog_decoder.h
|
add explicit port mapping for inverters of memory decoders
|
2019-06-10 17:36:14 -06:00 |
|
verilog_formal_random_top_testbench.c
|
clean warnings
|
2019-05-24 16:48:08 -06:00 |
|
verilog_formal_random_top_testbench.h
|
clean warnings
|
2019-05-24 16:48:08 -06:00 |
|
verilog_formality_autodeck.c
|
cleaned unused variables
|
2019-05-13 14:45:02 -06:00 |
|
verilog_formality_autodeck.h
|
Update VPR7 X2P with new engine
|
2019-04-26 12:23:47 -06:00 |
|
verilog_global.c
|
Update VPR7 X2P with new engine
|
2019-04-26 12:23:47 -06:00 |
|
verilog_global.h
|
Update VPR7 X2P with new engine
|
2019-04-26 12:23:47 -06:00 |
|
verilog_include_netlists.c
|
add explicit port mapping for inverters of memory decoders
|
2019-06-10 17:36:14 -06:00 |
|
verilog_include_netlists.h
|
add explicit port mapping for inverters of memory decoders
|
2019-06-10 17:36:14 -06:00 |
|
verilog_modelsim_autodeck.c
|
Update VPR7 X2P with new engine
|
2019-04-26 12:23:47 -06:00 |
|
verilog_modelsim_autodeck.h
|
Update VPR7 X2P with new engine
|
2019-04-26 12:23:47 -06:00 |
|
verilog_pbtypes.c
|
Avoid configuration bits for module wihch don't require them
|
2019-06-20 09:40:41 -06:00 |
|
verilog_pbtypes.h
|
support bus explicit port mapping to standard cells (for BRAMs)
|
2019-06-14 11:09:15 -06:00 |
|
verilog_primitives.c
|
support bus explicit port mapping to standard cells (for BRAMs)
|
2019-06-14 11:09:15 -06:00 |
|
verilog_primitives.h
|
Update VPR7 X2P with new engine
|
2019-04-26 12:23:47 -06:00 |
|
verilog_report_timing.c
|
Report timing modified to have only one liners
|
2019-06-20 14:10:39 -06:00 |
|
verilog_report_timing.h
|
updated bitstream to use new RRSwitchBlock as well as the report timing engine
|
2019-05-24 12:54:10 -06:00 |
|
verilog_routing.c
|
c++ string is not working, use char which is stable
|
2019-06-13 18:38:46 -06:00 |
|
verilog_routing.h
|
use const RRGSB to be more runtime and memory efficient, updating SDC generator to use RRGSB
|
2019-06-10 12:50:10 -06:00 |
|
verilog_sdc.c
|
use const RRGSB to be more runtime and memory efficient, updating SDC generator to use RRGSB
|
2019-06-10 12:50:10 -06:00 |
|
verilog_sdc.h
|
use const RRGSB to be more runtime and memory efficient, updating SDC generator to use RRGSB
|
2019-06-10 12:50:10 -06:00 |
|
verilog_sdc_pb_types.c
|
Break memories even in the clb sdc
|
2019-06-16 14:27:29 -06:00 |
|
verilog_sdc_pb_types.h
|
clean up warnings in SDC pb_type generator
|
2019-05-24 15:23:38 -06:00 |
|
verilog_submodules.c
|
add explicit port mapping for inverters of memory decoders
|
2019-06-10 17:36:14 -06:00 |
|
verilog_submodules.h
|
Update VPR7 X2P with new engine
|
2019-04-26 12:23:47 -06:00 |
|
verilog_tcl_utils.c
|
updated SDC generator to embrace the RRGSB data structure
|
2019-06-10 14:47:27 -06:00 |
|
verilog_tcl_utils.h
|
updated SDC generator to embrace the RRGSB data structure
|
2019-06-10 14:47:27 -06:00 |
|
verilog_top_netlist_utils.c
|
clean up DeviceRRGSB internal data and member functions
|
2019-06-07 14:45:56 -06:00 |
|
verilog_top_netlist_utils.h
|
Update VPR7 X2P with new engine
|
2019-04-26 12:23:47 -06:00 |
|
verilog_top_testbench.c
|
clean warnings
|
2019-05-24 16:48:08 -06:00 |
|
verilog_top_testbench.h
|
clean warnings
|
2019-05-24 16:48:08 -06:00 |
|
verilog_utils.c
|
fix a bug in formal verification port for memory bank configuration circuits
|
2019-06-13 15:33:13 -06:00 |
|
verilog_utils.h
|
add explicit port mapping for inverters of memory decoders
|
2019-06-10 17:36:14 -06:00 |
|
verilog_verification_top_netlist.c
|
clean warnings
|
2019-05-24 16:48:08 -06:00 |
|
verilog_verification_top_netlist.h
|
clean warnings
|
2019-05-24 16:48:08 -06:00 |
be25b6dd66