tangxifan cf82d87e11 Merge branch 'multimode_clb' into tileable_routing		2019-06-20 18:18:20 -06:00
..
base	basically finished the coding of tileable rr_graph generator. testing to go	2019-06-20 18:17:07 -06:00
bitstream	use const RRGSB to be more runtime and memory efficient, updating SDC generator to use RRGSB	2019-06-10 12:50:10 -06:00
clb_pin_remap	cleaned unused variables	2019-05-13 14:45:02 -06:00
router	bug fixing for memory leaking in allocating pb_rr_graph and power estimation	2019-06-15 12:23:36 -06:00
shell	Merge branch 'multimode_clb' of https://github.com/LNIS-Projects/OpenFPGA into multimode_clb	2019-05-13 14:45:57 -06:00
spice	fix a bug for iopad SPICE generation	2019-06-11 11:43:56 -06:00
verilog	Merge branch 'multimode_clb' of https://github.com/LNIS-Projects/OpenFPGA into multimode_clb	2019-06-20 14:11:03 -06:00