tangxifan 9c7868cfab [hdl] add a counter design which is triggered by negative edges		2022-05-09 16:41:21 +08:00
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counter_4bit_2clock	[HDL] Fix a typo	2022-02-15 16:09:14 -08:00
counter_8bit_async_reset	[HDL] Add initial conditons to counter benchmarks so that yosys's post synthesis netlists can work	2022-02-15 15:21:08 -08:00
counter_8bit_async_resetb	[HDL] Add initial conditons to counter benchmarks so that yosys's post synthesis netlists can work	2022-02-15 15:21:08 -08:00
counter_8bit_negedge_async_reset	[hdl] add a counter design which is triggered by negative edges	2022-05-09 16:41:21 +08:00
counter_8bit_sync_reset	[HDL] Add initial conditons to counter benchmarks so that yosys's post synthesis netlists can work	2022-02-15 15:21:08 -08:00
counter_128bit_async_reset	[HDL] Add initial conditons to counter benchmarks so that yosys's post synthesis netlists can work	2022-02-15 15:21:08 -08:00
counter_128bit_async_resetb	[HDL] Add initial conditons to counter benchmarks so that yosys's post synthesis netlists can work	2022-02-15 15:21:08 -08:00