tangxifan
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9c7868cfab
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[hdl] add a counter design which is triggered by negative edges
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2022-05-09 16:41:21 +08:00 |
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tangxifan
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430580f138
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[HDL] Fix a typo
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2022-02-15 16:09:14 -08:00 |
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tangxifan
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a7786efde1
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[HDL] Now dual-clock counter has only 1 reset pin
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2022-02-15 16:07:50 -08:00 |
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tangxifan
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7121513396
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[HDL] Add initial conditons to counter benchmarks so that yosys's post synthesis netlists can work
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2022-02-15 15:21:08 -08:00 |
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tangxifan
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5a6874e9f1
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[Benchmark] Rename the dual clock counter benchmark to follow the naming convention on counter benchmarks
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2021-07-02 17:28:17 -06:00 |
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tangxifan
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0b6a9b06f5
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[Benchmark] Reorganize counter benchmarks. Move them to a directory and give specific naming regarding their functionality
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2021-07-02 10:39:07 -06:00 |