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formality_template.tcl
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Updated formality python script
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2019-09-27 14:00:57 -06:00 |
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fpgaflow_default_tool_path.conf
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Update fpgaflow_default_tool_path.conf
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2021-09-17 14:02:26 +08:00 |
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modelsim_proc.tcl
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Added task support for modelsim script
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2019-11-15 23:23:15 -07:00 |
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modelsim_runsim.tcl
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Fixed modelsim include references
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2020-06-11 19:28:13 -06:00 |
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qlf_yosys.ys
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[Script] Update quicklogic's script to output correct verilog file name
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2021-03-08 21:39:44 -07:00 |
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ys_tmpl_rewrite_flow.ys
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[Script] Split rewrite yosys scripts into two runs because yosys cannot output consistent verilog files using 'design -reset'
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2021-03-10 13:56:35 -07:00 |
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ys_tmpl_yosys_vpr_bram_dsp_dff_flow.ys
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[Flow] Update yosys script to not use sdff and dffe
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2021-10-30 14:56:54 -07:00 |
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ys_tmpl_yosys_vpr_bram_dsp_flow.ys
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[Flow] Disable DFFE and SDFF in no-ff Yosys scripts
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2021-10-30 13:29:38 -07:00 |
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ys_tmpl_yosys_vpr_bram_flow.ys
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[Flow] Disable DFFE and SDFF in no-ff Yosys scripts
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2021-10-30 14:36:43 -07:00 |
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ys_tmpl_yosys_vpr_dff_flow.ys
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[Flow] Enable flatten for dff-related yosys scripts
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2021-10-30 15:12:34 -07:00 |
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ys_tmpl_yosys_vpr_dsp_flow.ys
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[Flow] Disable DFFE and SDFF in no-ff Yosys scripts
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2021-10-30 14:34:37 -07:00 |
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ys_tmpl_yosys_vpr_flow.ys
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[Flow] Enable flatten for dff-related yosys scripts
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2021-10-30 15:12:34 -07:00 |
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ys_tmpl_yosys_vpr_flow_with_rewrite.ys
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[Flow] Enable flatten for dff-related yosys scripts
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2021-10-30 15:12:34 -07:00 |
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