91 lines
1.9 KiB
Plaintext
91 lines
1.9 KiB
Plaintext
# Yosys synthesis script for ${TOP_MODULE}
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#########################
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# Parse input files
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#########################
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# Read verilog files
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${READ_VERILOG_FILE}
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# Read technology library
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read_verilog -lib -specify ${YOSYS_CELL_SIM_VERILOG}
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#########################
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# Prepare for synthesis
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#########################
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# Identify top module from hierarchy
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hierarchy -check -top ${TOP_MODULE}
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# - Convert process blocks to AST
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proc
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# Flatten all the gates/primitives
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flatten
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# Identify tri-state buffers from 'z' signal in AST
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# with follow-up optimizations to clean up AST
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tribuf -logic
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opt_expr
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opt_clean
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# demote inout ports to input or output port
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# with follow-up optimizations to clean up AST
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deminout
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opt -nodffe -nosdff
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opt_expr
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opt_clean
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check
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opt -nodffe -nosdff
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wreduce -keepdc
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peepopt
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pmuxtree
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opt_clean
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#########################
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# Run coarse synthesis
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#########################
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# Extract arithmetic functions
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alumacc
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share
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opt -nodffe -nosdff
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fsm
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# Run a quick follow-up optimization to sweep out unused nets/signals
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opt -fast -nodffe -nosdff
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# Optimize any memory cells by merging share-able ports and collecting all the ports belonging to memorcy cells
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memory -nomap
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opt_clean
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#########################
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# Map logics to BRAMs
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#########################
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memory_bram -rules ${YOSYS_BRAM_MAP_RULES}
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techmap -map ${YOSYS_BRAM_MAP_VERILOG}
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opt -fast -mux_undef -undriven -fine -nodffe -nosdff
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memory_map
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opt -undriven -fine -nodffe -nosdff
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#########################
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# Map flip-flops
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#########################
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dfflegalize -cell $_DFF_P_ 0
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techmap -map +/adff2dff.v
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opt_expr -mux_undef
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simplemap
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opt_expr
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opt_merge
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opt_dff -nodffe -nosdff
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opt_clean
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opt -nodffe -nosdff
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#########################
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# Map LUTs
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#########################
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abc -lut ${LUT_SIZE}
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#########################
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# Check and show statisitics
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#########################
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hierarchy -check
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stat
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#########################
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# Output netlists
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#########################
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opt_clean -purge
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write_blif ${OUTPUT_BLIF}
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