tangxifan c33b9f1b9b [script] enable eval mode in tcl reg test		2022-12-02 12:07:27 -08:00
..
arch_bitstreams	[test] update arch bitstream and force a pin placement for the test case where external bistream is fixed	2022-09-20 14:14:18 -07:00
benchmarks	[test] fixed a few bugs	2022-09-29 15:32:31 -07:00
docs	Added first draft of fpga_task script	2019-08-09 00:17:06 -06:00
fabric_keys	[Arch] Add an example fabric key that models a shift-register-based QuickLogic memory bank using custom chain organization	2021-10-11 09:49:22 -07:00
misc	[script] fixed a bug on wrong path to the ace2 executable	2022-08-23 10:53:44 -07:00
openfpga_arch	Merge branch 'master' into rst_on_lut_strong	2022-10-13 16:01:57 -07:00
openfpga_cell_library	Merge pull request #864 from yunuseryilmaz18/master	2022-10-30 12:16:21 -07:00
openfpga_shell_scripts	[test] added a new test to validate explicit port direction in pin table support	2022-10-17 15:25:19 -07:00
openfpga_simulation_settings	[Script] Bug fix in slow clock frequency in shift register chain contraints	2021-10-06 16:49:01 -07:00
openfpga_yosys_techlib	[arch] fixed a few bugs	2022-05-09 17:22:48 +08:00
regression_test_scripts	[script] enable eval mode in tcl reg test	2022-12-02 12:07:27 -08:00
scripts	[test] add a small test to validate tcl integration	2022-12-02 11:43:46 -08:00
tasks	[test] hit the bug of tileable rr_graph skip it	2022-11-05 10:52:04 -07:00
tech	Added Power Model Files	2019-08-19 18:55:23 -06:00
vpr_arch	[arch] fixed a few bugs	2022-10-13 11:54:58 -07:00
.gitignore	Added first draft of fpga_task script	2019-08-09 00:17:06 -06:00