tangxifan ad5cce0ae8 [Test] Use frac_ff arch for SAPone; Otherwise Yosys cannot map reset signals		2021-10-30 15:11:07 -07:00
..
arch_bitstreams	[Architecture] Update external bitstream	2020-09-25 21:30:59 -06:00
benchmarks	[Benchmark] Rename the dual clock counter benchmark to follow the naming convention on counter benchmarks	2021-07-02 17:28:17 -06:00
docs	Added first draft of fpga_task script	2019-08-09 00:17:06 -06:00
fabric_keys	[Architecture] Add example fabric key using multiple regions	2020-09-29 14:14:50 -06:00
misc	[Flow] Update yosys script to not use sdff and dffe	2021-10-30 14:56:54 -07:00
openfpga_arch	Fixed port names for mult_36x36	2021-10-26 19:14:43 +05:00
openfpga_cell_library	[HDL] Fixed critical bugs in multi-mode FF HDL modeling, which caused reset signal unconnected	2021-10-30 11:45:01 -07:00
openfpga_shell_scripts	[Test] Disable ACE2 in implicit verilog test cases due to Yosys upgrade	2021-10-30 14:49:56 -07:00
openfpga_simulation_settings	[Arch] Add simulation setting for 8-clock architectures	2021-02-22 11:10:03 -07:00
openfpga_yosys_techlib	[Script] Add dff with active-low async reset to default yosys tech lib	2021-07-02 11:17:43 -06:00
regression_test_scripts	[Test] Disable all the quicklogic tests due to missing support in Yosys v0.10 release	2021-10-30 13:20:58 -07:00
scripts	Fixing python string formatting: clean_up_and_exit calls in run_fpga_flow.py	2021-10-18 10:45:35 +00:00
tasks	[Test] Use frac_ff arch for SAPone; Otherwise Yosys cannot map reset signals	2021-10-30 15:11:07 -07:00
tech	Added Power Model Files	2019-08-19 18:55:23 -06:00
vpr_arch	[Arch] Patch architecture due to missing mode bit definition	2021-07-02 11:41:29 -06:00
.gitignore	Added first draft of fpga_task script	2019-08-09 00:17:06 -06:00