tangxifan f02f3c10d4 [Test] Fix bugs on the remaining implicit verilog test cases		2022-02-15 16:49:15 -08:00
..
arch_bitstreams	[Architecture] Update external bitstream	2020-09-25 21:30:59 -06:00
benchmarks	[HDL] Fix a typo	2022-02-15 16:09:14 -08:00
docs	Added first draft of fpga_task script	2019-08-09 00:17:06 -06:00
fabric_keys	[Arch] Add an example fabric key that models a shift-register-based QuickLogic memory bank using custom chain organization	2021-10-11 09:49:22 -07:00
misc	Changed HDL files reading to be as a single compilation unit in yosys_vpr flow for Verific mode. Changed '' variable to 'read_verilog ' in yosys template scripts. Updated task configs accordingly.	2022-01-17 13:21:29 +05:00
openfpga_arch	[Flow] Add openfpga arch for DSP with registers	2022-01-02 19:59:33 -08:00
openfpga_cell_library	Merge branch 'master' of https://github.com/lnis-uofu/OpenFPGA into upstream	2021-10-31 11:51:34 -07:00
openfpga_shell_scripts	[Script] Now counter benchmarks should pass on the implicit verilog test case	2022-02-15 16:47:14 -08:00
openfpga_simulation_settings	[Script] Bug fix in slow clock frequency in shift register chain contraints	2021-10-06 16:49:01 -07:00
openfpga_yosys_techlib	[Script] Add dff with active-low async reset to default yosys tech lib	2021-07-02 11:17:43 -06:00
regression_test_scripts	[Test] Add new test case to regression tests	2022-02-14 15:58:53 -08:00
scripts	[Script] Fix a bug	2022-02-14 23:11:42 -08:00
tasks	[Test] Fix bugs on the remaining implicit verilog test cases	2022-02-15 16:49:15 -08:00
tech	Added Power Model Files	2019-08-19 18:55:23 -06:00
vpr_arch	[Test] Now use 4x4 fabric in testing write_rr_gsb commands	2022-01-26 11:41:48 -08:00
.gitignore	Added first draft of fpga_task script	2019-08-09 00:17:06 -06:00