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adder.v
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[Architecture] Reorganize the cell netlists and update architecture files accordingly
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2020-09-25 11:55:28 -06:00 |
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aib.v
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[Architecture] Reorganize the cell netlists and update architecture files accordingly
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2020-09-25 11:55:28 -06:00 |
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buf4.v
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bugfix in alt
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2021-02-08 23:04:00 -05:00 |
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dff.v
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[arch] add arch that supports negative edge triggered flip-flop
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2022-05-09 16:32:01 +08:00 |
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dpram.v
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Update dpram.v
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2022-10-27 08:29:56 +03:00 |
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dpram1k.v
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Update dpram1k.v
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2022-10-26 16:32:14 +03:00 |
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dpram8k.v
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[HDL] Add dual-port RAM 1024x8 bit HDL decription as a primitive module of OpenFPGA cells
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2021-03-17 15:15:22 -06:00 |
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dpram16k.v
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Update dpram16k.v
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2022-10-27 08:28:58 +03:00 |
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dpram_2048x8.v
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Update dpram_2048x8.v
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2022-10-26 16:31:16 +03:00 |
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frac_lut4_arith.v
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[HDL] Patch the superLUT HDL code to be consistent with (qlf_k4n8_sim.v)[https://github.com/lnsharma/yosys/blob/add_qlf_k4n8_dev/techlibs/quicklogic/qlf_k4n8_cells_sim.v]
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2021-03-11 15:23:14 -07:00 |
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frac_mem_32k.v
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Update frac_mem_32k.v
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2022-10-20 09:48:29 +03:00 |
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frac_mult_16x16.v
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[HDL] Bug fix in HDL modeling of multi-mode 16-bit DSP block
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2021-04-24 14:57:09 -06:00 |
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frac_mult_36x36.v
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Added new cell library for fracturable dsp36
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2022-10-21 17:30:20 +03:00 |
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gpio.v
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[Test] Update test case by using GPIO with config_done signals
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2022-02-24 09:49:34 -08:00 |
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inv.v
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adding dff synth
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2021-02-09 10:34:54 -05:00 |
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latch.v
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[Architecture] Reorganize the cell netlists and update architecture files accordingly
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2020-09-25 11:55:28 -06:00 |
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lut6.v
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[Architecture] Reorganize the cell netlists and update architecture files accordingly
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2020-09-25 11:55:28 -06:00 |
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mult_8x8.v
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[HDL] Add HDL for 8-bit single-mode multiplier
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2021-03-23 15:36:09 -06:00 |
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mult_32x32.v
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[Architecture] Reorganize the cell netlists and update architecture files accordingly
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2020-09-25 11:55:28 -06:00 |
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mult_36x36.v
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[Architecture] Reorganize the cell netlists and update architecture files accordingly
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2020-09-25 11:55:28 -06:00 |
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mux2.v
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[test] validate mux2 at last stage
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2024-09-18 17:40:13 -07:00 |
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or2.v
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no need for dff*, but need tap_buf4
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2021-02-08 23:00:13 -05:00 |
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spram_4x1.v
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Microbenchmarks of Single-Port RAM and Associated Example Architecture Files as well as Test Cases (#200)
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2021-01-29 10:19:05 -07:00 |
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sram.v
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[HDL] Temporarily disable WLR func in primitive HDL modeling
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2021-09-20 17:07:51 -07:00 |
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tap_buf4.v
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no need for dff*, but need tap_buf4
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2021-02-08 22:27:57 -05:00 |
7b4f06ed7d