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build_decoder_modules.cpp
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[FPGA-Verilog] Upgrade fpga-verilog to support decoders with WLR
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2021-09-20 17:07:26 -07:00 |
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build_decoder_modules.h
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add configuration bus nets for memory bank decoders at top module
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2020-06-11 19:31:13 -06:00 |
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build_device_module.cpp
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[Engine] Now the MemoryBankShiftRegisterBanks data structure combines both BL/WL data structures as the unified interface
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2021-10-08 15:25:37 -07:00 |
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build_device_module.h
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[Engine] Now the MemoryBankShiftRegisterBanks data structure combines both BL/WL data structures as the unified interface
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2021-10-08 15:25:37 -07:00 |
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build_essential_modules.cpp
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[OpenFPGA Tool] Bug fix in creating auto-generated cells using lib_name
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2020-09-25 14:54:51 -06:00 |
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build_essential_modules.h
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start integrating module graph builder
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2020-02-12 17:53:23 -07:00 |
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build_fabric_global_port_info.cpp
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[Engine] Upgrade check codes for WL CCFF
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2021-10-01 17:23:10 -07:00 |
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build_fabric_global_port_info.h
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[Engine] Upgrade check codes for WL CCFF
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2021-10-01 17:23:10 -07:00 |
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build_fabric_io_location_map.cpp
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[Tool] Adapted tools to support I/O in center grid
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2020-12-04 18:50:13 -07:00 |
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build_fabric_io_location_map.h
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[Tool] Split io location mapping builder from fabric builder
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2020-11-02 18:27:34 -07:00 |
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build_grid_module_duplicated_pins.cpp
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[Tool] Trim dead codes in port naming function
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2021-03-13 20:23:08 -07:00 |
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build_grid_module_duplicated_pins.h
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[Tool] Change pin naming of grid modules to be related to architecture port names
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2021-03-13 20:05:18 -07:00 |
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build_grid_module_utils.cpp
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[Tool] Trim dead codes in port naming function
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2021-03-13 20:23:08 -07:00 |
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build_grid_module_utils.h
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[Tool] Change pin naming of grid modules to be related to architecture port names
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2021-03-13 20:05:18 -07:00 |
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build_grid_modules.cpp
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[Engine] Merge BL/WLs in the Grid/CB/SB modules
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2021-09-15 11:27:55 -07:00 |
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build_grid_modules.h
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add frame decoder builder to all the module graph builder except the top-level
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2020-06-11 19:31:09 -06:00 |
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build_lut_modules.cpp
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[Tool] Support superLUT circuit model in core engine
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2021-02-09 20:23:05 -07:00 |
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build_lut_modules.h
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add lut module builder
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2020-02-12 19:52:41 -07:00 |
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build_memory_modules.cpp
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[Engine] Upgraded fabric generator to support single shift register bank per configuration region for QuickLogic memory bank
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2021-09-29 16:57:49 -07:00 |
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build_memory_modules.h
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[Engine] Upgraded fabric generator to support single shift register bank per configuration region for QuickLogic memory bank
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2021-09-29 16:57:49 -07:00 |
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build_module_graph_utils.cpp
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add mux module builder
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2020-02-12 19:45:14 -07:00 |
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build_module_graph_utils.h
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add mux module builder
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2020-02-12 19:45:14 -07:00 |
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build_mux_modules.cpp
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[Tool] bug fix in spypad lut
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2021-02-09 22:53:18 -07:00 |
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build_mux_modules.h
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add mux module builder
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2020-02-12 19:45:14 -07:00 |
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build_routing_module_utils.cpp
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[Tool] Change routing module port naming to include architecture port names
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2021-03-14 19:35:49 -06:00 |
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build_routing_module_utils.h
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[Tool] Change routing module port naming to include architecture port names
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2021-03-14 19:35:49 -06:00 |
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build_routing_modules.cpp
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[Engine] Merge BL/WLs in the Grid/CB/SB modules
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2021-09-15 11:27:55 -07:00 |
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build_routing_modules.h
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add frame decoder builder to all the module graph builder except the top-level
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2020-06-11 19:31:09 -06:00 |
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build_top_module.cpp
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[Engine] Upgrade fabric generator to support multiple shift register banks in a configuration region
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2021-10-09 16:44:04 -07:00 |
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build_top_module.h
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[Engine] Now the MemoryBankShiftRegisterBanks data structure combines both BL/WL data structures as the unified interface
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2021-10-08 15:25:37 -07:00 |
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build_top_module_connection.cpp
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[Engine] Now global port can be connected partial pins of a tile port
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2022-03-20 11:36:03 +08:00 |
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build_top_module_connection.h
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[Tool] Change pin naming of grid modules to be related to architecture port names
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2021-03-13 20:05:18 -07:00 |
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build_top_module_directs.cpp
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[Tool] Trim dead codes in port naming function
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2021-03-13 20:23:08 -07:00 |
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build_top_module_directs.h
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[Tool] Change pin naming of grid modules to be related to architecture port names
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2021-03-13 20:05:18 -07:00 |
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build_top_module_memory.cpp
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[Engine] Upgrade fabric generator to support multiple shift register banks in a configuration region
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2021-10-09 16:44:04 -07:00 |
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build_top_module_memory.h
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[Engine] Upgrade fabric generator to support multiple shift register banks in a configuration region
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2021-10-09 16:44:04 -07:00 |
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build_top_module_memory_bank.cpp
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[Engine] Bug fix
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2021-10-09 18:46:20 -07:00 |
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build_top_module_memory_bank.h
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[Engine] Upgrade fabric generator to support multiple shift register banks in a configuration region
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2021-10-09 16:44:04 -07:00 |
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build_top_module_memory_utils.h
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[Engine] Place QL memory bank source codes in a separated source file so that integration to OpenFPGA open-source version is easier
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2021-09-05 13:23:38 -07:00 |
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build_top_module_utils.cpp
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start moving top-module builder. Now adapt the utils
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2020-02-14 10:00:24 -07:00 |
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build_top_module_utils.h
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start moving top-module builder. Now adapt the utils
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2020-02-14 10:00:24 -07:00 |
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build_wire_modules.cpp
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[OPENFPGA LIBRARY] change method names to be consistent with FPGA-SPICE needs
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2020-09-20 12:03:10 -06:00 |
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build_wire_modules.h
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add wire module builder
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2020-02-12 19:57:15 -07:00 |
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fabric_global_port_info.cpp
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[Engine] Upgrade check codes for WL CCFF
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2021-10-01 17:23:10 -07:00 |
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fabric_global_port_info.h
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[Engine] Upgrade check codes for WL CCFF
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2021-10-01 17:23:10 -07:00 |
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fabric_global_port_info_fwd.h
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[Tool] Use use standard data structure to store global port information
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2020-11-10 19:07:28 -07:00 |
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fabric_hierarchy_writer.cpp
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format fix in the fabric hierarchy and grid SDC hierarchy to be complaint to YAML format
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2020-06-11 19:31:05 -06:00 |
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fabric_hierarchy_writer.h
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add --depth option to fabric hierarchy writer
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2020-06-11 19:31:04 -06:00 |
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fabric_key_writer.cpp
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[Engine] Bug fix for fabric key writer which errors out when there is no BL/WL banks in the architecture
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2021-10-11 09:40:02 -07:00 |
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fabric_key_writer.h
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[Engine] Bug fix for fabric key writer which errors out when there is no BL/WL banks in the architecture
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2021-10-11 09:40:02 -07:00 |
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memory_bank_shift_register_banks.cpp
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[FPGA-Bitstream] Upgrade bitstream generator to support multiple shift register banks in a configuration region for QuickLogic memory bank
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2021-10-09 20:39:45 -07:00 |
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memory_bank_shift_register_banks.h
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[FPGA-Bitstream] Upgrade bitstream generator to support multiple shift register banks in a configuration region for QuickLogic memory bank
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2021-10-09 20:39:45 -07:00 |
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module_manager.cpp
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[Engine] Start developing QL memory bank: upgrade infrastructures of fabric builder
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2021-09-03 17:55:23 -07:00 |
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module_manager.h
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[Engine] Start developing QL memory bank: upgrade infrastructures of fabric builder
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2021-09-03 17:55:23 -07:00 |
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module_manager_fwd.h
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[OpenFPGA Tool] Support configurable regions in module manager
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2020-09-28 18:13:07 -06:00 |
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