Go to file
tangxifan 9c66a35bf6 [arch language] Now circuit library will automatically identify the default circuit model if needed 2020-08-23 14:06:03 -06:00
.travis [regression test] Add more tests for thru channels and deploy to CI 2020-08-19 20:11:37 -06:00
abc Add latest abc and update ace dependence 2019-05-03 18:56:03 -06:00
ace2 Now we use the ace from VTR 2019-07-16 17:00:09 -06:00
cmake copy missing cmake modules from vtr project 2020-01-03 21:57:19 -05:00
docs [documentation] remove the limitation on through channels 2020-08-19 20:12:49 -06:00
libopenfpga [arch language] Now circuit library will automatically identify the default circuit model if needed 2020-08-23 14:06:03 -06:00
libs bug fixing to constant string to display interconnect names 2020-04-07 18:28:19 -06:00
openfpga added a new XML syntax: initial offset for physical mode pin mapping 2020-08-19 14:43:44 -06:00
openfpga_flow [regression test] Add more tests for thru channels and deploy to CI 2020-08-19 20:11:37 -06:00
vpr bug fix in through channel support in tileable routing 2020-08-19 20:01:50 -06:00
yosys use adapt yosys Makefile for OpenFPGA framework 2019-11-27 14:42:47 -07:00
.dockerignore Added dockerignore + minor changes in openfpga_flow script 2019-08-17 16:22:52 -06:00
.gitignore modify the git ignore list for ctags so that we only ignore those tags in specific folders 2020-01-03 21:17:40 -07:00
.gitmodules Update .gitmodules 2018-12-10 12:07:05 -07:00
.travis.yml refactored CI for split regression tests in terms of OpenFPGA tools 2020-07-27 17:05:46 -06:00
CMakeLists.txt remove obselete codes and update regression tests 2020-07-04 17:31:34 -06:00
Dockerfile . 2020-07-09 09:25:11 -06:00
LICENSE Create LICENSE 2018-06-26 21:52:08 -07:00
README.md remove debug mode in compilation guidelines as we can use release in default now 2020-07-04 19:19:06 -06:00
README_Benchmarks.md Correction of the global make, the fpga_flow and the doc 2018-11-20 14:47:15 -07:00
deploy_key.enc Updated Encrypt Key 2019-11-02 16:37:00 -06:00
openfpga.sh Added GCC paths to source 2020-04-06 00:35:28 -06:00
run_local.bat Working lattice benchmark unclean commit 2019-08-08 18:08:39 -06:00
run_local.sh Added build files in .gitignore 2019-08-17 22:59:54 -06:00
run_test.sh Travis Test: Run 2 2019-11-01 23:12:56 -06:00

README.md

Getting Started with OpenFPGA

Build Status Documentation Status

Introduction

The OpenFPGA framework is the first open-source FPGA IP generator supporting highly-customizable homogeneous FPGA architectures. OpenFPGA provides a full set of EDA support for customized FPGAs, including Verilog-to-bitstream generation and self-testing verification. OpenFPGA opens the door to democratizing FPGA technology and EDA techniques, with agile prototyping approaches and constantly evolving EDA tools for chip designers and researchers.

Compilation

Dependencies and help using docker can be found here.

Compilation Steps:

# Clone the repository and go inside it
git clone https://github.com/LNIS-Projects/OpenFPGA.git && cd OpenFPGA
mkdir build && cd build            # Create a folder named build in the OpenPFGA repository
cmake ..                           # Create a Makefile in this folder using cmake
make                               # Compile the tool and its dependencies

cmake3.12 is recommended to compile OpenFPGA with GUI

Quick Compilation Verification To quickly verify the tool is well compiled, user can run the following command from OpenFPGA root repository.

python3 openfpga_flow/scripts/run_fpga_task.py compilation_verification --debug --show_thread_logs

Python3 and iVerilog v10.1+ are required. GUI will pop-up if enabled during compilation.

Supported Operating Systems We currently target OpenFPGA for:

  1. Ubuntu 18.04
  2. Red Hat 7.5

The tool was tested with these operating systems. It might work with earlier versions and other distributions.

Documentation

OpenFPGA's full documentation includes tutorials, descriptions of the design flow, and tool options.

Tutorials

You can find some tutorials in the ./tutorials folder. This will help you get more familiar with the tool and use OpenFPGA under different configurations.