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Travis Test: Run 2

This commit is contained in:
Ganesh Gore 2019-11-01 23:12:56 -06:00
parent 5c8ca81645
commit 94b60b9714
1 changed files with 60 additions and 60 deletions
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120
run_test.sh
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@ -18,14 +18,13 @@
# Test popular multi-mode architecture
python3 openfpga_flow/scripts/run_fpga_flow.py \
./openfpga_flow/arch/template/k6_N10_sram_chain_HC_template.xml \
./openfpga_flow/benchmarks/Test_Modes/test_modes.blif \
./openfpga_flow/benchmarks/test_modes/test_modes.blif \
--fpga_flow vpr_blif \
--top_module test_modes \
--activity_file ./openfpga_flow/benchmarks/Test_Modes/test_modes.act \
--base_verilog ./openfpga_flow/benchmarks/Test_Modes/test_modes.v \
--activity_file ./openfpga_flow/benchmarks/test_modes/test_modes.act \
--base_verilog ./openfpga_flow/benchmarks/test_modes/test_modes.v \
--power \
--power_tech ./openfpga_flow/tech/PTM_45nm/45nm.xml \
#--fix_route_chan_width 300 \
--min_route_chan_width 1.3 \
--vpr_fpga_verilog \
--vpr_fpga_verilog_dir . \
@ -42,64 +41,65 @@ python3 openfpga_flow/scripts/run_fpga_flow.py \
--vpr_fpga_verilog_print_sdc_pnr \
--vpr_fpga_verilog_print_sdc_analysis \
--vpr_fpga_x2p_compact_routing_hierarchy \
--end_flow_with_test
--end_flow_with_test \
--vpr_fpga_verilog_print_modelsim_autodeck /uusoc/facility/cad_tools/Mentor/modelsim10.7b/modeltech/modelsim.ini
# Test Standard cell MUX2
python3 openfpga_flow/scripts/run_fpga_flow.py \
./openfpga_flow/arch/template/k8_N10_sram_chain_FC_template.xml \
./openfpga_flow/benchmarks/Test_Modes/test_modes.blif \
--fpga_flow vpr_blif \
--top_module test_modes \
--activity_file ./openfpga_flow/benchmarks/Test_Modes/test_modes.act \
--base_verilog ./openfpga_flow/benchmarks/Test_Modes/test_modes.v \
--power \
--power_tech ./openfpga_flow/tech/PTM_45nm/45nm.xml \
#--fix_route_chan_width 300 \
--min_route_chan_width 1.3 \
--vpr_fpga_verilog \
--vpr_fpga_verilog_dir . \
--vpr_fpga_x2p_rename_illegal_port \
--vpr_fpga_verilog_include_icarus_simulator \
--vpr_fpga_verilog_formal_verification_top_netlist \
--vpr_fpga_verilog_include_timing \
--vpr_fpga_verilog_include_signal_init \
--vpr_fpga_verilog_print_autocheck_top_testbench \
--debug \
--vpr_fpga_bitstream_generator \
--vpr_fpga_verilog_print_user_defined_template \
--vpr_fpga_verilog_print_report_timing_tcl \
--vpr_fpga_verilog_print_sdc_pnr \
--vpr_fpga_verilog_print_sdc_analysis \
--vpr_fpga_x2p_compact_routing_hierarchy \
--end_flow_with_test
# # Test Standard cell MUX2
# python3 openfpga_flow/scripts/run_fpga_flow.py \
# ./openfpga_flow/arch/template/k8_N10_sram_chain_FC_template.xml \
# ./openfpga_flow/benchmarks/Test_Modes/test_modes.blif \
# --fpga_flow vpr_blif \
# --top_module test_modes \
# --activity_file ./openfpga_flow/benchmarks/Test_Modes/test_modes.act \
# --base_verilog ./openfpga_flow/benchmarks/Test_Modes/test_modes.v \
# --power \
# --power_tech ./openfpga_flow/tech/PTM_45nm/45nm.xml \
# #--fix_route_chan_width 300 \
# --min_route_chan_width 1.3 \
# --vpr_fpga_verilog \
# --vpr_fpga_verilog_dir . \
# --vpr_fpga_x2p_rename_illegal_port \
# --vpr_fpga_verilog_include_icarus_simulator \
# --vpr_fpga_verilog_formal_verification_top_netlist \
# --vpr_fpga_verilog_include_timing \
# --vpr_fpga_verilog_include_signal_init \
# --vpr_fpga_verilog_print_autocheck_top_testbench \
# --debug \
# --vpr_fpga_bitstream_generator \
# --vpr_fpga_verilog_print_user_defined_template \
# --vpr_fpga_verilog_print_report_timing_tcl \
# --vpr_fpga_verilog_print_sdc_pnr \
# --vpr_fpga_verilog_print_sdc_analysis \
# --vpr_fpga_x2p_compact_routing_hierarchy \
# --end_flow_with_test
# Test local encoder feature
python3 openfpga_flow/scripts/run_fpga_flow.py \
./openfpga_flow/arch/template/k6_N10_sram_chain_HC_local_encoder_template.xml \
./openfpga_flow/benchmarks/Test_Modes/test_modes.blif \
--fpga_flow vpr_blif \
--top_module test_modes \
--activity_file ./openfpga_flow/benchmarks/Test_Modes/test_modes.act \
--base_verilog ./openfpga_flow/benchmarks/Test_Modes/test_modes.v \
--power \
--power_tech ./openfpga_flow/tech/PTM_45nm/45nm.xml \
--fix_route_chan_width 300 \
--vpr_fpga_verilog \
--vpr_fpga_verilog_dir . \
--vpr_fpga_x2p_rename_illegal_port \
--vpr_fpga_verilog_include_icarus_simulator \
--vpr_fpga_verilog_formal_verification_top_netlist \
--vpr_fpga_verilog_include_timing \
--vpr_fpga_verilog_include_signal_init \
--vpr_fpga_verilog_print_autocheck_top_testbench \
--debug \
--vpr_fpga_bitstream_generator \
--vpr_fpga_verilog_print_user_defined_template \
--vpr_fpga_verilog_print_report_timing_tcl \
--vpr_fpga_verilog_print_sdc_pnr \
--vpr_fpga_verilog_print_sdc_analysis \
--vpr_fpga_x2p_compact_routing_hierarchy \
--end_flow_with_test
# # Test local encoder feature
# python3 openfpga_flow/scripts/run_fpga_flow.py \
# ./openfpga_flow/arch/template/k6_N10_sram_chain_HC_local_encoder_template.xml \
# ./openfpga_flow/benchmarks/Test_Modes/test_modes.blif \
# --fpga_flow vpr_blif \
# --top_module test_modes \
# --activity_file ./openfpga_flow/benchmarks/Test_Modes/test_modes.act \
# --base_verilog ./openfpga_flow/benchmarks/Test_Modes/test_modes.v \
# --power \
# --power_tech ./openfpga_flow/tech/PTM_45nm/45nm.xml \
# --fix_route_chan_width 300 \
# --vpr_fpga_verilog \
# --vpr_fpga_verilog_dir . \
# --vpr_fpga_x2p_rename_illegal_port \
# --vpr_fpga_verilog_include_icarus_simulator \
# --vpr_fpga_verilog_formal_verification_top_netlist \
# --vpr_fpga_verilog_include_timing \
# --vpr_fpga_verilog_include_signal_init \
# --vpr_fpga_verilog_print_autocheck_top_testbench \
# --debug \
# --vpr_fpga_bitstream_generator \
# --vpr_fpga_verilog_print_user_defined_template \
# --vpr_fpga_verilog_print_report_timing_tcl \
# --vpr_fpga_verilog_print_sdc_pnr \
# --vpr_fpga_verilog_print_sdc_analysis \
# --vpr_fpga_x2p_compact_routing_hierarchy \
# --end_flow_with_test
# Test tileable routing feature
#python3 openfpga_flow/scripts/run_fpga_flow.py \