tangxifan 542fadaaae allow users to use VPR critical path delay in OpenFPGA simulation		2020-02-28 12:10:27 -07:00
..
annotation	add more methods to acquire physical truth table from physical pb	2020-02-25 21:21:44 -07:00
base	allow users to use VPR critical path delay in OpenFPGA simulation	2020-02-28 12:10:27 -07:00
fabric	adapt pnr sdc grid writer	2020-02-27 21:06:33 -07:00
fpga_bitstream	debugged LUT bitstream	2020-02-26 11:42:18 -07:00
fpga_sdc	use user defined critical path delay in SDC generation	2020-02-28 11:24:39 -07:00
fpga_verilog	add simulation ini file writer	2020-02-27 18:01:47 -07:00
mux_lib	add mux library builder	2020-02-12 14:58:23 -07:00
repack	debugged LUT bitstream	2020-02-26 11:42:18 -07:00
tile_direct	tile direct supports inter-column/inter-row direct connections	2020-02-15 13:42:53 -07:00
utils	bug fixed for clock names	2020-02-27 16:51:55 -07:00
vpr_wrapper	add rr_segment binding to circuit model	2020-02-12 11:21:40 -07:00
ctag_src.sh	add ctags script to index openfpga source files	2020-01-24 10:15:16 -07:00
main.cpp	bring pnr sdc generator online and fixed minor bugs in bitstream writing	2020-02-28 11:14:50 -07:00