tangxifan 977283dd34 [core] typo		2024-07-10 14:12:49 -07:00
..
FIR_filter	…
FSM_three_code	…
RISC_posedge_clk	…
SAPone	…
adder	…
and2	…
and2_latch	…
and2_latch_2clock	…
and2_or2	…
and2_pipelined	…
and4	…
asyn_spram_4x1	…
blinking	…
clk_cond	[test] reworking the testcase to validate clock network with internal drivers	2024-07-10 11:36:22 -07:00
clk_divider	[benchmark] add clock divider	2023-01-13 16:39:06 -08:00
clk_gate	…
clk_on_lut	[test] add a new benchmark to validate clock on LUT	2024-07-09 18:42:39 -07:00
config_loader	…
counters	…
discrete_dffn	[test] now use a new benchmark: discrete dffn to validate the clk gen locally feature	2023-01-15 13:09:40 -08:00
dual_port_ram_1k	…
dual_port_ram_16k	…
fifo/rtl	…
mac	…
mult	[test] adding a new test case to validate the bitstream overloading for DSP blocks	2023-01-24 14:58:52 -08:00
or2	…
pipelined_8bit_adder	…
routing_test	…
rst_and_clk_on_lut	[test] typo	2024-07-09 22:54:33 -07:00
rst_cond	[core] typo	2024-07-10 14:12:49 -07:00
rst_on_lut	…
rst_on_lut_4bit	[test] deploy new benchmarks	2024-06-02 14:23:08 -07:00
rst_on_lut_8bit	[test] add and deploy new benchmark	2024-06-02 14:27:02 -07:00
signal_gen	…
syn_spram_4x1	…
test_mode_low	…
test_modes	…
two_dff_inv_rst	[benchmark] syntax	2023-01-18 18:34:24 -08:00