tangxifan d1e951e52e [test] debugging		2023-01-24 17:57:34 -08:00
..
dont_care_bits	Changed HDL files reading to be as a single compilation unit in yosys_vpr flow for Verific mode. Changed '' variable to 'read_verilog ' in yosys template scripts. Updated task configs accordingly.	2022-01-17 13:21:29 +05:00
generate_bitstream	[test] now reduce the size for ql memory bank from 96x96 to 72x72; 96x96 requires >15G memory which exceeds github runner machine's RAM limit	2022-09-01 20:10:29 -07:00
load_external_architecture_bitstream/config	[test] update arch bitstream and force a pin placement for the test case where external bistream is fixed	2022-09-20 14:14:18 -07:00
overload_dsp_mode_bit/config	[test] debugging	2023-01-24 17:57:34 -08:00
overload_mux_default_path/config	Changed HDL files reading to be as a single compilation unit in yosys_vpr flow for Verific mode. Changed '' variable to 'read_verilog ' in yosys template scripts. Updated task configs accordingly.	2022-01-17 13:21:29 +05:00
repack_wire_lut/config	[Test] bug fix	2021-10-30 16:50:57 -07:00
repack_wire_lut_strong/config	[script] add missing files	2022-09-29 16:14:38 -07:00
report_bitstream_distribution	Changed HDL files reading to be as a single compilation unit in yosys_vpr flow for Verific mode. Changed '' variable to 'read_verilog ' in yosys template scripts. Updated task configs accordingly.	2022-01-17 13:21:29 +05:00
write_io_mapping/config	Changed HDL files reading to be as a single compilation unit in yosys_vpr flow for Verific mode. Changed '' variable to 'read_verilog ' in yosys template scripts. Updated task configs accordingly.	2022-01-17 13:21:29 +05:00