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and_k6_frac.openfpga
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add a microbenchmark `and_latch` to test LUTs in wired mode
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2020-03-11 10:40:59 -06:00 |
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and_k6_frac_adder_chain.openfpga
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fix bugs in flow manager on default compress routing problems
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2020-03-22 15:26:15 -06:00 |
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and_k6_frac_adder_chain_mem16K.openfpga
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bug fixed for heterogeneous block instances in top module
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2020-03-24 17:39:26 -06:00 |
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and_k6_frac_tileable.openfpga
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add all the test cases considering tileable, carry chain, direct connection and memory blocks
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2020-03-27 13:58:35 -06:00 |
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and_k6_frac_tileable_adder_chain.openfpga
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add all the test cases considering tileable, carry chain, direct connection and memory blocks
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2020-03-27 13:58:35 -06:00 |
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and_k6_frac_tileable_adder_chain_mem16K.openfpga
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add all the test cases considering tileable, carry chain, direct connection and memory blocks
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2020-03-27 13:58:35 -06:00 |
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and_k6_frac_tileable_adder_chain_mem16K_aib.openfpga
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relax asseration to allow AIB (non-I/O) blocks on the side of FPGA fabrics
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2020-03-27 19:07:34 -06:00 |
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and_k6_frac_tileable_adder_chain_mem16K_multi_io_capacity.openfpga
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debugging multiple io_types; bug fixed to support I/Os in more flexible location of FPGA fabric
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2020-03-27 16:03:42 -06:00 |
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and_k6_frac_tileable_adder_chain_mem16K_reduced_io.openfpga
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added FPGA architecture with I/Os on the left and right sides
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2020-04-01 15:46:38 -06:00 |
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and_k6_frac_tileable_adder_chain_wide_mem16K.openfpga
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add architecture examples on wide memory blocks (width=2). tileable routing is working
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2020-03-28 15:41:26 -06:00 |
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and_k6_frac_tileable_thru_channel_adder_chain_mem16K.openfpga
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add all the test cases considering tileable, carry chain, direct connection and memory blocks
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2020-03-27 13:58:35 -06:00 |
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and_latch_k6_frac.openfpga
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debugging multi-source lb router
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2020-03-12 20:42:41 -06:00 |
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and_latch_k6_frac_tileable.openfpga
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add all the test cases considering tileable, carry chain, direct connection and memory blocks
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2020-03-27 13:58:35 -06:00 |
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and_latch_k6_frac_tileable_adder_chain.openfpga
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add all the test cases considering tileable, carry chain, direct connection and memory blocks
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2020-03-27 13:58:35 -06:00 |
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and_latch_k6_frac_tileable_adder_chain_mem16K.openfpga
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add all the test cases considering tileable, carry chain, direct connection and memory blocks
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2020-03-27 13:58:35 -06:00 |
