tangxifan 32c74ad811 added FPGA architecture with I/Os on the left and right sides		2020-04-01 15:46:38 -06:00
..
src	add comments to explain the memory organization in the top-level module	2020-04-01 11:05:30 -06:00
test_blif	add missing files for micro benchmarks	2020-03-20 11:08:55 -06:00
test_openfpga_arch	relax I/O circuit model checking to fit AIB interface. Adapt testbench generation for multiple types of I/O pads	2020-03-27 20:09:50 -06:00
test_script	added FPGA architecture with I/Os on the left and right sides	2020-04-01 15:46:38 -06:00
test_vpr_arch	added FPGA architecture with I/Os on the left and right sides	2020-04-01 15:46:38 -06:00
CMakeLists.txt	add simulation ini file writer	2020-02-27 18:01:47 -07:00