tangxifan 60dd37e086 remove simulation settings from openfpga arch XML ... update travis to split CI tests fix errors in travis configuration fixing travis errors in scripts keep fixing travis fix travis on build.sh bug fixing in travis CI bug fix in travis regression test run fixing bugs in the travis scripts bug fix in travis script: remove common.sh in regression test call keep bug fixing in travis		2020-06-11 19:31:17 -06:00
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OpenFPGAShellScripts	update all the templates and regression test cases with simulation settings	2020-06-11 19:31:16 -06:00
SpiceNetlists	Moved spice and verilog netlist folder location	2019-08-17 01:49:49 -06:00
VerilogNetlists	update arch to support reset signal for SRAm	2020-06-11 19:31:14 -06:00
arch	bug fixed in k6_n10_40 architecture	2020-06-11 19:31:15 -06:00
benchmarks	start using counter benchmark in regression tests	2020-06-11 19:31:15 -06:00
docs	Added first draft of fpga_task script	2019-08-09 00:17:06 -06:00
misc	Fixed modelsim include references	2020-06-11 19:28:13 -06:00
openfpga_arch	remove simulation settings from openfpga arch XML	2020-06-11 19:31:17 -06:00
openfpga_simulation_settings	add example simulation setting for openfpga flow	2020-06-11 19:31:15 -06:00
scripts	Added support for simulation setting file in the task flow	2020-06-11 19:28:13 -06:00
tasks	update all the templates and regression test cases with simulation settings	2020-06-11 19:31:16 -06:00
tech	Added Power Model Files	2019-08-19 18:55:23 -06:00
.gitignore	Added first draft of fpga_task script	2019-08-09 00:17:06 -06:00