tangxifan 27caeb1d1f [Arch] Patched VPR arch		2022-01-02 20:47:22 -08:00
..
arch_bitstreams	[Architecture] Update external bitstream	2020-09-25 21:30:59 -06:00
benchmarks	[Benchmark] Add pipelined multiplier benchmark to test DSP block with registers	2022-01-02 20:16:59 -08:00
docs	Added first draft of fpga_task script	2019-08-09 00:17:06 -06:00
fabric_keys	[Arch] Add an example fabric key that models a shift-register-based QuickLogic memory bank using custom chain organization	2021-10-11 09:49:22 -07:00
misc	Updating yosys-plugin compilation to create command synth_ql instead of synth_quicklogic. This is done to surpass the assertion failure	2021-11-12 01:46:06 -08:00
openfpga_arch	[Flow] Add openfpga arch for DSP with registers	2022-01-02 19:59:33 -08:00
openfpga_cell_library	Merge branch 'master' of https://github.com/lnis-uofu/OpenFPGA into upstream	2021-10-31 11:51:34 -07:00
openfpga_shell_scripts	Merge branch 'master' of https://github.com/lnis-uofu/OpenFPGA into upstream	2021-10-31 11:51:34 -07:00
openfpga_simulation_settings	[Script] Bug fix in slow clock frequency in shift register chain contraints	2021-10-06 16:49:01 -07:00
openfpga_yosys_techlib	[Script] Add dff with active-low async reset to default yosys tech lib	2021-07-02 11:17:43 -06:00
regression_test_scripts	[Test] Add new test case (DSP with registers) into FPGA-Verilog regression tests	2022-01-02 20:21:58 -08:00
scripts	Merge remote-tracking branch 'upstream/master' into update_from_upstream	2021-11-18 00:00:55 +05:00
tasks	[Flow] Patch new test case	2022-01-02 20:20:36 -08:00
tech	Added Power Model Files	2019-08-19 18:55:23 -06:00
vpr_arch	[Arch] Patched VPR arch	2022-01-02 20:47:22 -08:00
.gitignore	Added first draft of fpga_task script	2019-08-09 00:17:06 -06:00