tangxifan 1a6f096393 [test] deploy the new test to fpga bitstream regression tests		2022-09-21 15:54:52 -07:00
..
arch_bitstreams	[Architecture] Update external bitstream	2020-09-25 21:30:59 -06:00
benchmarks	[benchmark] add a new benchmark test the mapping of LUT + adder pairs	2022-09-21 15:47:04 -07:00
docs	Added first draft of fpga_task script	2019-08-09 00:17:06 -06:00
fabric_keys	[Arch] Add an example fabric key that models a shift-register-based QuickLogic memory bank using custom chain organization	2021-10-11 09:49:22 -07:00
misc	[Script] Support simplified rewriting for Yosys on output verilog	2022-02-18 14:54:39 -08:00
openfpga_arch	[test] fixed a bug	2022-09-20 18:12:23 -07:00
openfpga_cell_library	[arch] add arch that supports negative edge triggered flip-flop	2022-05-09 16:32:01 +08:00
openfpga_shell_scripts	[engine] fixed a few bugs	2022-09-12 16:50:32 -07:00
openfpga_simulation_settings	[Script] Bug fix in slow clock frequency in shift register chain contraints	2021-10-06 16:49:01 -07:00
openfpga_yosys_techlib	[arch] fixed a few bugs	2022-05-09 17:22:48 +08:00
regression_test_scripts	[test] deploy the new test to fpga bitstream regression tests	2022-09-21 15:54:52 -07:00
scripts	[script] add a python script for users to visualize the I/O sequence	2022-09-16 10:49:10 -07:00
tasks	[test] a new test case to validate the lut+adder pair in repacker	2022-09-21 15:53:59 -07:00
tech	Added Power Model Files	2019-08-19 18:55:23 -06:00
vpr_arch	[arch] fixed a bug	2022-09-20 15:47:15 -07:00
.gitignore	Added first draft of fpga_task script	2019-08-09 00:17:06 -06:00