tangxifan 037c7e5c43 adapt top-level function for analysis SDC writer		2020-03-02 17:58:44 -07:00
..
annotation	move simulation setting annotation to a separated source file	2020-02-29 15:19:02 -07:00
base	adapt top-level function for analysis SDC writer	2020-03-02 17:58:44 -07:00
fabric	bug fixed for io location mapping	2020-02-28 14:46:01 -07:00
fpga_bitstream	fixed critical bugs in bitstream generation and now we pass microbenchmarks	2020-02-28 16:45:50 -07:00
fpga_sdc	adapt top-level function for analysis SDC writer	2020-03-02 17:58:44 -07:00
fpga_verilog	start verification and bug fixing	2020-02-28 14:29:01 -07:00
mux_lib	add mux library builder	2020-02-12 14:58:23 -07:00
repack	debugged LUT bitstream	2020-02-26 11:42:18 -07:00
tile_direct	tile direct supports inter-column/inter-row direct connections	2020-02-15 13:42:53 -07:00
utils	bug fixed for clock names	2020-02-27 16:51:55 -07:00
vpr_wrapper	add rr_segment binding to circuit model	2020-02-12 11:21:40 -07:00
ctag_src.sh	add ctags script to index openfpga source files	2020-01-24 10:15:16 -07:00
main.cpp	bring pnr sdc generator online and fixed minor bugs in bitstream writing	2020-02-28 11:14:50 -07:00