Tarachand Pagarani ce76c58422 add shift register test case		2021-03-05 09:06:05 -08:00
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MCNC_Verilog	Added first draft of fpga_task script	2019-08-09 00:17:06 -06:00
mcnc_big20	add explicit port mapping support in testbenches; remove dangling ports in benchmarks	2019-11-02 23:03:47 -06:00
micro_benchmark	[Benchmark] Add micro benchmark for FIR filter	2021-02-18 19:37:44 -07:00
pipelined_8bit_adder	passing regression test on dpram benchmarks	2019-11-07 14:57:46 -07:00
quicklogic_tests	add shift register test case	2021-03-05 09:06:05 -08:00
test_modes	add single mode test case to regression test. debugging now	2019-10-28 15:57:17 -06:00