tangxifan e61857aa2b Merge branch 'master' into ganesh_dev		2021-03-11 19:17:02 -07:00
..
arch_bitstreams	[Architecture] Update external bitstream	2020-09-25 21:30:59 -06:00
benchmarks	add shift register test case	2021-03-05 09:06:05 -08:00
docs	Added first draft of fpga_task script	2019-08-09 00:17:06 -06:00
fabric_keys	[Architecture] Add example fabric key using multiple regions	2020-09-29 14:14:50 -06:00
misc	[Script] Split rewrite yosys scripts into two runs because yosys cannot output consistent verilog files using 'design -reset'	2021-03-10 13:56:35 -07:00
openfpga_arch	[Arch] Comment out dummy circuit model for adder_lut model in QL's cell sim library. which is no longer used in verification	2021-03-10 22:45:19 -07:00
openfpga_cell_library	[HDL] Patch the superLUT HDL code to be consistent with (qlf_k4n8_sim.v)[https://github.com/lnsharma/yosys/blob/add_qlf_k4n8_dev/techlibs/quicklogic/qlf_k4n8_cells_sim.v]	2021-03-11 15:23:14 -07:00
openfpga_shell_scripts	Merge branch 'master' into default_net_type	2021-03-01 08:38:58 -07:00
openfpga_simulation_settings	[Arch] Add simulation setting for 8-clock architectures	2021-02-22 11:10:03 -07:00
regression_test_scripts	Merge branch 'master' into default_net_type	2021-03-01 08:38:58 -07:00
scripts	[Flow] Support multiple iterations in rewriting yosys scripts	2021-03-10 14:10:35 -07:00
tasks	Merge branch 'master' into ganesh_dev	2021-03-11 19:17:02 -07:00
tech	Added Power Model Files	2019-08-19 18:55:23 -06:00
vpr_arch	[Arch] Patched superLUT architecture example when trying adder8 synthesis script	2021-02-23 19:00:27 -07:00
.gitignore	Added first draft of fpga_task script	2019-08-09 00:17:06 -06:00